Purpose This paper aims to improve the life of the printed circuit boards (PCB) used in computers based on modal analysis by increasing the natural frequency of the PCB assembly. Design/methodology/approach In this work, through experiments and numerical simulations, an attempt has been made to increase the fundamental natural frequency of the PCB assembly as high as practically achievable so as to minimize the impacts of dynamic loads acting on it. An optimization tool in the finite element software (ANSYS) was used to search the specified design space for the optimal support location of the six fastening screws. Findings It is observed that by changing the support locations based on the optimization results the fundamental natural frequency can be raised up to 51.1% and the same is validated experimentally. Research limitations/implications Manufacturers of PCBs used in computers fix the support locations based on symmetric feature of the board not on the dynamic behavior of the assembly. This work might lead manufacturers to redesign the location of other surface mount components. Practical implications This work provides guidelines for PCB manufacturers to finalize their support locating points which will improve the dynamic characteristics of the PCB assembly during its functioning. Originality/value This study provides a novel method to improve the life of PCB based on support locations optimization which includes majority of the surface mount components that contributes to the total mass the PCB assembly.
{"title":"A modal analysis based optimal mounting support locations of a printed circuit board","authors":"Muthuram N., S. S.","doi":"10.1108/mi-07-2022-0126","DOIUrl":"https://doi.org/10.1108/mi-07-2022-0126","url":null,"abstract":"\u0000Purpose\u0000This paper aims to improve the life of the printed circuit boards (PCB) used in computers based on modal analysis by increasing the natural frequency of the PCB assembly.\u0000\u0000\u0000Design/methodology/approach\u0000In this work, through experiments and numerical simulations, an attempt has been made to increase the fundamental natural frequency of the PCB assembly as high as practically achievable so as to minimize the impacts of dynamic loads acting on it. An optimization tool in the finite element software (ANSYS) was used to search the specified design space for the optimal support location of the six fastening screws.\u0000\u0000\u0000Findings\u0000It is observed that by changing the support locations based on the optimization results the fundamental natural frequency can be raised up to 51.1% and the same is validated experimentally.\u0000\u0000\u0000Research limitations/implications\u0000Manufacturers of PCBs used in computers fix the support locations based on symmetric feature of the board not on the dynamic behavior of the assembly. This work might lead manufacturers to redesign the location of other surface mount components.\u0000\u0000\u0000Practical implications\u0000This work provides guidelines for PCB manufacturers to finalize their support locating points which will improve the dynamic characteristics of the PCB assembly during its functioning.\u0000\u0000\u0000Originality/value\u0000This study provides a novel method to improve the life of PCB based on support locations optimization which includes majority of the surface mount components that contributes to the total mass the PCB assembly.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42936601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this study is to investigate the ammonia sensing performance of polyaniline/polyethylene oxide (PANI/PEO) and polyaniline/polyethylene oxide/zinc oxide (PANI/PEO-ZnO) composite nanofibers at room temperature. Design/methodology/approach Gas sensor structures were fabricated using micro-fabrication techniques. First, onto the SiO2 wafer, gold electrodes were fabricated via thermal evaporation. PANI/PEO nanofibers were produced by the electrospinning method and the ZnO layer was deposited by RF magnetron sputtering on the electrospun nanofibers as a sensing layer. Fourier transform infrared spectroscopy (FTIR) and scanning electron microscopy (SEM) were performed for characterization analysis of nanofibers. After all, gas sensing analysis of PANI/PEO and PANI/PEO/ZnO nanofibers was performed using an experimental setup at room temperature conditions. Findings FTIR analysis confirms the presence of functional groups of PANI, PEO and ZnO in nanofiber structure. SEM images demonstrate beads-free, thinner and smooth nanofibers with ZnO contribution to electrospun PANI/PEO nanofibers. Moreover, according to the gas sensing results, the PANI/PEO nanofibers exhibit 115 and 457 s response time and recovery time, respectively. However, the PANI/PEO/ZnO nanofibers exhibit 245 and 153 s response time and recovery time, respectively. Originality/value In this study, ZnO was deposited via RF magnetron sputtering techniques on PANI/PEO nanofibers as a different approach instead of in situ polymerization, to investigate and enhance the sensor response and recovery time of the PANI/PEO/ZnO and PANI/PEO composite nanofibers to ammonia. These results indicated that ZnO can enhance the sensing properties of conductive polymer based resistive sensors.
{"title":"A chemosensitive based ammonia gas sensor with PANI/PEO- ZnO nanofiber composites sensing layer","authors":"Gözde Konuk Ege, Ö. Akay, H. Yüce","doi":"10.1108/mi-09-2022-0161","DOIUrl":"https://doi.org/10.1108/mi-09-2022-0161","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to investigate the ammonia sensing performance of polyaniline/polyethylene oxide (PANI/PEO) and polyaniline/polyethylene oxide/zinc oxide (PANI/PEO-ZnO) composite nanofibers at room temperature.\u0000\u0000\u0000Design/methodology/approach\u0000Gas sensor structures were fabricated using micro-fabrication techniques. First, onto the SiO2 wafer, gold electrodes were fabricated via thermal evaporation. PANI/PEO nanofibers were produced by the electrospinning method and the ZnO layer was deposited by RF magnetron sputtering on the electrospun nanofibers as a sensing layer. Fourier transform infrared spectroscopy (FTIR) and scanning electron microscopy (SEM) were performed for characterization analysis of nanofibers. After all, gas sensing analysis of PANI/PEO and PANI/PEO/ZnO nanofibers was performed using an experimental setup at room temperature conditions.\u0000\u0000\u0000Findings\u0000FTIR analysis confirms the presence of functional groups of PANI, PEO and ZnO in nanofiber structure. SEM images demonstrate beads-free, thinner and smooth nanofibers with ZnO contribution to electrospun PANI/PEO nanofibers. Moreover, according to the gas sensing results, the PANI/PEO nanofibers exhibit 115 and 457 s response time and recovery time, respectively. However, the PANI/PEO/ZnO nanofibers exhibit 245 and 153 s response time and recovery time, respectively.\u0000\u0000\u0000Originality/value\u0000In this study, ZnO was deposited via RF magnetron sputtering techniques on PANI/PEO nanofibers as a different approach instead of in situ polymerization, to investigate and enhance the sensor response and recovery time of the PANI/PEO/ZnO and PANI/PEO composite nanofibers to ammonia. These results indicated that ZnO can enhance the sensing properties of conductive polymer based resistive sensors.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47433858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tian Huang, Gui-Sheng Gan, Cong Liu, P. Ma, Yongchong Ma, Zheng Tang, Dayong Cheng, Xin Liu, Kun Tian
Purpose This paper aims to investigate the effects of different ultrasonic-assisted loading degrees on the microstructure, mechanical properties and the fracture morphology of Cu/Zn+15%SAC0307+15%Cu/Al solder joints. Design/methodology/approach A new method in which 45 μm Zn particles were mixed with 15% 500 nm Cu particles and 15% 500 nm SAC0307 particles as solders (SACZ) and five different ultrasonic loading degrees were applied for realizing the soldering between Cu and Al at 240 °C and 8 MPa. Then, SEM was used to observe and analyze the soldering seam, interface microstructure and fracture morphology; the structural composition was determined by EDS; the phase of the soldering seam was characterized by XRD; and a PTR-1102 bonding tester was adopted to test the average shear strength. Findings The results manifest that Al–Zn solid solution is formed on the Al side of the Cu/SACZ/Al joints, while the interface IMC (Cu5Zn8) is formed on the Cu side of the Cu/SACZ/Al joints. When single ultrasonic was used in soldering, the interface IMC (Cu5Zn8) gradually thickens with the increase of ultrasonic degree. It is observed that the proportion of Zn or ZnO areas in solders decreases, and the proportion of Cu–Zn compound areas increases with the variation of ultrasonic degree. The maximum shear strength of joint reaches 46.01 MPa when the dual ultrasonic degree is 60°. The fracture position of the joint gradually shifts from the Al side interface to the solders and then to the Cu side interface. Originality/value The mechanism of ultrasonic action on micro-nanoparticles is further studied. By using different ultrasonic loading degrees to realize Cu/Al soldering, it is believed that the understandings gained in this study may offer some new insights for the development of low-temperature soldering methodology for heterogeneous materials.
{"title":"Properties of Cu/Zn+15%SAC0307+15%Cu/Al joints by different ultrasonic-assisted degrees","authors":"Tian Huang, Gui-Sheng Gan, Cong Liu, P. Ma, Yongchong Ma, Zheng Tang, Dayong Cheng, Xin Liu, Kun Tian","doi":"10.1108/mi-08-2022-0154","DOIUrl":"https://doi.org/10.1108/mi-08-2022-0154","url":null,"abstract":"\u0000Purpose\u0000This paper aims to investigate the effects of different ultrasonic-assisted loading degrees on the microstructure, mechanical properties and the fracture morphology of Cu/Zn+15%SAC0307+15%Cu/Al solder joints.\u0000\u0000\u0000Design/methodology/approach\u0000A new method in which 45 μm Zn particles were mixed with 15% 500 nm Cu particles and 15% 500 nm SAC0307 particles as solders (SACZ) and five different ultrasonic loading degrees were applied for realizing the soldering between Cu and Al at 240 °C and 8 MPa. Then, SEM was used to observe and analyze the soldering seam, interface microstructure and fracture morphology; the structural composition was determined by EDS; the phase of the soldering seam was characterized by XRD; and a PTR-1102 bonding tester was adopted to test the average shear strength.\u0000\u0000\u0000Findings\u0000The results manifest that Al–Zn solid solution is formed on the Al side of the Cu/SACZ/Al joints, while the interface IMC (Cu5Zn8) is formed on the Cu side of the Cu/SACZ/Al joints. When single ultrasonic was used in soldering, the interface IMC (Cu5Zn8) gradually thickens with the increase of ultrasonic degree. It is observed that the proportion of Zn or ZnO areas in solders decreases, and the proportion of Cu–Zn compound areas increases with the variation of ultrasonic degree. The maximum shear strength of joint reaches 46.01 MPa when the dual ultrasonic degree is 60°. The fracture position of the joint gradually shifts from the Al side interface to the solders and then to the Cu side interface.\u0000\u0000\u0000Originality/value\u0000The mechanism of ultrasonic action on micro-nanoparticles is further studied. By using different ultrasonic loading degrees to realize Cu/Al soldering, it is believed that the understandings gained in this study may offer some new insights for the development of low-temperature soldering methodology for heterogeneous materials.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47430079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this paper is to propose a DC-port voltage balance strategy realizing it by logic combination modulation (LCM). This voltage balance strategy is brief and high efficient, which can be used in many power electronic devices adopting the cascaded H-bridge rectifier (CHBR) such as power electronic transformer (PET). Design/methodology/approach The CHBR is typically as a core component in the power electronic devices to implement the voltage or current conversion. The modulation method presented here is aiming to solve the voltage imbalance problem occurred in the CHBR with more stable work station and higher reliability in ordinary operating conditions. In particular, by changing the switch states smoothly and quickly, the DC-port voltage can be controlled as the ideal value even one of the modules in CHBR is facing the load-removed problem. Findings By using the voltage balance strategy of LCM, the problem of voltage imbalance occurring in three-phase cascaded rectifiers has been solved properly. With the lower modulation depth, the efficiency of the strategy is shown to be better and stronger. The strategy can work reliably and quickly no matter facing the problem as load-removed change or the ordinary operating conditions. Research limitations/implications The limitation of the proposed DC-port voltage balance strategy is calculated and proved, in a three-module CHBR, the LCM could balance the DC-port voltage while one module facing the load-removed situation under 0.83 modulation depth. Originality/value This paper provides a useful and particular voltage balance strategy which can be used in the topology of three-phase cascaded rectifier. The value of the strategy is that a brief and reliable voltage balance method in the power electronic devices can be achieved. What is more, facing the problem, such as load-removed, in outport, the strategy can response quickly with no switch jump and switch frequency rising.
{"title":"DC-port voltage balance strategy for three-phase cascaded H-bridge rectifier based on logic combination modulation","authors":"Mingxiao Dai, Xu Peng, Xiao Liang, Xinyu Zhu, Xiaohan Liu, Xijun Liu, Pengcheng Han, Chao Wu","doi":"10.1108/mi-07-2022-0118","DOIUrl":"https://doi.org/10.1108/mi-07-2022-0118","url":null,"abstract":"Purpose The purpose of this paper is to propose a DC-port voltage balance strategy realizing it by logic combination modulation (LCM). This voltage balance strategy is brief and high efficient, which can be used in many power electronic devices adopting the cascaded H-bridge rectifier (CHBR) such as power electronic transformer (PET). Design/methodology/approach The CHBR is typically as a core component in the power electronic devices to implement the voltage or current conversion. The modulation method presented here is aiming to solve the voltage imbalance problem occurred in the CHBR with more stable work station and higher reliability in ordinary operating conditions. In particular, by changing the switch states smoothly and quickly, the DC-port voltage can be controlled as the ideal value even one of the modules in CHBR is facing the load-removed problem. Findings By using the voltage balance strategy of LCM, the problem of voltage imbalance occurring in three-phase cascaded rectifiers has been solved properly. With the lower modulation depth, the efficiency of the strategy is shown to be better and stronger. The strategy can work reliably and quickly no matter facing the problem as load-removed change or the ordinary operating conditions. Research limitations/implications The limitation of the proposed DC-port voltage balance strategy is calculated and proved, in a three-module CHBR, the LCM could balance the DC-port voltage while one module facing the load-removed situation under 0.83 modulation depth. Originality/value This paper provides a useful and particular voltage balance strategy which can be used in the topology of three-phase cascaded rectifier. The value of the strategy is that a brief and reliable voltage balance method in the power electronic devices can be achieved. What is more, facing the problem, such as load-removed, in outport, the strategy can response quickly with no switch jump and switch frequency rising.","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135583581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this study is to investigate the reliability of flex-on-board (FOB) interconnection connected with an anisotropic conductive paste (ACP), which is prepared by dispersing nickel balls in the epoxy-curing system. Design/methodology/approach Differential scanning calorimetry was used to evaluate the curing characteristics of the paste. And the contact resistances of bonding joints and 90º peel adhesion were tested before and after high temperature and high humidity test (85°C, 85% humidity), thermal cycling (−45°C∼125°C, 30min/cycle) and pressure cooker test (PCT, 121°C, 100% humidity 2 atm) to evaluate the flex on board (FOB) interconnection reliability. Findings It is found that FOB test vehicles have been successfully bonded by using ACP for the first time. And the ACP bonding joint of FOB has good reliability and can meet the requirements of FOB interconnection. Compared with conventional anisotropic conductive film (ACF), this ACP interconnection provides higher adhesion strength, higher joint current carrying capability and higher reliability performance and lower cost for FOB interconnection. Originality/value ACP is applied in the interconnection of FOB. It has the higher reliability performance and lower cost for than the conventional ACF.
{"title":"The preparation of anisotropic conductive paste and its application in FOB interconnection","authors":"Xiong-hui Cai, A. Zhai, Chenglong Zhou, K. Paik","doi":"10.1108/mi-11-2022-0187","DOIUrl":"https://doi.org/10.1108/mi-11-2022-0187","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to investigate the reliability of flex-on-board (FOB) interconnection connected with an anisotropic conductive paste (ACP), which is prepared by dispersing nickel balls in the epoxy-curing system.\u0000\u0000\u0000Design/methodology/approach\u0000Differential scanning calorimetry was used to evaluate the curing characteristics of the paste. And the contact resistances of bonding joints and 90º peel adhesion were tested before and after high temperature and high humidity test (85°C, 85% humidity), thermal cycling (−45°C∼125°C, 30min/cycle) and pressure cooker test (PCT, 121°C, 100% humidity 2 atm) to evaluate the flex on board (FOB) interconnection reliability.\u0000\u0000\u0000Findings\u0000It is found that FOB test vehicles have been successfully bonded by using ACP for the first time. And the ACP bonding joint of FOB has good reliability and can meet the requirements of FOB interconnection. Compared with conventional anisotropic conductive film (ACF), this ACP interconnection provides higher adhesion strength, higher joint current carrying capability and higher reliability performance and lower cost for FOB interconnection.\u0000\u0000\u0000Originality/value\u0000ACP is applied in the interconnection of FOB. It has the higher reliability performance and lower cost for than the conventional ACF.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46659270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Light emitting diode (LED) has been the best resource for commercial and industrial lighting applications. However, thermal management in high power LEDs is a major challenge in which the thermal resistance (Rth) and rise in junction temperature (TJ) are critical parameters. The purpose of this work is to evaluate the Rth and Tj of the LED attached with the modified heat transfer area of the heatsink to improve thermal management. Design/methodology/approach This paper deals with the design of metal substrate for heatsink applications where the surface area of the heatsink is modified. Numerical simulation on heat distribution proved the influence of the design aspects and surface area of heatsink. Findings TJ was low for outward step design when compared to flat heatsink design (ΔT ∼ 38°C) because of increase in surface area from 1,550 mm2 (flat) to 3,076 mm2 (outward step). On comparison with inward step geometry, the TJ value was low for outward step configuration (ΔTJ ∼ 6.6°C), which is because of efficient heat transfer mechanism with outward step design. The observed results showed that outward step design performs well for LED testing by reducing both Rth and TJ for different driving currents. Originality/value This work is authors’ own design and also has the originality for the targeted application. To the best of the authors’ knowledge, the proposed design has not been tried before in the electronic or LED applications.
{"title":"Influence of extended surface area of heatsink on heat transfer: design and analysis","authors":"Shanmugan Subramani, M. Devarajan","doi":"10.1108/mi-09-2022-0171","DOIUrl":"https://doi.org/10.1108/mi-09-2022-0171","url":null,"abstract":"\u0000Purpose\u0000Light emitting diode (LED) has been the best resource for commercial and industrial lighting applications. However, thermal management in high power LEDs is a major challenge in which the thermal resistance (Rth) and rise in junction temperature (TJ) are critical parameters. The purpose of this work is to evaluate the Rth and Tj of the LED attached with the modified heat transfer area of the heatsink to improve thermal management.\u0000\u0000\u0000Design/methodology/approach\u0000This paper deals with the design of metal substrate for heatsink applications where the surface area of the heatsink is modified. Numerical simulation on heat distribution proved the influence of the design aspects and surface area of heatsink.\u0000\u0000\u0000Findings\u0000TJ was low for outward step design when compared to flat heatsink design (ΔT ∼ 38°C) because of increase in surface area from 1,550 mm2 (flat) to 3,076 mm2 (outward step). On comparison with inward step geometry, the TJ value was low for outward step configuration (ΔTJ ∼ 6.6°C), which is because of efficient heat transfer mechanism with outward step design. The observed results showed that outward step design performs well for LED testing by reducing both Rth and TJ for different driving currents.\u0000\u0000\u0000Originality/value\u0000This work is authors’ own design and also has the originality for the targeted application. To the best of the authors’ knowledge, the proposed design has not been tried before in the electronic or LED applications.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41286616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Kim, HyeongIl Jeon, G. Kim, W. Bang, JinYoung Khim
Purpose The purpose of this study is to offer the advanced leadless leadframe package which achieve small form factor and high thermal and electrical performance, according to the continuous market requirement. Because of demand and trends, new package structures that can accommodate many pins (I/Os) while maintaining the excellent thermal and electrical properties of the leadframe package was studied. Different from conventional leadframe and laminate packages, it must have the large-exposed pad for thermal dissipation and design flexibility to deploy signal, ground and power selectively. Design/methodology/approach In this study, the routable molded leadframe (rtMLF®) package applying the pre-resin MLF substrate was introduced. The structural advantages, in terms of design flexibility, were checked by adopting the specific electrical feature. Also, the excellence of thermal and electrical performance was confirmed by simulation. The sample was manufactured, and its package robustness was validated by reliability test. Findings rtMLF package that enables one layer substrate but routable pattern on top layer differently from existing leadframe package was developed and studied if it overcome the limitations of leadframe and laminate products. Asymmetric land layout was designed and special features to keep electrical interference was applied to prove design flexibility. The thermal and electrical simulation has been executed to check the advantages. And key differentiations were identified. Finally, actual sample was manufactured, and structural robustness was validated by package level and board level reliability. Originality/value The differentiation of new semiconductor package was introduced and its excellence was verified by electrical and thermal simulation as well as reliability test. It is expected to be adopted for alternative solutions not covered by the existing products.
{"title":"The advanced leadless leadframe package and its characteristics","authors":"B. Kim, HyeongIl Jeon, G. Kim, W. Bang, JinYoung Khim","doi":"10.1108/mi-10-2022-0175","DOIUrl":"https://doi.org/10.1108/mi-10-2022-0175","url":null,"abstract":"\u0000Purpose\u0000The purpose of this study is to offer the advanced leadless leadframe package which achieve small form factor and high thermal and electrical performance, according to the continuous market requirement. Because of demand and trends, new package structures that can accommodate many pins (I/Os) while maintaining the excellent thermal and electrical properties of the leadframe package was studied. Different from conventional leadframe and laminate packages, it must have the large-exposed pad for thermal dissipation and design flexibility to deploy signal, ground and power selectively.\u0000\u0000\u0000Design/methodology/approach\u0000In this study, the routable molded leadframe (rtMLF®) package applying the pre-resin MLF substrate was introduced. The structural advantages, in terms of design flexibility, were checked by adopting the specific electrical feature. Also, the excellence of thermal and electrical performance was confirmed by simulation. The sample was manufactured, and its package robustness was validated by reliability test.\u0000\u0000\u0000Findings\u0000rtMLF package that enables one layer substrate but routable pattern on top layer differently from existing leadframe package was developed and studied if it overcome the limitations of leadframe and laminate products. Asymmetric land layout was designed and special features to keep electrical interference was applied to prove design flexibility. The thermal and electrical simulation has been executed to check the advantages. And key differentiations were identified. Finally, actual sample was manufactured, and structural robustness was validated by package level and board level reliability.\u0000\u0000\u0000Originality/value\u0000The differentiation of new semiconductor package was introduced and its excellence was verified by electrical and thermal simulation as well as reliability test. It is expected to be adopted for alternative solutions not covered by the existing products.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47696388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hui Xiao, X. Guo, Fangzhou Chen, Weiwei Zhang, Hao Liu, Ze Chen, Jiahao Liu
Purpose Traditional nondestructive failure localization techniques are increasingly difficult to meet the requirements of high density and integration of system in package (SIP) devices in terms of resolution and accuracy. Time domain reflection (TDR) is recognized as a novel positioning analysis technology gradually being used in the electronics industry because of the good compatibility, high accuracy and high efficiency. However, there are limited reports focus on the application of TDR technology to SiP devices. Design/methodology/approach In this study, the authors used the TDR technique to locate the failure of SiP devices, and the results showed that the TDR technique can accurately locate the cracking of internal solder joints of SiP devices. Findings The measured transmission rate of electromagnetic wave signal was 9.56 × 107 m/s in the experimental SiP devices. In addition, the TDR technique successfully located the failure point, which was mainly caused by the cracking of the solder joint at the edge of the SiP device after 1,500 thermal cycles. Originality/value TDR technology is creatively applied to SiP device failure location, and quantitative analysis is realized.
{"title":"A failure location technology for SiP devices based on TDR nondestructive testing method","authors":"Hui Xiao, X. Guo, Fangzhou Chen, Weiwei Zhang, Hao Liu, Ze Chen, Jiahao Liu","doi":"10.1108/mi-09-2022-0168","DOIUrl":"https://doi.org/10.1108/mi-09-2022-0168","url":null,"abstract":"\u0000Purpose\u0000Traditional nondestructive failure localization techniques are increasingly difficult to meet the requirements of high density and integration of system in package (SIP) devices in terms of resolution and accuracy. Time domain reflection (TDR) is recognized as a novel positioning analysis technology gradually being used in the electronics industry because of the good compatibility, high accuracy and high efficiency. However, there are limited reports focus on the application of TDR technology to SiP devices.\u0000\u0000\u0000Design/methodology/approach\u0000In this study, the authors used the TDR technique to locate the failure of SiP devices, and the results showed that the TDR technique can accurately locate the cracking of internal solder joints of SiP devices.\u0000\u0000\u0000Findings\u0000The measured transmission rate of electromagnetic wave signal was 9.56 × 107 m/s in the experimental SiP devices. In addition, the TDR technique successfully located the failure point, which was mainly caused by the cracking of the solder joint at the edge of the SiP device after 1,500 thermal cycles.\u0000\u0000\u0000Originality/value\u0000TDR technology is creatively applied to SiP device failure location, and quantitative analysis is realized.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43895990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Polymer-based thermal interface materials (TIMs) are having pump out problem and could be resolved for reliable application. Solid-based interface materials have been suggested and reported. The purpose of this paper is suggesting thin film-based TIM to sustain the light-emiting diode (LED) performance and electronic device miniaturization. Design/methodology/approach Consequently, ZnO thin film at various thicknesses was prepared by chemical vapour deposition (CVD) method and tested their thermal behaviour using thermal transient analysis as solid TIM for high-power LED. Findings Low value in total thermal resistance (Rth-tot) was observed for ZnO thin film boundary condition than bare Al boundary condition. The measured interface (ZnO thin film) resistance {(Rth-bhs) thermal resistance of the interface layer (thin film) placed between metal core printed circuit board (MCPCB) board and Al substrates} was nearly equal to Ag paste boundary condition and showed low values for ZnO film prepared at 30 min process time measured at 700 mA. The TJ value of LED mounted on ZnO thin film (prepared at 30 min.) coated Al substrates was measured to be 74.8°C. High value in junction temperature difference (ΔTJ) of about 4.7°C was noticed with 30 min processed ZnO thin film when compared with Al boundary condition. Low correlated colour temperature and high luminous flux values of tested LED were also observed with ZnO thin film boundary condition (processed at 30 min) compared with both Al substrate and Ag paste boundary condition. Originality/value Overall, 30 min CVD processed ZnO thin film would be an alternative for commercial TIM to achieve efficient thermal management. This will increase the life span of the LED as the proposed material decreases the TJ values.
{"title":"CVD processed ZnO thin film as solid thermal interface material in electronic devices: thermal and optical performance of LED","authors":"Shanmugan Subramani, M. Devarajan","doi":"10.1108/mi-05-2022-0080","DOIUrl":"https://doi.org/10.1108/mi-05-2022-0080","url":null,"abstract":"\u0000Purpose\u0000Polymer-based thermal interface materials (TIMs) are having pump out problem and could be resolved for reliable application. Solid-based interface materials have been suggested and reported. The purpose of this paper is suggesting thin film-based TIM to sustain the light-emiting diode (LED) performance and electronic device miniaturization.\u0000\u0000\u0000Design/methodology/approach\u0000Consequently, ZnO thin film at various thicknesses was prepared by chemical vapour deposition (CVD) method and tested their thermal behaviour using thermal transient analysis as solid TIM for high-power LED.\u0000\u0000\u0000Findings\u0000Low value in total thermal resistance (Rth-tot) was observed for ZnO thin film boundary condition than bare Al boundary condition. The measured interface (ZnO thin film) resistance {(Rth-bhs) thermal resistance of the interface layer (thin film) placed between metal core printed circuit board (MCPCB) board and Al substrates} was nearly equal to Ag paste boundary condition and showed low values for ZnO film prepared at 30 min process time measured at 700 mA. The TJ value of LED mounted on ZnO thin film (prepared at 30 min.) coated Al substrates was measured to be 74.8°C. High value in junction temperature difference (ΔTJ) of about 4.7°C was noticed with 30 min processed ZnO thin film when compared with Al boundary condition. Low correlated colour temperature and high luminous flux values of tested LED were also observed with ZnO thin film boundary condition (processed at 30 min) compared with both Al substrate and Ag paste boundary condition.\u0000\u0000\u0000Originality/value\u0000Overall, 30 min CVD processed ZnO thin film would be an alternative for commercial TIM to achieve efficient thermal management. This will increase the life span of the LED as the proposed material decreases the TJ values.\u0000","PeriodicalId":49817,"journal":{"name":"Microelectronics International","volume":null,"pages":null},"PeriodicalIF":1.1,"publicationDate":"2023-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47290366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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