Iet Circuits Devices & Systems最新文献

A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S₁₁ and S₂₂ parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW.

An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and power-delay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.

Retraction: [Jiazheng Yuan, Zhuang Wang, Cheng Xu, Hongtian Li, Songyin Dai, Hongzhe Liu, Multi-vehicle group-aware data protection model based on differential privacy for autonomous sensor networks, IET Circuits, Devices & Systems 2022 (https://doi.org/10.1049/cds2.12140)].

The above article from IET Circuits, Devices & Systems, published online on 29 December 2022 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal's peer review standards and there is evidence that the peer revie process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.

The Internet of Things (IoT) is a self-configuring, intelligent system in which autonomous things connect to the Internet and communicate with each other. As ‘things’ are autonomous, it may raise privacy concerns. In this study, the authors describe the background of IoT systems and privacy and security measures, including (a) approaches to preserving privacy in IoT-based systems, (b) existing privacy solutions, and (c) recommending privacy models for different layers of IoT applications. Based on the results of our study, it is clear that new methods such as Blockchain, Machine Learning, Data Minimisation, and Data Encryption can greatly impact privacy issues to ensure security and privacy. Moreover, it makes sense that users can protect their personal information easier if there is fewer data to collect, store, and share by smart devices. Thus, this study proposes a machine learning-based data minimisation method that, in these networks, can be very beneficial for privacy-preserving.

In this work, the proposed model is developed by employing a smart metre design which is done by controlling and monitoring the system frequency. This model estimates the changes in the frequency in accordance to the loading conditions of the power system, overload or under load-conditions respectively. The estimated frequency is analysed by employing a smart metre design, which estimates the change in the system frequency caused by overload or under-load conditions and compared with a reference frequency value set by the load dispatching unit in the control server. In this analysis, the line responsible for the frequency change are being isolated from the rest of the system or given only based on the demand power as per the priority loads. The proposed model is equipped with an embedded realistic system set along with a synchronised network and central server by using a cloud computing approach as a test bed laboratory set up. The parameters of the electric power are based on load forecasting involved for setting the required reference frequency. The model is developed with a realistic approach by developing the prototype. The work employs both software and hardware modelling with cloud interface. A complete hardware demonstration rig is developed with a smart metre design and experimental results are studied and demonstrated using cloud interface.

Retraction: [Jun Mao, Jun Ma, Research on wavelet neural network PID control of maglev linear synchronous motor, IET Circuits, Devices & Systems 2022 (https://doi.org/10.1049/cds2.12136)].

The above article from IET Circuits, Devices & Systems, published online on 8 December 2022 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer review process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.

Polymer-dispersed liquid crystal automated quantification system for vision through polymer-dispersed liquid crystal double-glazed windows: Circuit implementation (PDLC)-windows played an essential role in providing a visual comfort for occupants in commercial buildings recently. PDLC windows adjust the visible transparency of the glazing to control the daylight accessed to internal environments. A former study proposed an algorithm to quantify the vision through the PDLC glazing in terms of image contrast. The quantification algorithm determines the minimum level of transparency that maintains a comfortable vision through the window. This study introduced the implementation of a real-time automated system that achieves the vision quantification process. Firstly, system on-chip was utilised to realise the quantification algorithm, including contrast estimation. Secondly, the contrast determination action was re-implemented using MATLAB, Cortex-A9 microcontroller, and Cyclone V field programmable gate array field programmable gate array-chip. The implemented systems were evaluated based on the latency, throughput, power consumption, and cost.

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase-frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage-controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase-frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage-controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed-forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide-by-47 and divide-by-48) that lacks a few extra flip-flops which save considerable power and improves the frequency difficulties of the multi-band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1-μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS-based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability.

In this correspondence, a mathematical model is developed for the efficient realisation of a generalised M × M polyphase parallel finite impulse response (FIR) filter structure composed of M parallel conventional decimator polyphase filters. Primarily, the proposed structure is designed in such a way that the benefit of coefficient symmetry property of linear-phase FIR filters can be availed without using the pre/post circuit blocks. A numerical example is also studied to validate the proposed structure. Furthermore, the delay-elements reduction approach is given to avoid the excessive usage of memory elements and the performance of the proposed structure is evaluated in terms of the number of delay elements $��\left(��D��\right)�$, adders $��\left(��A��\right)�$ and multipliers $��\left(��M��\right)�$. Compared to the traditional structures, our proposed structure is found to be more efficient in terms of $��M�$. Moreover, in contrast to the fast FIR algorithms, the proposed structure resolves the issues of additional requirements of the pre/post blocks and the absence of parallel structure with coefficient symmetry for higher prime values of M (i.e. M > 3). The synthesis result reveals that the proposed 37-tap filter (with M = 3 and 12-bit inputs) involves 30% less area-delay-product (ADP) per output and 33.05% less power per output compared to the most recent structure.