Iet Circuits Devices & Systems最新文献

To develop an optimised rehabilitation training system for various severity strokes in rats. The method provided feedback regarding the rat's measured position to a microprocessor, which adjusted the training speed accordingly and enables the rat to continuously exercise in the middle position of the ladder. This created a cyclic control system that provided various training intensities based on timely evaluations of the ladder-climbing capabilities of each rat, thus providing a suitable rehabilitation method for subjects with various stroke severities. The modified neurological severity score, rotarod and cerebral infarction volume results for the 60- and 90-min middle cerebral artery occlusion (MCAO) treadmill groups did not differ significantly from those of the control group. Conversely, the cerebral infarction volumes of the ladder-climbing rehabilitation groups in the 30-, 60-, and 90-min MCAO were all significantly lower than those of the control group (84.03 ± 23.24 vs. 256.77 ± 85.63 (mm³), 265.19 ± 41.12 versus 377.17 ± 90.97 (mm³), and 303.80 ± 47.15 versus 452.68 ± 90.44 (mm³) respectively), thereby indicating the optimised ladder-climbing method as effective for subjects with various stroke severities. Individual differences may cause different exercise capacities for each participant. To accommodate for these exercise capacities, an optimised ladder-climbing rehabilitation training system was proposed, which provided training according to the physical abilities of each participant.

Retraction: [Kaiyi Qiu, Xin Liu, Jie Liu, Hongbo Ma, Jingya Li, Zhengchao Zhang, Guangliang Chen, Li Cai, Research on tridimensional monitoring and defence technology of substation, IET Circuits, Devices & Systems 2022 (https://doi.org/10.1049/cds2.12129)].

The above article from IET Circuits, Devices & Systems, published online on 14 September 2022 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer review process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.

Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network-based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance.

Recently, several studies were done on SRAM bitcells at different supply-voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply-voltage with proper subthreshold operations and Nano/Pico power-dissipations, hence this paper decides to investigate challenges and solutions of designing at $��V_{�D�D�}�$ =  $��V_{�t�h�}�$, because this voltage will lead to having lower power consumptions. This research applies power-gating technique to adjust $��V_{�D�D�}�$ on $��V_{�t�h�}�$, and also utilises output-inverter to set Logic 1 at $��V_{�D�D�}�$. Although ‘power-gating’ and ‘output-inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power-gating technique in adjusting