Iet Circuits Devices & Systems最新文献

In order to deepen the understanding of power electronics circuits, in this study, a teaching method of adding simple small applications of circuits on the basis of basic verification experiments is proposed. Teachers teach basic principles and applications of circuits, and students conduct basic verification experiments of circuits in the laboratory. Simple application experiments are added after the verification experiments. The full-bridge DC-DC converter circuit is taken as an example to carry out practical teaching. After completing the function of the full-bridge DC-DC converter circuit, a load of DC motor is used. The full-bridge DC-DC converter circuit is used to control the speed of the DC motor so as to realise the simple application of the full-bridge DC-DC converter circuit with a motor speed control function. By comparing the experimental realisation rate, the correct rate of thinking questions and the in-depth understanding of the application theory of two experimental classes, namely the class with simple applications and the class without simple applications, it is shown that the students with simple application experiments improved the correct rate of thinking questions and deepened their understanding of the applications. Compared with the situation in which most students in the class that did not conduct the application experiment did not know the application principle in detail, most students in the class that conducted the application experiment had a deep understanding of the applications. Through the questionnaire survey of students, it is observed that the method proposed in this study could deepen the understanding of circuits and the students had a simple and preliminary understanding of the applications of power electronics technology. It improved students' interest in the course and their practicing ability. The proposed teaching method had a good effect.

Dynamic thermal management (DTM) is applied to address the thermal problem of high performance very-large-scale integrated chips. The false alarm rate (FAR) can be used to evaluate the impact of full-chip thermal field reconstruction accuracy on DTM. A low FAR relies on the accurate reconstruction of the full thermal field, especially near the temperature triggering threshold of DTM. However, little attention is currently being paid to such temperature ranges. To reduce FAR, a new full-chip thermal field reconstruction strategy is proposed. A low-dimensional linear model is used to accurately represent the thermal fields. The dictionary learning technology is exploited to train the model and the minimum weighted mean square error evaluation method is incorporated to improve the reconstruction accuracy near the temperature triggering threshold. A temperature sensor placement algorithm using the heuristic algorithm to solve the NP-hard problem is also proposed. The experimental results show that the proposed strategy can reconstruct the full thermal field with a more precise accuracy near the triggering threshold and achieve the lowest FAR compared to the state of the art.

This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.

Mismatch in the binary-weighted capacitive digital-to-analog converter (DAC) greatly affects the linearity of the successive-approximation-register (SAR) ADC by deteriorating the total harmonic distortion (THD). In this study, a theoretical relationship between the THD and the mismatch error of DAC array in SAR ADC is derived through discrete Fourier transform (DFT) analysis of the time-based integral error (TIE) of the ADC's output codes, which has no specific requirement on the type of the input signals. Guided by the theoretical THD expression, the trade-off among the linearity, design complexity, power consumption and chip area can be balanced easily. The presented formula is verified by a design example of 12-bit SAR ADC with dynamic-element-matching (DEM) technique, where the 3-bit LSBs from the SAR ADC are used to generate the randomised DEM state according to the previous THD evaluation. The linearity is enhanced by 9 dB approximately with very low hardware complexity and extremely small extra power consumption of 2 μW.

Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in the sub-100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage-controlled oscillators (VCOs) without affecting the circuit specifications. A circuit asymmetry technique is used for faster recovery of the oscillator in the event of a single event transient (SET) caused by an ion hit. Also, a new SET tolerant inductor capacitor-voltage controlled oscillator (LC-VCO) topology is proposed for a radiation environment that shows reduced phase displacement, amplitude displacement, and recovery time. A comparison has been made with various LC-VCOs that have an inherent rad-hard capability which proves a significant improvement in SET sensitivity.

In order to deepen students' understanding of experimental content and improve the accuracy of experimental results based on improving students' learning initiative, in this study, a teaching method is proposed that lets students check and correct experimental results among themselves after doing experiments. Teachers guide students in experiments but do not check and correct experimental results. At the end of the experiments, students check each other and correct the results of the experiments from the perspective of the teachers. When the experimental results are correct, the experiment ends. If problems are found, the correct experimental results can be obtained by modifying or redoing the experiment. In this study, the sinusoidal pulse width modulation inverter circuit experiment in power electronics course is taken as an example for practical teaching research. There are two classes in this study: one that applies the method and the other that does not. According to the statistics and analysis of the correct rate of experimental results and the answers to thinking questions, students who checked or corrected each other deepened their understanding of the experimental content when both groups did the experiments correctly. When the experimental results of the two groups are different, students can learn from each other, discuss with each other, redo the experiment, and correct wrong results so as to improve the accuracy of the experimental results and the correct answer rate of thinking questions. Through the questionnaire survey, the method proposed in this study enables students to correct the experimental results from the perspective of teachers, thus improving students' awareness of mutual learning and active learning. It can improve the experimental effect.

Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template-based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template-based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U-net while requiring 13× shorter training/validation time. To further improve the pixel-wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning-based TCMD-PL model. The proposed TCMD-PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling.

This work presents a simplified analytical model of a p-n junction diode based on a graphene nanoribbon (GNR) and a unique type of Schottky diode based on metallic graphene and semi-conducting GNRs. Due to the one-dimensional nature of GNRs, their electrostatic analyses need to be quite different from that of bulk devices. Two approaches have been taken to model the charge distribution in this depletion region, namely, the point charge approximation for the GNR p-n junction diode and the line charge approximation for the graphene/GNR Schottky diode. Analytical expressions for the spatial distribution of electric field and potential have been derived and the results are quite distinct from their bulk counterparts. The current-voltage relation of each diode has been investigated within the approximation of Shockley's law of junctions. The width dependency of the currents for these diodes has also been modelled and it has been found that the current density of both the diodes decreases with decreasing width. Such an analysis can encourage the modelling of next-generation GNR-based high-speed electronic devices.

Convolutional neural networks (CNNs) have been widely applied in the field of computer vision due to their inherent advantages in image feature extraction. However, it is difficult to implement CNNs directly on embedded platforms owing to excessive calculations of CNNs. Field Programmable Gate Arrays have been popular in CNN accelerators because of their configurability and high energy efficiency. Given the highly parallel workloads of the CNN, a CNN accelerator with a 14 × 16 processing element array is designed in this study to accelerate the CNN inference. Besides, a loop tiling strategy for convolutional layers is proposed to efficiently transmit feature maps. Additionally, the roofline model is employed to explore the best tiling parameters for optimal performance. Finally, the accelerator written in Verilog-HDL language is implemented on the Xilinx Zynq-7045 evaluation platform. At an operating frequency of 200 MHz, the proposed accelerator can achieve a performance of 57.24 giga operations per second on You Only Look Once v2-tiny and 78.39 GOPS on Visual Geometry Group-16. The accelerator only consumes 224 DSPs, demonstrating a better performance compared with the previous works.

In order to meet the need for more experimental content for students with strong active learning ability and to solve the problem of students’ different needs for experimental content and depth, a teaching method of adding selective experiments is proposed in this study on the basis of basic experiments. The method is also aimed at achieving the need for multi-level teaching. In the experimental course, the teacher arranges all the students in the class and makes them perform the basic circuit experiment. The teacher then adds the selective experiments on the basis of the basic experimental circuit so that the students can freely select the experiment they want to complete and meet the need for expanding the experimental needs of students with strong active learning ability. In this study, the voltage regulating circuit experiment is taken as an example to carry out practical teaching. The basic experimental content is a single-phase voltage regulating circuit experiment, and the selective experiment is a three-phase voltage regulating circuit experiment. The final examination scores of the students who have performed the selective experiments are higher than the average score of the class, which shows that the students who have performed the selective experiments are good students with a strong need for active learning. The curriculum of this study meets their need for active learning. With the help of the realisation rate of the circuit function, the correct answer rate of thinking questions and the experimental time of students who have performed the selective experiments, it is shown that the method of multi-level teaching and differentiated experimental teaching is feasible. Through the questionnaire survey of students, it can be seen that the teaching method proposed in this study can meet the students’ need for active learning, improve students’ interest in the course, and increase the opportunities for training students’ practical ability.