Iet Circuits Devices & Systems最新文献

This work presents a simplified analytical model of a p-n junction diode based on a graphene nanoribbon (GNR) and a unique type of Schottky diode based on metallic graphene and semi-conducting GNRs. Due to the one-dimensional nature of GNRs, their electrostatic analyses need to be quite different from that of bulk devices. Two approaches have been taken to model the charge distribution in this depletion region, namely, the point charge approximation for the GNR p-n junction diode and the line charge approximation for the graphene/GNR Schottky diode. Analytical expressions for the spatial distribution of electric field and potential have been derived and the results are quite distinct from their bulk counterparts. The current-voltage relation of each diode has been investigated within the approximation of Shockley's law of junctions. The width dependency of the currents for these diodes has also been modelled and it has been found that the current density of both the diodes decreases with decreasing width. Such an analysis can encourage the modelling of next-generation GNR-based high-speed electronic devices.

Convolutional neural networks (CNNs) have been widely applied in the field of computer vision due to their inherent advantages in image feature extraction. However, it is difficult to implement CNNs directly on embedded platforms owing to excessive calculations of CNNs. Field Programmable Gate Arrays have been popular in CNN accelerators because of their configurability and high energy efficiency. Given the highly parallel workloads of the CNN, a CNN accelerator with a 14 × 16 processing element array is designed in this study to accelerate the CNN inference. Besides, a loop tiling strategy for convolutional layers is proposed to efficiently transmit feature maps. Additionally, the roofline model is employed to explore the best tiling parameters for optimal performance. Finally, the accelerator written in Verilog-HDL language is implemented on the Xilinx Zynq-7045 evaluation platform. At an operating frequency of 200 MHz, the proposed accelerator can achieve a performance of 57.24 giga operations per second on You Only Look Once v2-tiny and 78.39 GOPS on Visual Geometry Group-16. The accelerator only consumes 224 DSPs, demonstrating a better performance compared with the previous works.

In order to meet the need for more experimental content for students with strong active learning ability and to solve the problem of students’ different needs for experimental content and depth, a teaching method of adding selective experiments is proposed in this study on the basis of basic experiments. The method is also aimed at achieving the need for multi-level teaching. In the experimental course, the teacher arranges all the students in the class and makes them perform the basic circuit experiment. The teacher then adds the selective experiments on the basis of the basic experimental circuit so that the students can freely select the experiment they want to complete and meet the need for expanding the experimental needs of students with strong active learning ability. In this study, the voltage regulating circuit experiment is taken as an example to carry out practical teaching. The basic experimental content is a single-phase voltage regulating circuit experiment, and the selective experiment is a three-phase voltage regulating circuit experiment. The final examination scores of the students who have performed the selective experiments are higher than the average score of the class, which shows that the students who have performed the selective experiments are good students with a strong need for active learning. The curriculum of this study meets their need for active learning. With the help of the realisation rate of the circuit function, the correct answer rate of thinking questions and the experimental time of students who have performed the selective experiments, it is shown that the method of multi-level teaching and differentiated experimental teaching is feasible. Through the questionnaire survey of students, it can be seen that the teaching method proposed in this study can meet the students’ need for active learning, improve students’ interest in the course, and increase the opportunities for training students’ practical ability.

This study proposes a high step-down DC-DC converter with minimum elements. In the proposed converter, soft switching condition is provided with only one auxiliary switch, which simplifies the structure of the converter. Leakage inductor energy is used to create a zero voltage condition; so the mutations created by this inductor are neutralised. The control of the auxiliary switch is complementary to the main switch, which does not require a new and complex control circuit. Due to low voltage gain, the proposed converter is suitable for use in voltage regulator modules. The proposed converter is completely analysed. To confirm the theoretical analysis, an experimental sample is made and tested at 15 W and the results are presented. Also, the efficiency of the proposed converter at full load is 97.5%.

Modern electronic systems usually use third-party IP cores to build basic blocks. However, there may be Hardware Trojans (HTs) in IP cores, which will cause critical security problem. There are already many HT detection methods which claim to detect all publicly available HT benchmarks. But these methods can still be defeated by designing novel HTs. In this article, a method called Blinding HT is proposed, which camouflages itself as a normal circuit and is difficult to be triggered. The Blinding HT hides input signals of HT modules by tracing across multiple sequential levels. This method increases the influence of HT trigger inputs on output signals, so that trigger inputs are not be identified as redundant inputs. In this way, this approach can defeat the detection methods which identify weakly affecting trigger inputs and redundant trigger inputs across multiple sequential levels. As shown in the experimental results, the proposed HTs are hardly detected even by the novel HT detection approach based on machine learning algorithm. These HTs have small footprints on the design in terms of area and power to resist the side-channel effect analysis. The proposed HT has stealthiness, general applicability and imperceptibility.

In this work, the design and development of a 128-channel transceiver hardware for medical ultrasound imaging systems and research is presented. The proposed hardware solution integrates the analog front-end (AFE) sections, high voltage transmit pulser sections, field programmable gate array (FPGA)-based transmit beamforming and control logic, time gain compensation (TGC) and continuous (CW) Doppler functional circuits, and the necessary power supplies (high voltage (HV) and low voltage (LV)) into a single board. In addition, it integrates pervasive segments like power, clock tree sections, and power management and debugger logic. The developed transceiver solution helps to advance the research in medical ultrasound imaging techniques and technologies. To prototype an ultrasound imaging system, the developed hardware can be interfaced with a 128-channel ultrasound transducer array and an FPGA-based signal processing module. As the transceiver hardware is designed with commercially available chipsets, it provides the flexibility to programme the ultrasound AFE signal chain, transmit beamforming and the arbitrary transmit wave pattern. Besides, compared to the commercial open ultrasound research scanners, the flexibility to interface FPGA-based signal processing module helps to investigate the performance of hardware realisation of various ultrasound signal processing algorithms. Moreover, the work realises a single-board transceiver solution for multichannel ultrasound system fulfilment.

Memristors are passive non-linear circuit components with memory characteristics, and have been recognized as the fourth basic circuit component, along with resistors, capacitors, and inductors. It has been nearly half a century since the conceptualisation of the memristor, and related research has mainly focussed on the two aspects of binary and continuous memristors. However, compared with these two types of memristors, tri-state and multi-state memristors have greater data density per device, with rich dynamics and great potential in logic and chaotic circuit applications. Moreover, previous studies show that the series-parallel connection of memristor generates more diverse circuit behaviours and increased capacity over a single memristor. However, most of this research is based on mathematical analysis, and lack behavioural circuit simulations or experimental validation. Here, the tri-state memristor is proposed and the mathematic and equivalent Spice models of the tri-state memristor is shown. Furthermore, the circuit characteristics are studied with a complete characterisation of its series-parallel behaviours of the tri-state memristor. Simulations are performed with LTSpice, and the results verify the theoretical analysis, which provides a strong experimental basis for the study of combinational memristive circuits.

In [1], the following corrections should be noted.

This work is sponsored by the Young Faculty Research Fellowship (YFRF) of Visvesvaraya Ph.D. scheme through the grant number MLA/MUM/GA/10(37)B.

Quantum-dot cellular automata (QCA) is one of the best methods to implement digital circuits at nanoscale. It has excellent potential with high density, fast switching speed, and low energy consumption. Researchers have emphasized reducing the number of gates, the delay, and the cell count in QCA technology. In addition, a ripple carry adder (RCA) is a circuit in which each full adder's carry-out is the connection for the next full adder's carry-in. These types of adders are quite simple and easily expandable to any desired size. However, they are relatively slow because carries may broadcast across the entire adder. Therefore, an RCA design on a nanoscale QCA is proposed to diminish the cell number, improve complexity, and decrease latency. The QCADesigner simulation tool is used to verify the correctness of the suggested circuit. The comparison results for the design indicate an approximately 49.14% improvement in cell number and 14.29% advantage in area for the state-of-the-art 4-bit RCA designs with QCA technology. In addition, the obtained results specify the effectiveness of the offered design.

The Ćuk converters operating in continuous conduction mode (CCM) can be preferred in applications such as microprocessor power delivery and pulsed load because these circuits have advantages of being able to step up/down, a small number of power components, and low input/output current ripples. However, they show poor transient performance due to right-half-plane-zeros (RHPZs) in the closed-loop transfer function of the Ćuk CCM converter. To enhance the transient response, a combined feedback–feedforward control for the Ćuk CCM converter is proposed. The proposed control scheme comprises a feedback control signal based on a Lyapunov function and a duty-ratio feedforward control signal. A Lyapunov-function-based controller (LBC) achieves fast dynamic response even under large-signal variations from the operating point. The duty ratio feedforward controller (DFFC) is developed to predict the effect of the disturbances and compensate it, while alleviating the burden of LBC. The proposed control logic makes the closed-loop system of the Ćuk CCM converter globally exponentially stable and thus provides a fast transient response even under large-signal variations. To construct the proposed controller, the authors make use of the large-signal averaged model of the Ćuk CCM converter, and consider the parasitic elements. To verify the proposed control scheme, numerical simulations and experimental tests are conducted.