Microelectronics Reliability最新文献_第7页

Mechanisms of electrochemical migration in damp-heat and dew-condensation environments of chip resistors 片式电阻器湿热、结露环境下电化学迁移机理研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-11-20 DOI: 10.1016/j.microrel.2025.115958

Hao Zhang , Zixue Jiang , Luntao Wang , Yao Tan , Xiaowen Song , Chao Li , Jialiang Song , Hao Yu , Junsheng Wu , Kui Xiao

Electrochemical migration (ECM) has become a major reliability concern in miniaturized and high-density electronic components, particularly under damp-heat and condensation environments. This study comparatively investigates the ECM behavior of chip resistors exposed to these two moisture regimes. After applying a 6 V bias voltage for 30 min under damp-heat atmospheres with 60 %, 70 %, and 80 % relative humidity, no significant signs of corrosion were observed at the resistor terminals. In damp-heat conditions (up to 90 % RH), the anode underwent gradual Sn oxidation dominated by Sn⁴⁺ species, yet no dendritic structures were observed due to the absence of a continuous electrolyte film. In contrast, condensation environments (RH > 60 %) facilitated the formation of a continuous liquid layer, leading to rapid ECM initiation and the growth of Sn-based dendrites enriched in Sn²⁺ species. Furthermore, as the relative humidity increased, the degree of corrosion at both ends of the resistor became more severe correspondingly. At 90 % RH, simultaneous anodic darkening and aggravated corrosion were observed, confirming the accelerated redox processes within the condensed electrolyte. The results demonstrate that ECM failure occurs only when both a continuous electrolyte film and an external bias potential coexist, providing new insights into moisture-induced reliability degradation of surface-mount components.

电化学迁移（ECM）已经成为小型化和高密度电子元件的主要可靠性问题，特别是在湿热和冷凝环境下。本研究比较研究了贴片电阻在这两种湿度下的ECM行为。在相对湿度分别为60%、70%和80%的湿热环境下，施加6v偏置电压30分钟后，电阻器端子未观察到明显的腐蚀迹象。在湿热条件下（高达90% RH），阳极发生以Sn4+为主的逐渐锡氧化，但由于没有连续的电解质膜，没有观察到枝晶结构。相比之下，冷凝环境（RH > 60%）有利于形成连续的液体层，导致ECM的快速启动和富含Sn2+的sn基枝晶的生长。此外，随着相对湿度的增加，电阻器两端的腐蚀程度也相应加重。在90%相对湿度下，观察到同时阳极变暗和腐蚀加剧，证实了冷凝电解质中的氧化还原过程加速。结果表明，只有当连续电解质膜和外部偏置电位共存时，ECM才会发生故障，这为表面贴装组件的湿致可靠性退化提供了新的见解。

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引用次数: 0

Uncertainty quantification in microelectronic packaging using feedback-enhanced adaptive polynomial chaos expansion 基于反馈增强自适应多项式混沌展开的微电子封装不确定度量化

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-12-08 DOI: 10.1016/j.microrel.2025.115973

Guozhuang Fan , Jinzhu Zhou , Qiangqiang Lin , Jiancheng Shi

This paper presents a feedback-enhanced adaptive polynomial chaos modeling framework for robust performance prediction of microelectronic packages incorporating wire bonding, with the aim of addressing process-induced variability in advanced packaging environments. To tackle persistent reliability challenges in microelectronic assembly—particularly those associated with gold wire bonding—the proposed approach integrates adaptive kernel density estimation with residual-driven basis refinement to dynamically model non-Gaussian process fluctuations observed across manufacturing batches. By incorporating an online feedback loop, the model autonomously adjusts to process drift and parameter shifts, enabling real-time response to deviations in the packaging workflow. Validation on a 16-channel microelectronic module demonstrates that the proposed approach maintains high prediction accuracy across varying production conditions, with over 98 % of measured samples falling within the predicted confidence bounds. The method effectively models packaging-induced performance variability and serves as a data-driven tool for manufacturing-oriented uncertainty quantification and predictive control in high-frequency module production.

本文提出了一种反馈增强的自适应多项式混沌建模框架，用于结合线键合的微电子封装的鲁棒性能预测，旨在解决先进封装环境中工艺引起的可变性。为了解决微电子组装中持续存在的可靠性挑战，特别是与金丝键合相关的问题，该方法将自适应核密度估计与残差驱动基精化相结合，以动态建模在制造批次中观察到的非高斯过程波动。通过整合在线反馈回路，该模型可以自动调整过程漂移和参数变化，从而对包装工作流程中的偏差做出实时响应。在16通道微电子模块上的验证表明，所提出的方法在不同的生产条件下保持较高的预测精度，超过98%的测量样品落在预测的置信范围内。该方法有效地模拟了封装引起的性能变化，并为高频模块生产中面向制造的不确定性量化和预测控制提供了数据驱动工具。

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引用次数: 0

Radiation effect in FD-SOI nanowire FETs due to high dose rate gamma-ray under variable irradiation temperatures 可变辐照温度下高剂量率γ射线对FD-SOI纳米线场效应管的辐射效应

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-11-19 DOI: 10.1016/j.microrel.2025.115957

Jonghyeon Ha, Minki Suh, Minsang Ryu, Dabok Lee, Dae-Young Jeon, Jungsik Kim

In this study, the effects of gamma-ray irradiation on fully depleted silicon on insulator (FD-SOI) Nanowire FETs (NWFETs) at different irradiation temperatures (265, 300, and 400 K) were analyzed. For PMOS, positive threshold shift (ΔV_th) owing to interface and oxide traps could be observed regardless of the irradiation temperature. However, NMOS showed a different temperature trend. At 400 K, the oxide traps were cured during annealing, enhancing the influence of interface traps and resulting in a positive ΔV_th. In comparison, at 265 K, the oxide traps became more influential due to reduced hole mobility in the buried oxide (BOX), resulting in a negative ΔV_th. Annealing was performed at room temperature for 24 and 168 h to investigate the ΔV_th owing to the annealing effect (ΔV_th-anneal). In NMOS, a positive ΔV_th-anneal occurred regardless of width (W) as the oxide traps were cured by annealing. PMOS showed a negative ΔV_th-anneal regardless of W.

在本研究中，分析了不同辐照温度（265、300和400 K）下γ射线辐照对全贫硅绝缘体（FD-SOI）纳米线场效应管（nwfet）的影响。对于PMOS，由于界面和氧化物陷阱，无论辐照温度如何，都可以观察到正的阈值位移（ΔVth）。而NMOS则表现出不同的升温趋势。在400 K时，氧化陷阱在退火过程中固化，增强了界面陷阱的影响，产生了正ΔVth。相比之下，在265 K时，由于埋藏氧化物（BOX）的空穴迁移率降低，氧化物捕集器的影响更大，导致负ΔVth。在室温下退火24和168 h，以研究由于退火效应（ΔVth-anneal）而产生的ΔVth。在NMOS中，当氧化阱通过退火固化时，无论宽度(W)如何，都出现了正ΔVth-anneal。PMOS表现为负ΔVth-anneal与W无关。

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引用次数: 0

Interlayer capacitance extraction for profiling interface states in LaB₆/H-diamond Schottky diodes lab4600 / h -金刚石肖特基二极管界面态分析的层间电容提取

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-11-18 DOI: 10.1016/j.microrel.2025.115955

Xufang Zhang , Mingkun Li , Shihao Lu , Shuopei Jiao , Shichao Wang , Pengyu Li , Zhiwei Jiao , Kang An , Hong Dong , Wei Wang , Jing Zhang

The performance of diamond-based Schottky barrier diodes (SBDs) is often limited by poor understanding of Schottky interfaces due to the existence of a native interlayer. Specifically, it is difficult to characterize the dielectric constant and thickness of the interlayer by conventional methods. In this work, we established an equivalent circuit model based on high-frequency capacitance–voltage (C–V) characteristics, thereby directly extracting the interlayer capacitance (C_i) and circumventing the challenge of determining the dielectric constant and thickness. Furthermore, the voltage-dependent ideality factor (n (V)) was evaluated based on current–voltage (I–V) characteristics under forward biases. By combining the C_i and n (V) extraction, the energy distribution of interface state density (D_it) was evaluated for the LaB₆/H-diamond SBD, ranging from approximately 4 × 10¹³ to 1.2 × 10¹⁴ cm⁻² eV⁻¹ in the energy levels of 0.2 to 0.5 eV from the valence band edge (E_v) of diamond. This work provides a novel technique to characterize D_it profile for diamond SBDs, which would be beneficial for the future improvement of device performances.

基于金刚石的肖特基势垒二极管（sbd）的性能通常受到肖特基界面的限制，因为存在固有的中间层。具体地说，用常规方法很难表征介电常数和中间层的厚度。在这项工作中，我们建立了一个基于高频电容-电压（C-V）特性的等效电路模型，从而直接提取层间电容（Ci），从而规避了确定介电常数和厚度的挑战。此外，基于正向偏置下的电流-电压（I-V）特性，评估了电压依赖的理想因数（n (V)）。结合Ci和n (V)萃取，计算了LaB6/ h -金刚石SBD的界面态密度（Dit）的能量分布，在距金刚石价带边缘（eV） 0.2 ~ 0.5 eV的能级上，Dit的范围约为4 × 1013 ~ 1.2 × 1014 cm−2 eV−1。这项工作为金刚石sdd的Dit剖面的表征提供了一种新的技术，这将有利于未来器件性能的提高。

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引用次数: 0

AI surrogate modeling for PBGA solder joint fatigue risk assessment 基于AI的PBGA焊点疲劳风险评估模型

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-11-29 DOI: 10.1016/j.microrel.2025.115956

Cadmus Yuan, Jian-Cheng Hong, Pin-Sian Li

Solder joint reliability is a critical concern in advanced electronic packaging, especially as heterogeneous integration and chiplet-based architectures increase interconnect density and stricter reliability demands. This study introduces an artificial intelligence (AI)–finite element modeling (FEM) co-design framework for assessing solder fatigue failures, utilizing AI surrogate models for quick conceptual design exploration while preserving the accuracy of FEM validation. The research emphasizes developing training strategies that create AI surrogate models with strong generalization capabilities and investigates their use in conceptual design optimization using a database generated from an experimentally validated FEM.

To achieve robust model performance, the methodology integrates genetic algorithms for diverse weight initialization, kernel principal component analysis (K-PCA) for dimensionality reduction, and ensemble learning to balance computational efficiency and predictive robustness. Beyond conventional metrics, cosine similarity analysis and weight frequency decomposition are introduced as diagnostic tools for overparameterized deep neural networks (DNNs). Comparative analyses of adaptive moment estimation (ADAM) and stochastic gradient descent (SGD) show that both optimizers can achieve low validation errors, with SGD tending to yield smoother gradients and ADAM converging more rapidly. Experimental results indicate that well-constructed ensembles achieve validation errors below 1 % while maintaining consistent gradient-based optimization outcomes across different weight initializations. Monte Carlo simulations further confirm the greater robustness of SGD-trained models under parameter uncertainty, attributed to their preference for low-frequency, smooth solutions. The proposed framework ensures that AI surrogate models are both predictive and optimization-consistent, effectively bridging early-stage design exploration with high-fidelity reliability assessment in electronic packaging applications.

焊点可靠性是先进电子封装的一个关键问题，特别是在异构集成和基于芯片的架构增加互连密度和更严格的可靠性要求的情况下。本研究引入了人工智能(AI) -有限元建模（FEM）协同设计框架，用于评估焊料疲劳失效，利用AI替代模型进行快速概念设计探索，同时保持FEM验证的准确性。该研究强调开发训练策略，以创建具有强大泛化能力的人工智能代理模型，并使用由实验验证的FEM生成的数据库研究其在概念设计优化中的应用。为了实现稳健的模型性能，该方法集成了用于不同权重初始化的遗传算法、用于降维的核主成分分析（K-PCA）和用于平衡计算效率和预测鲁棒性的集成学习。除了传统的度量，余弦相似度分析和权重频率分解被引入作为过度参数化深度神经网络（dnn）的诊断工具。对自适应矩估计（ADAM）和随机梯度下降（SGD）的比较分析表明，这两种优化方法都可以实现较低的验证误差，SGD倾向于产生更平滑的梯度，ADAM更快收敛。实验结果表明，在不同权重初始化的情况下，构造良好的集成在保持一致的基于梯度的优化结果的同时，验证误差低于1%。蒙特卡罗模拟进一步证实了sgd训练的模型在参数不确定性下具有更强的鲁棒性，这归因于它们对低频光滑解的偏好。提出的框架确保人工智能代理模型既具有预测性又具有优化一致性，有效地将电子封装应用中的早期设计探索与高保真可靠性评估联系起来。

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引用次数: 0

Investigation of interface traps properties induced by NBTI effects at different interfaces of VDMOS NBTI效应在VDMOS不同界面诱导的界面陷阱特性研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-12-08 DOI: 10.1016/j.microrel.2025.115977

Yanyong Wang , Liang He , Yanfang Li , Zhenni Wang , Zhongyang Li , Hao Zhou , Kaihe Liu , Maolin Zhang

This paper investigates the negative bias temperature instability (NBTI) of P-channel vertical double-diffused MOSFETs (VDMOS). The threshold voltage (V_TH) shift in VDMOS due to NBTI is primarily caused by the generation of oxide charge and interface traps in the gate oxide layer. The interface traps at the VDMOS drain interface and channel were investigated using the Direct-Current Current-Voltage (DCIV) technique and the conductance method, respectively. The results indicate that NBTI stress induces a higher density of interface traps in the channel region. Through TCAD simulation, it was discovered that the electric field intensity in the channel region exceeds that at the drain interface under negative bias. This larger electric field intensity causes increased dissociation of interface hanging bonds, ultimately leading to a greater number of interface traps in the channel region.

研究了p沟道垂直双扩散mosfet （VDMOS）的负偏置温度不稳定性（NBTI）。NBTI在VDMOS中引起的阈值电压（VTH）偏移主要是由于栅极氧化层中氧化电荷和界面陷阱的产生。采用直流电压法（DCIV）和电导法分别研究了VDMOS漏极界面和沟道的界面陷阱。结果表明，NBTI应力在通道区诱导了更高密度的界面陷阱。通过TCAD仿真发现，在负偏压下，沟道区域的电场强度大于漏极界面处的电场强度。这种较大的电场强度导致界面悬垂键解离增加，最终导致通道区域界面陷阱数量增加。

引用次数: 0

Comparative study of extrapolation methods for solder joint lifetime estimation using crack length data 利用裂纹长度数据估算焊点寿命的外推方法比较研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-12-12 DOI: 10.1016/j.microrel.2025.115976

Dorottya Varga , Zsombor Olajos , Gabor Belina

Estimating solder joint lifetime often involves extrapolating crack length measurements from cross-sectional images to a defined end-of-life (EoL) criterion. The original pearl string method fits a single regression line to all data points, which can result in unrealistic predictions, such as negative slopes or failure times. To address these issues, an alternative pearl string method was proposed, incorporating a fixed crack-free time (CFT) ratio to better reflect actual damage evolution. This study compares the two methods in terms of robustness, accuracy, and statistical consistency. The alternative method fits individual crack propagation curves for each specimen, enabling lifetime estimation in destructive testing with limited measurement points. Outlier sensitivity analysis showed that the original method is highly affected by anomalous data, while the alternative method exhibited minimal change. Goodness-of-fit evaluation using the Kolmogorov–Smirnov test confirmed that the alternative method aligns more closely with the validation data (p = 0.09 and 0.22), unlike the original method (p = 3.66 × 10⁻⁶ and 1.20 × 10⁻⁸). In conclusion, the alternative pearl string method offers a more robust and physically meaningful approach for lifetime extrapolation, especially in contexts with limited or noisy data.

估计焊点寿命通常涉及从横截面图像推断裂纹长度测量到定义的寿命终止（EoL）标准。原始的珍珠串方法将单个回归线拟合到所有数据点，这可能导致不切实际的预测，例如负斜率或失效时间。为了解决这些问题，提出了一种替代的珍珠管柱方法，该方法结合了固定的无裂纹时间（CFT）比，以更好地反映实际的损伤演变。本研究在稳健性、准确性和统计一致性方面比较了两种方法。另一种方法适合每个试样的单独裂纹扩展曲线，使得在有限测点的破坏性测试中进行寿命估计。异常值敏感性分析表明，原始方法受异常数据影响较大，而替代方法变化较小。使用Kolmogorov-Smirnov检验的拟合优度评估证实，与原始方法（p = 3.66 × 10 - 6和1.20 × 10 - 8）不同，替代方法与验证数据更接近（p = 0.09和0.22）。总之，替代珍珠管柱方法为寿命外推提供了一种更可靠、更有物理意义的方法，特别是在数据有限或有噪声的情况下。

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引用次数: 0

Improved thermoreflectance imaging of trench IGBT via focus and illumination optimized reconstruction 通过聚焦和光照优化重建改进了堑壕IGBT的热反射成像

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-11-25 DOI: 10.1016/j.microrel.2025.115952

M. Sanogo , T. Kociniewski , Z. Khatir

In this paper, we improved the signal-to-noise ratio (S/N) of thermoreflectance images of trench Insulated Gate Bipolar Transistors (IGBT) particularly in low-intensity areas caused by insufficient illumination or defocusing due to topography and depth variations within these components. To enhance and homogenize signal intensity across the entire surface, we accurately determined the focal planes and optimal lighting conditions for each region. Then, before performing reflectivity calculations, we reconstructed a single high intensity optical image by selecting pixels based on their local focus values. This optical image reconstruction ensures a uniform distribution of maximum intensity across the image and significantly improvises the S/N ratio minimizing artifacts in the final reflectivity map.

在本文中，我们提高了沟槽绝缘栅双极晶体管（IGBT）的热反射图像的信噪比（S/N），特别是在低强度区域，由于这些组件内部的地形和深度变化导致光照不足或散焦。为了增强和均匀化整个表面的信号强度，我们精确地确定了每个区域的焦平面和最佳照明条件。然后，在进行反射率计算之前，我们根据其局部焦点值选择像素，重建了单个高强度光学图像。这种光学图像重建确保了最大强度在整个图像中的均匀分布，并显著提高了信噪比，最大限度地减少了最终反射率图中的伪影。

引用次数: 0

Investigation of thermal contact resistance, incident depth, incident angle, drain voltage and ambient temperature on single event transient during self-heating 自热过程中单事件瞬态的热接触电阻、入射深度、入射角、漏极电压和环境温度的研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-12-08 DOI: 10.1016/j.microrel.2025.115979

Yan Liu , Yanhua Ma , Chong Pan

In this work, the impacts of thermal contact resistance (SR), incident depth, incident angle, drain voltage and ambient temperature on the nanosheet characteristics under single event transient during self-heating are investigated using 3D computer-aided design. The results show that the self-heating reduces the maximum transient current under single event transient by 12.65 %. This attributes to the fact that the self-heating increases lattice temperature, thereby reducing the mobility and linear energy transfer. Moreover, the maximum transient current decreases by 9.69 % with an increase of SR. Besides, the increasing incident depth arises the maximum transient current by 9.80 %. Meanwhile, an increase in incident angle decreases the maximum transient current by 0.44 %. Furthermore, as the drain voltage increases, the maximum transient current rises by 16.09 %. Additionally, the increasing ambient temperature reduces the maximum transient current by 10.72 %.

本文采用三维计算机辅助设计，研究了热接触电阻（SR）、入射深度、入射角、漏极电压和环境温度对纳米片自加热过程中单事件瞬态特性的影响。结果表明，自加热使单事件暂态下的最大暂态电流降低了12.65%。这是由于自加热提高了晶格温度，从而降低了迁移率和线性能量传递。最大瞬态电流随入射深度的增加而减小9.69%，最大瞬态电流随入射深度的增加而增大9.80%。同时，入射角的增加使最大瞬态电流降低0.44%。此外，随着漏极电压的增加，最大瞬态电流增加了16.09%。另外，随着环境温度的升高，最大瞬态电流降低了10.72%。

引用次数: 0

Enhanced fatigue reliability of SnBi solder joints through integrated cobalt nanoparticle reinforcement and magnetic field-assisted reflow 通过集成钴纳米颗粒强化和磁场辅助回流，提高SnBi焊点的疲劳可靠性

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-01 Epub Date: 2025-11-22 DOI: 10.1016/j.microrel.2025.115959

Suleiman Ibrahim Mohammad , Asokan Vasudevan , S. Sujai , Premananda Pradhan , Nivin Joy Thykattusserry , Ripendeep Singh , Yashwant Singh Bisht

This work investigates the combined effects of cobalt (Co) nanoparticle incorporation and magnetic field-assisted reflow processing on the microstructure and fatigue reliability of eutectic 42Sn58Bi solder joints. A set of six sample groups was prepared to independently and jointly assess the influence of 0.8 wt% Co reinforcement, application of a 1.0 T magnetic field, and thermal cycling. The results show that Co nanoparticles refine the eutectic lamellae and suppress intermetallic compound (IMC) coarsening at the interface, while magnetic field-assisted reflow enhances nanoparticle dispersion and produces a fine, honeycomb-like microstructure. After thermal cycling, unreinforced joints exhibited severe coarsening, localized strain accumulation, and brittle fracture, whereas Co nanoparticle-reinforced samples retained greater microstructural stability but showed moderate resistance to fatigue degradation. In contrast, joints fabricated using the combined Co + magnetic field approach maintained a uniformly refined microstructure, distributed stresses more evenly, and demonstrated enhanced hardness, strength, and ductility during prolonged cycling. These findings underscore the strong interdependence among nanoparticle dispersion, IMC evolution, and cyclic deformation behavior, offering a promising strategy for developing durable SnBi solder joints for advanced electronic packaging where thermal and mechanical reliability are paramount.

本文研究了纳米钴掺杂和磁场辅助回流处理对共晶42Sn58Bi焊点组织和疲劳可靠性的综合影响。制备了6组样品，分别对0.8 wt% Co增强、1.0 T磁场和热循环的影响进行独立和联合评估。结果表明，Co纳米颗粒细化了共晶片层，抑制了界面处金属间化合物（IMC）的粗化，而磁场辅助回流增强了纳米颗粒的分散，形成了精细的蜂窝状微观结构。热循环后，未增强的接头表现出严重的粗化、局部应变积累和脆性断裂，而Co纳米颗粒增强的样品保留了更大的微观结构稳定性，但表现出中等的抗疲劳退化能力。相比之下，采用Co +复合磁场方法制备的接头在长时间循环过程中保持了均匀细化的组织，更均匀地分布应力，并表现出更高的硬度、强度和延展性。这些发现强调了纳米颗粒分散，IMC演变和循环变形行为之间的强烈相互依赖性，为开发耐用的SnBi焊点提供了有前途的策略，用于先进的电子封装，其中热可靠性和机械可靠性至关重要。

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引用次数: 0