Pub Date : 2025-11-18DOI: 10.1016/j.microrel.2025.115955
Xufang Zhang , Mingkun Li , Shihao Lu , Shuopei Jiao , Shichao Wang , Pengyu Li , Zhiwei Jiao , Kang An , Hong Dong , Wei Wang , Jing Zhang
The performance of diamond-based Schottky barrier diodes (SBDs) is often limited by poor understanding of Schottky interfaces due to the existence of a native interlayer. Specifically, it is difficult to characterize the dielectric constant and thickness of the interlayer by conventional methods. In this work, we established an equivalent circuit model based on high-frequency capacitance–voltage (C–V) characteristics, thereby directly extracting the interlayer capacitance (Ci) and circumventing the challenge of determining the dielectric constant and thickness. Furthermore, the voltage-dependent ideality factor (n (V)) was evaluated based on current–voltage (I–V) characteristics under forward biases. By combining the Ci and n (V) extraction, the energy distribution of interface state density (Dit) was evaluated for the LaB6/H-diamond SBD, ranging from approximately 4 × 1013 to 1.2 × 1014 cm−2 eV−1 in the energy levels of 0.2 to 0.5 eV from the valence band edge (Ev) of diamond. This work provides a novel technique to characterize Dit profile for diamond SBDs, which would be beneficial for the future improvement of device performances.
{"title":"Interlayer capacitance extraction for profiling interface states in LaB₆/H-diamond Schottky diodes","authors":"Xufang Zhang , Mingkun Li , Shihao Lu , Shuopei Jiao , Shichao Wang , Pengyu Li , Zhiwei Jiao , Kang An , Hong Dong , Wei Wang , Jing Zhang","doi":"10.1016/j.microrel.2025.115955","DOIUrl":"10.1016/j.microrel.2025.115955","url":null,"abstract":"<div><div>The performance of diamond-based Schottky barrier diodes (SBDs) is often limited by poor understanding of Schottky interfaces due to the existence of a native interlayer. Specifically, it is difficult to characterize the dielectric constant and thickness of the interlayer by conventional methods. In this work, we established an equivalent circuit model based on high-frequency capacitance–voltage (<em>C</em>–<em>V</em>) characteristics, thereby directly extracting the interlayer capacitance (<em>C</em><sub>i</sub>) and circumventing the challenge of determining the dielectric constant and thickness. Furthermore, the voltage-dependent ideality factor (<em>n</em> (<em>V</em>)) was evaluated based on current–voltage (<em>I</em>–<em>V</em>) characteristics under forward biases. By combining the <em>C</em><sub>i</sub> and <em>n</em> (<em>V</em>) extraction, the energy distribution of interface state density (<em>D</em><sub>it</sub>) was evaluated for the LaB<sub>6</sub>/H-diamond SBD, ranging from approximately 4 × 10<sup>13</sup> to 1.2 × 10<sup>14</sup> cm<sup>−2</sup> eV<sup>−1</sup> in the energy levels of 0.2 to 0.5 eV from the valence band edge (<em>E</em><sub>v</sub>) of diamond. This work provides a novel technique to characterize <em>D</em><sub>it</sub> profile for diamond SBDs, which would be beneficial for the future improvement of device performances.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115955"},"PeriodicalIF":1.9,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145536917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-17DOI: 10.1016/j.microrel.2025.115954
Pushpa Rajaguru
This report focuses on the estimation of Anand viscoplastic model parameters for aluminium wirebonds, a critical component in Power Electronic Modules (PEMs). These complex PEM inhomogeneous structures are prone to thermo-mechanical failure due to heat generation and material Coefficient of Thermal Expansion (CTE) mismatches. The wirebond failures account for approximately 70 % of total PEM failures. The study addresses a gap in existing literature by deriving Anand model parameters for aluminium wirebonds from experimental tensile data. This involved of conducting isothermal uniaxial tensile tests on pure aluminium wire at various temperatures and strain rates and measuring the stress strain profile of each sample specimens. The nine Anand model parameters were then determined through a four-step non-linear fitting process. The accuracy of these estimated parameters was validated by comparing stress-strain curves from Finite Element Analysis (FEA) simulations with experimental data, showing a good fit across various conditions. The research proceeded to predict the fatigue lifetime of wirebond structures under various thermal cyclic loading scenarios, adhering to JEDEC standards. Accumulated plastic strain at the wirebond heel was identified as a key lifetime prediction parameter, utilizing the Coffin-Manson relationship. The analysis revealed an exponential decrease in wirebond lifetime with increasing temperature difference (ΔT) and upper thermal cycle temperature. Finally, the study explored using tree-based machine learning (ML) regressors (Random Forest, Decision Tree, and XGBoost) to predict accumulated plastic strain, aiming to mitigate the need for computationally expensive FEA simulations. Trained on a small dataset from 11 FEA simulations, the Decision Tree model exhibited a reasonable prediction error of 2.4 %, suggesting the potential for ML to provide efficient and reasonably accurate lifetime predictions in power electronics.
{"title":"Anand model parameter estimation for the aluminium wirebond in power electronic module and lifetime prediction by combining the finite element analysis and machine learning","authors":"Pushpa Rajaguru","doi":"10.1016/j.microrel.2025.115954","DOIUrl":"10.1016/j.microrel.2025.115954","url":null,"abstract":"<div><div>This report focuses on the estimation of Anand viscoplastic model parameters for aluminium wirebonds, a critical component in Power Electronic Modules (PEMs). These complex PEM inhomogeneous structures are prone to thermo-mechanical failure due to heat generation and material Coefficient of Thermal Expansion (CTE) mismatches. The wirebond failures account for approximately 70 % of total PEM failures. The study addresses a gap in existing literature by deriving Anand model parameters for aluminium wirebonds from experimental tensile data. This involved of conducting isothermal uniaxial tensile tests on pure aluminium wire at various temperatures and strain rates and measuring the stress strain profile of each sample specimens. The nine Anand model parameters were then determined through a four-step non-linear fitting process. The accuracy of these estimated parameters was validated by comparing stress-strain curves from Finite Element Analysis (FEA) simulations with experimental data, showing a good fit across various conditions. The research proceeded to predict the fatigue lifetime of wirebond structures under various thermal cyclic loading scenarios, adhering to JEDEC standards. Accumulated plastic strain at the wirebond heel was identified as a key lifetime prediction parameter, utilizing the Coffin-Manson relationship. The analysis revealed an exponential decrease in wirebond lifetime with increasing temperature difference (ΔT) and upper thermal cycle temperature. Finally, the study explored using tree-based machine learning (ML) regressors (Random Forest, Decision Tree, and XGBoost) to predict accumulated plastic strain, aiming to mitigate the need for computationally expensive FEA simulations. Trained on a small dataset from 11 FEA simulations, the Decision Tree model exhibited a reasonable prediction error of 2.4 %, suggesting the potential for ML to provide efficient and reasonably accurate lifetime predictions in power electronics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115954"},"PeriodicalIF":1.9,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145578951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As crucial packaging components of insulated gate bipolar transistor (IGBT) power modules, bonding wires are often confronted with strong load current from tens to hundreds of amperes. Thus, the reliability issues of bonding wires induced by electrical-mechanical coupling stress have become increasingly prominent. Nevertheless, the current mainstream research focuses on the reliability issues of bonding wires caused by electrical-thermal-mechanical (ETM) coupling stress, while neglecting electrical-magnetic-mechanical (EMM) coupling stress. In this article, for the first time, an in-depth investigation of EMM coupling stress of bonding wires in IGBT packaging modules is demonstrated by finite element simulation. The results indicate that the EMM coupling stress is mainly concentrated on the heel interfaces of bonding wires, presenting significantly quadratic and positive correlation with the intensity of load current. Furthermore, it is found that the stress fluctuation of bonding wires caused by EMM coupling is much larger than that caused by ETM coupling when IGBT modules operate at high switching frequency, providing confident evidence that the EMM stress on the bonding wires cannot be casually neglected and should be carefully taken into consideration. This work is bound to bring new insights and inspirations to electrical-mechanical coupling related reliability evaluation in power electronic devices.
{"title":"Electrical-magnetic-mechanical coupling stress of bonding wires in IGBT packaging modules","authors":"Cong Chen, Yuxin Luo, Jiahao Wang, Chaoyue Song, Bo Xu, Libing Bai, Yuhua Cheng","doi":"10.1016/j.microrel.2025.115953","DOIUrl":"10.1016/j.microrel.2025.115953","url":null,"abstract":"<div><div>As crucial packaging components of insulated gate bipolar transistor (IGBT) power modules, bonding wires are often confronted with strong load current from tens to hundreds of amperes. Thus, the reliability issues of bonding wires induced by electrical-mechanical coupling stress have become increasingly prominent. Nevertheless, the current mainstream research focuses on the reliability issues of bonding wires caused by electrical-thermal-mechanical (ETM) coupling stress, while neglecting electrical-magnetic-mechanical (EMM) coupling stress. In this article, for the first time, an in-depth investigation of EMM coupling stress of bonding wires in IGBT packaging modules is demonstrated by finite element simulation. The results indicate that the EMM coupling stress is mainly concentrated on the heel interfaces of bonding wires, presenting significantly quadratic and positive correlation with the intensity of load current. Furthermore, it is found that the stress fluctuation of bonding wires caused by EMM coupling is much larger than that caused by ETM coupling when IGBT modules operate at high switching frequency, providing confident evidence that the EMM stress on the bonding wires cannot be casually neglected and should be carefully taken into consideration. This work is bound to bring new insights and inspirations to electrical-mechanical coupling related reliability evaluation in power electronic devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115953"},"PeriodicalIF":1.9,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145578949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-15DOI: 10.1016/j.microrel.2025.115949
Waseem Abbas , Chang Lu , Yuluo Hou , Qian Xia , Ghulam Abbas Khan , Hiu Hung Lee , K.H. Loo
The reliability of Intelligent Power Modules (IPMs), critical for electric-vehicles (EVs), renewable-energy systems, and industrial-automation, is compromised by process-induced voids in die-attach joints. Previous research has investigated the thermo-mechanical behavior of solders/die-attach containing manufacturing induced voids, often by artificially creating excessive voids through simulation-analysis without sufficient experimental validation. Current electronic packages assembly standards, including IPC-A-610H, J-STD-001H, and IEC 61191–2, discontinue address voiding on account of conflicting perspectives and a lack of sufficient empirical findings. Given the lack of experimental evidence and conflicting industry perspectives, comprehensive data is essential to bridge this gap and refine void inspection standards. To address this critical issue, two commercially available 6-packed Insulated-Gate Bipolar Transistor (IGBT) IPM packages from different brands, featuring varying sizes and patterns of pre-existing die-attach voids, were selected. Two IGBTs from each brand were subjected to accelerated degradation testing based on power-cycling under identical stress levels, with the locality and frequency of solder/die-attach degradation monitored at certain intervals. Experimental observations reveal that small, distributive voids with specific patterns in solder joints exhibit negligible impact on die-attach degradation. Furthermore, these voids exhibit potential self-healing capabilities under moderate thermo-mechanical stress when Sn-based soldering materials are utilized. Conversely, large, dispersive voids without a specific pattern initiate solder damage and significantly reduce solder lifespan. Our findings highlight the need to consider void size and pattern in solder void inspection standards to improve power-device reliability. This study also provides the first experimental validation of self-healing in Sn-based solders under real-world power-cycling conditions, moving beyond previous simulations and theoretical analyses. This approach would enhance the reliability of power-devices for end user power-supply and management applications.
{"title":"Self-healing solder joints in power electronics: Experimental validation of die-attach void effects on reliability","authors":"Waseem Abbas , Chang Lu , Yuluo Hou , Qian Xia , Ghulam Abbas Khan , Hiu Hung Lee , K.H. Loo","doi":"10.1016/j.microrel.2025.115949","DOIUrl":"10.1016/j.microrel.2025.115949","url":null,"abstract":"<div><div>The reliability of Intelligent Power Modules (IPMs), critical for electric-vehicles (EVs), renewable-energy systems, and industrial-automation, is compromised by process-induced voids in die-attach joints. Previous research has investigated the thermo-mechanical behavior of solders/die-attach containing manufacturing induced voids, often by artificially creating excessive voids through simulation-analysis without sufficient experimental validation. Current electronic packages assembly standards, including IPC-A-610H, J-STD-001H, and IEC 61191–2, discontinue address voiding on account of conflicting perspectives and a lack of sufficient empirical findings. Given the lack of experimental evidence and conflicting industry perspectives, comprehensive data is essential to bridge this gap and refine void inspection standards. To address this critical issue, two commercially available 6-packed Insulated-Gate Bipolar Transistor (IGBT) IPM packages from different brands, featuring varying sizes and patterns of pre-existing die-attach voids, were selected. Two IGBTs from each brand were subjected to accelerated degradation testing based on power-cycling under identical stress levels, with the locality and frequency of solder/die-attach degradation monitored at certain intervals. Experimental observations reveal that small, distributive voids with specific patterns in solder joints exhibit negligible impact on die-attach degradation. Furthermore, these voids exhibit potential self-healing capabilities under moderate thermo-mechanical stress when Sn-based soldering materials are utilized. Conversely, large, dispersive voids without a specific pattern initiate solder damage and significantly reduce solder lifespan. Our findings highlight the need to consider void size and pattern in solder void inspection standards to improve power-device reliability. This study also provides the first experimental validation of self-healing in Sn-based solders under real-world power-cycling conditions, moving beyond previous simulations and theoretical analyses. This approach would enhance the reliability of power-devices for end user power-supply and management applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115949"},"PeriodicalIF":1.9,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145528246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1016/j.microrel.2025.115948
Chieh-Chen Ker , Chun-Yu Lin , Ming-Duo Ker , Yu-Hsuan Chang , Ching-Wei Li , Tsung-Yin Chiang , Chun-Chi Wang
A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.
{"title":"Gate-to-source ESD protection design for GaN-on-silicon power HEMT","authors":"Chieh-Chen Ker , Chun-Yu Lin , Ming-Duo Ker , Yu-Hsuan Chang , Ching-Wei Li , Tsung-Yin Chiang , Chun-Chi Wang","doi":"10.1016/j.microrel.2025.115948","DOIUrl":"10.1016/j.microrel.2025.115948","url":null,"abstract":"<div><div>A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115948"},"PeriodicalIF":1.9,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145528247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-12DOI: 10.1016/j.microrel.2025.115951
Weiwei Wei , Shilin Liu , Guoqing Xu , Hongtao Liu
Junction temperature (Tj) is a key parameter to judge the reliability of power MOSFET. However, extracting the junction temperature of a power MOSFET in real-time remains a challenge. To address this challenge, this manuscript proposes an online method to extract the junction temperature of a power MOSFET using calculated turn-off time (tcoff). This manuscript makes three main contributions: 1) The influence of junction temperature on the turn-off process of power MOSFET is analyzed. The calculated turn-off time is proposed as a temperature-sensitive electrical parameter (TSEP) to extract the junction temperature. 2) The high-frequency response of the circuit parasitic parameters caused by the switching process of the power MOSFET is analyzed. An online calculated turn-off time measurement method is proposed. 3) Experiments confirm that calculated turn-off time, as TSEP, offers advantages such as high sensitivity and good linearity. Additionally, the effectiveness of the online measurement method for calculated turn-off time was verified, and an experiment was conducted to extract the junction temperature online.
{"title":"Online extraction of power MOSFET junction temperature using calculated turn-off time","authors":"Weiwei Wei , Shilin Liu , Guoqing Xu , Hongtao Liu","doi":"10.1016/j.microrel.2025.115951","DOIUrl":"10.1016/j.microrel.2025.115951","url":null,"abstract":"<div><div>Junction temperature (<em>T</em><sub>j</sub>) is a key parameter to judge the reliability of power MOSFET. However, extracting the junction temperature of a power MOSFET in real-time remains a challenge. To address this challenge, this manuscript proposes an online method to extract the junction temperature of a power MOSFET using calculated turn-off time (<em>t</em><sub>coff</sub>). This manuscript makes three main contributions: 1) The influence of junction temperature on the turn-off process of power MOSFET is analyzed. The calculated turn-off time is proposed as a temperature-sensitive electrical parameter (TSEP) to extract the junction temperature. 2) The high-frequency response of the circuit parasitic parameters caused by the switching process of the power MOSFET is analyzed. An online calculated turn-off time measurement method is proposed. 3) Experiments confirm that calculated turn-off time, as TSEP, offers advantages such as high sensitivity and good linearity. Additionally, the effectiveness of the online measurement method for calculated turn-off time was verified, and an experiment was conducted to extract the junction temperature online.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115951"},"PeriodicalIF":1.9,"publicationDate":"2025-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145528248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-08DOI: 10.1016/j.microrel.2025.115946
Danni Cao , Ping Wu , Linjie Liao , Zhen Liu , Yiou Qiu , Linzheng Fu , Wenhui Zhu , Liancheng Wang
With the rapid development of artificial intelligence, cloud computing, 5G, and new energy industries, power modules face multiple technical challenges including increasing power density, higher integration levels, and long-term reliability. To meet miniaturization requirements, industry has developed technologies such as double-sided plastic encapsulation and component-on-package (CoP) to enhance integration. Although system-in-package (SiP) technology enables compact size and high performance for power modules, it introduces interfacial reliability degradation under harsh environmental conditions (e.g., humidity and thermal cycling). To address this issue, this study combined finite element analysis (FEA) with reliability testing conducted according to JEDEC standards to systematically evaluate failure mechanisms under complex operating conditions. Testing revealed that after MSL1 moisture absorption treatment, extensive delamination occurred during three reflow soldering processes. Through establishing three physical models—85 °C/85 % RH hygrothermal diffusion model, reflow desorption model, and peak-temperature vapor pressure model—the stress distribution and crack propagation under thermo-hygro-vapor pressure coupling were elucidated. Key findings include: Moisture diffusion exhibited low concentration gradients within 100 h due to inorganic material barrier effects; Moisture loss rate during reflow demonstrated nonlinear growth with temperature, reaching maximum at peak temperature; Equivalent coefficient of thermal expansion (CTE) analysis quantified stress ratios as 1:1.07:0.84 (thermal-hygro-vapor), revealing that crack propagation is primarily driven by shear stress-dominated GII mode. Notably, the strain energy release rate (SERR) under multi-field coupling exceeded the linear superposition values of individual fields by 304 %, demonstrating that synergistic effects significantly accelerate interfacial delamination failure risks.
{"title":"Research on hygrothermal reliability of double-sided molded power modules","authors":"Danni Cao , Ping Wu , Linjie Liao , Zhen Liu , Yiou Qiu , Linzheng Fu , Wenhui Zhu , Liancheng Wang","doi":"10.1016/j.microrel.2025.115946","DOIUrl":"10.1016/j.microrel.2025.115946","url":null,"abstract":"<div><div>With the rapid development of artificial intelligence, cloud computing, 5G, and new energy industries, power modules face multiple technical challenges including increasing power density, higher integration levels, and long-term reliability. To meet miniaturization requirements, industry has developed technologies such as double-sided plastic encapsulation and component-on-package (CoP) to enhance integration. Although system-in-package (SiP) technology enables compact size and high performance for power modules, it introduces interfacial reliability degradation under harsh environmental conditions (e.g., humidity and thermal cycling). To address this issue, this study combined finite element analysis (FEA) with reliability testing conducted according to JEDEC standards to systematically evaluate failure mechanisms under complex operating conditions. Testing revealed that after MSL1 moisture absorption treatment, extensive delamination occurred during three reflow soldering processes. Through establishing three physical models—85 °C/85 % RH hygrothermal diffusion model, reflow desorption model, and peak-temperature vapor pressure model—the stress distribution and crack propagation under thermo-hygro-vapor pressure coupling were elucidated. Key findings include: Moisture diffusion exhibited low concentration gradients within 100 h due to inorganic material barrier effects; Moisture loss rate during reflow demonstrated nonlinear growth with temperature, reaching maximum at peak temperature; Equivalent coefficient of thermal expansion (CTE) analysis quantified stress ratios as 1:1.07:0.84 (thermal-hygro-vapor), revealing that crack propagation is primarily driven by shear stress-dominated G<sub>II</sub> mode. Notably, the strain energy release rate (SERR) under multi-field coupling exceeded the linear superposition values of individual fields by 304 %, demonstrating that synergistic effects significantly accelerate interfacial delamination failure risks.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115946"},"PeriodicalIF":1.9,"publicationDate":"2025-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-08DOI: 10.1016/j.microrel.2025.115950
Shweta, Sunil Jadav
In response to the growing need for flexible and wearable electronics, multifunctional sensing films have been developed. For ensuring the reliability of the sensing films on flexible substrate, the bending analysis becomes highly significant. This research presents the bending analysis of SnO2 Quantum dots (QDs) to assess their suitability as gas and strain sensors. Determining the mechanical durability and failure lifespan of flexible devices thus requires a precise assessment of bending-induced strain and the associated resistance change. The impact of various bending factors such as bending radius, substrate thickness, and film thickness on strain is examined. The findings demonstrate that thinner substrates and films may withstand greater strain without experiencing structural failure, which qualifies them for flexible gas sensing applications. The reverse design approach is also specified that will help the researchers to optimize the design structure as per performance requirement. Furthermore, the resistance changes of SnO2 QDs with strain is modeled using a calibration-based technique, utilizing reference data from carbon nanocoil (CNC) and single-walled carbon nanotube (SWCNT) film and the observed results are validated with experimental data of SnO2 QDs. With a consistent response value of 0.96 for SnO2 QDs throughout bending radii between 2 mm and 40 mm, the modeled sensor validates the feasibility of SnO2 QDs for flexible and wearable gas sensor applications and demonstrates that gas sensing performance is strain-insensitive.
{"title":"SnO2 quantum dots under mechanical bending: Modeling and application in flexible sensors","authors":"Shweta, Sunil Jadav","doi":"10.1016/j.microrel.2025.115950","DOIUrl":"10.1016/j.microrel.2025.115950","url":null,"abstract":"<div><div>In response to the growing need for flexible and wearable electronics, multifunctional sensing films have been developed. For ensuring the reliability of the sensing films on flexible substrate, the bending analysis becomes highly significant. This research presents the bending analysis of SnO<sub>2</sub> Quantum dots (QDs) to assess their suitability as gas and strain sensors. Determining the mechanical durability and failure lifespan of flexible devices thus requires a precise assessment of bending-induced strain and the associated resistance change. The impact of various bending factors such as bending radius, substrate thickness, and film thickness on strain is examined. The findings demonstrate that thinner substrates and films may withstand greater strain without experiencing structural failure, which qualifies them for flexible gas sensing applications. The reverse design approach is also specified that will help the researchers to optimize the design structure as per performance requirement. Furthermore, the resistance changes of SnO<sub>2</sub> QDs with strain is modeled using a calibration-based technique, utilizing reference data from carbon nanocoil (CNC) and single-walled carbon nanotube (SWCNT) film and the observed results are validated with experimental data of SnO<sub>2</sub> QDs. With a consistent response value of 0.96 for SnO<sub>2</sub> QDs throughout bending radii between 2 mm and 40 mm, the modeled sensor validates the feasibility of SnO<sub>2</sub> QDs for flexible and wearable gas sensor applications and demonstrates that gas sensing performance is strain-insensitive.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115950"},"PeriodicalIF":1.9,"publicationDate":"2025-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1016/j.microrel.2025.115945
Zhen Xu , Man Luo , Jining Li , Kai Chen , Longhai Liu , Chao Yan , Degang Xu , Jianquan Yao
With the advancement of technology, integrated circuit technology is developing towards smaller feature sizes, higher integration levels, and lower power consumption. The issue of wire voids has become increasingly prominent, and traditional detection methods can no longer meet the growing demand for accurate detection. This study utilizes the time-domain pulse reflection technology combined with experimental testing, theoretical calculations, and simulations to locate and detect wire voids of different sizes and positions in integrated circuit wires with different parameters. The research results show that with the size of the void increasing, the reflected signal lags slightly behind compared to that of a smaller void. When the size of the wire void is 100 μm, the test error for a substrate dielectric constant of 2.2 is greater than that for a dielectric constant of 3. When the void size is 150 μm, the test error for a substrate dielectric constant of 2.2 is smaller than that for a dielectric constant of 3. When the dielectric constant of the substrate is 2.2 and the void size is 150 μm, the minimum distance test deviation is only 34.819 μm, and the position error is only 0.35 %. The farther the void position is from the test point, the greater the error. This study utilizes terahertz pulse time - domain reflection technology to detect tiny voids and fault locations in integrated circuits, which is of great significance for ensuring the quality of integrated circuits and promoting the sustainable development of electronic technology.
{"title":"Terahertz pulse time-domain reflection for accurate detection of wire voids in integrated circuits: A simulation and experimental validation","authors":"Zhen Xu , Man Luo , Jining Li , Kai Chen , Longhai Liu , Chao Yan , Degang Xu , Jianquan Yao","doi":"10.1016/j.microrel.2025.115945","DOIUrl":"10.1016/j.microrel.2025.115945","url":null,"abstract":"<div><div>With the advancement of technology, integrated circuit technology is developing towards smaller feature sizes, higher integration levels, and lower power consumption. The issue of wire voids has become increasingly prominent, and traditional detection methods can no longer meet the growing demand for accurate detection. This study utilizes the time-domain pulse reflection technology combined with experimental testing, theoretical calculations, and simulations to locate and detect wire voids of different sizes and positions in integrated circuit wires with different parameters. The research results show that with the size of the void increasing, the reflected signal lags slightly behind compared to that of a smaller void. When the size of the wire void is 100 μm, the test error for a substrate dielectric constant of 2.2 is greater than that for a dielectric constant of 3. When the void size is 150 μm, the test error for a substrate dielectric constant of 2.2 is smaller than that for a dielectric constant of 3. When the dielectric constant of the substrate is 2.2 and the void size is 150 μm, the minimum distance test deviation is only 34.819 μm, and the position error is only 0.35 %. The farther the void position is from the test point, the greater the error. This study utilizes terahertz pulse time - domain reflection technology to detect tiny voids and fault locations in integrated circuits, which is of great significance for ensuring the quality of integrated circuits and promoting the sustainable development of electronic technology.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115945"},"PeriodicalIF":1.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1016/j.microrel.2025.115942
Shi-Jin Liu , Ying Wang , Cheng-Hao Yu , Hao-Min Guo
This article investigates the influence mechanism of substrate bias on the electrical characteristics of p-GaN HEMT devices, and uses the Sentaurus Technology Computer Aided Design (Sentaurus TCAD) and Stopping and Range of Ions in Matter (SRIM) joint simulation method to simulate the single-event effects (SEE) of devices under different substrate biases. Research has found that the device's threshold voltage is more stable under a positive substrate bias, and the vertical leakage current is lower. Furthermore, based on experimental testing, a Sentaurus TCAD and SRIM joint simulation was conducted to analyze the impact mechanism of different substrate biases on the device's SEE. Compared with the substrate-free electrode structure, the gate and drain currents are significantly reduced, reducing the possibility of device burnout at the drain and gate. In addition, the increase in source current and substrate current accelerates charge collection. Therefore, by designing and applying substrate bias reasonably, the stability and reliability of the device in both radiation and non-radiation environments can be effectively improved.
{"title":"Mechanism analysis and single event effect simulation of p-GaN HEMT devices under substrate bias conditions","authors":"Shi-Jin Liu , Ying Wang , Cheng-Hao Yu , Hao-Min Guo","doi":"10.1016/j.microrel.2025.115942","DOIUrl":"10.1016/j.microrel.2025.115942","url":null,"abstract":"<div><div>This article investigates the influence mechanism of substrate bias on the electrical characteristics of p-GaN HEMT devices, and uses the Sentaurus Technology Computer Aided Design (Sentaurus TCAD) and Stopping and Range of Ions in Matter (SRIM) joint simulation method to simulate the single-event effects (SEE) of devices under different substrate biases. Research has found that the device's threshold voltage is more stable under a positive substrate bias, and the vertical leakage current is lower. Furthermore, based on experimental testing, a Sentaurus TCAD and SRIM joint simulation was conducted to analyze the impact mechanism of different substrate biases on the device's SEE. Compared with the substrate-free electrode structure, the gate and drain currents are significantly reduced, reducing the possibility of device burnout at the drain and gate. In addition, the increase in source current and substrate current accelerates charge collection. Therefore, by designing and applying substrate bias reasonably, the stability and reliability of the device in both radiation and non-radiation environments can be effectively improved.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115942"},"PeriodicalIF":1.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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