Microelectronics Reliability最新文献_第7页

Theoretical performance and reliability optimization of graphene based electrically doped tunnel FET under interface trap charge constraints: A device-level approach 界面阱电荷约束下石墨烯基电掺杂隧道场效应管的理论性能和可靠性优化：器件级方法

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-09 DOI: 10.1016/j.microrel.2025.115928

Bandi Venkata Chandan, Kaushal Kumar Nigam, Bibhudendra Acharya, Adil Tanveer

This article investigates the performance of graphene based electrostatic doped tunnel field-effect transistors (G-ED-TFET) for energy-efficient applications. In this design, the drain and source regions are induced by applying polarity gate (PG) bias voltages, respectively. This approach eliminates doping control issues, reduces thermal budget constraints, and simplifies fabrication compared to conventional TFETs. Graphene is utilized in the channel region as a promising alternative material to silicon (Si) due to exceptional characteristics such as high electron mobility and a zero band gap. The G-ED-TFET device achieve an ON current of 1.34 ×

1 0^{- 5}

A/

μ m

, threshold voltage (V

_{t h}

) of 0.32 V, subthreshold swing (SS) of 3.34 mV/decade, and a switching ratio of 2.86 ×

1 0^{14}

. Analog/RF metrics suggest that their is minimum 10

\times

improvement in every figure-of-metrics because graphene has an intrinsically small bandgap, which allows efficient tunneling from the P

^{+}

source to the graphene channel. To further use of G-ED-TFET device, it is important to assess its reliability for which we have chosen interface trap charges (ITCs) approach. In the presence of ITCs, G-ED-TFET shows less variation, as compare to ED-TFET indicates that the G-ED-TFET is more reliable. Overall, this work offers significant insights into the analog/RF characteristics of G-ED-TFET, enabling the development of optimized devices and ensuring dependable performance in many applications.

本文研究了基于石墨烯的静电掺杂隧道场效应晶体管（G-ED-TFET）在节能应用中的性能。在本设计中，漏极区和源极区分别通过施加极性门（PG）偏置电压来感应。与传统tfet相比，这种方法消除了掺杂控制问题，减少了热预算限制，并简化了制造过程。石墨烯由于具有高电子迁移率和零带隙等特殊特性，在通道区域被用作硅（Si）的有前途的替代品。该器件的ON电流为1.34 × 10−5 A/μm，阈值电压（Vth）为0.32 V，亚阈值摆幅（SS）为3.34 mV/decade，开关比为2.86 × 1014。模拟/射频指标表明，由于石墨烯具有固有的小带隙，因此可以从P+源有效地隧穿到石墨烯通道，因此每个指标的改进幅度至少为10倍。为了进一步使用G-ED-TFET器件，我们选择了界面陷阱电荷（ITCs）方法来评估其可靠性是很重要的。在ITCs存在的情况下，G-ED-TFET表现出较小的变化，与ED-TFET相比表明G-ED-TFET更可靠。总的来说，这项工作为G-ED-TFET的模拟/射频特性提供了重要的见解，使优化器件的开发成为可能，并确保在许多应用中具有可靠的性能。

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引用次数: 0

Improving transformer model reliability on NVIDIA Jetson AGX: Insights from single event effects with two-photon absorption laser analysis 提高NVIDIA Jetson AGX上变压器模型的可靠性：双光子吸收激光分析单事件效应的见解

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-08 DOI: 10.1016/j.microrel.2025.115929

Haonan Tian , Younis Ibrahim , Manasi Sharma , George Belev , Shijie Wen , Li Chen

This paper investigates the susceptibility of Transformer models, specifically DistilBERT, to Single Event Effects (SEEs) on the NVIDIA Jetson AGX Xavier, which poses significant risks in radiation-prone environments such as aerospace. One critical challenge is Silent Data Corruption (SDC), where errors caused by radiation may go undetected, potentially degrading model performance without immediate signs of failure. Using Two-Photon Absorption (TPA) laser testing, we analysed the model's robustness and innovatively proposed evaluating the impact of soft errors on the model by calculating the Euclidean distance (L2 distance) between the output tensor of each layer and its reference value. This approach allows us to assess the severity of soft errors on model performance. Our results reveal that critical errors significantly escalate when the L2 distance exceeds 1.0, highlighting the model's vulnerability to such disruptions. To address these issues, we firstly propose a layer-level Triple Modular Redundancy (TMR) strategy, achieving an 89.2 % reduction in error rates. Meanwhile, to alleviate the issue of excessive overhead in the TMR model, we introduce a Hybrid Selected Dual Modular Redundancy (HS-DMR) technique, which activates TMR operation only when the L2 distance threshold is surpassed. This approach maintains 85.8 % decrease of critical error rate with only 3.6 % latency overhead.

本文研究了变压器模型，特别是蒸馏器，对NVIDIA Jetson AGX Xavier上的单事件效应（SEEs）的敏感性，这在辐射易发环境（如航空航天）中构成重大风险。一个关键的挑战是无声数据损坏（SDC），其中由辐射引起的错误可能未被检测到，可能会在没有立即出现故障迹象的情况下降低模型性能。利用双光子吸收（TPA）激光测试分析了模型的鲁棒性，并创新地提出了通过计算每层输出张量与其参考值之间的欧几里得距离（L2距离）来评估软误差对模型影响的方法。这种方法允许我们评估模型性能上软错误的严重程度。我们的研究结果表明，当L2距离超过1.0时，临界误差显著上升，突出了模型对此类中断的脆弱性。为了解决这些问题，我们首先提出了一种层级三模冗余（TMR）策略，使错误率降低了89.2%。同时，为了缓解TMR模型中过大的开销问题，我们引入了一种混合选择双模冗余（HS-DMR）技术，该技术仅在超过L2距离阈值时才激活TMR操作。这种方法使临界错误率降低了85.8%，而延迟开销仅为3.6%。

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引用次数: 0

The thermal cycling response of Sn-Zn, Sn-Ag-Cu and Sn-Bi solder in industrial production 工业生产中Sn-Zn、Sn-Ag-Cu和Sn-Bi焊料的热循环响应

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-04 DOI: 10.1016/j.microrel.2025.115925

Tianyuan Chen , Mengran Zhou , Hao Fu , Xiaohua Xu , Xinhua Dong , Yunjian Zhao , Gaoqiang Chen , Gong Zhang , Qingyu Shi

The reliability of different solder joints assembled with Sn-Zn, Sn-Ag-Cu, and Sn-Bi solders under thermal cycling conditions based on industrial production conditions was analyzed in this study. The results of dye and pull test indicated that there were significant differences in the number, types, and location of fractures at different component joints soldered with different solder. Due to the excellent mechanical properties and unique intermetallic compound (IMC) composition, the number of fractures in Sn-Zn solder joints is remarkably lower than the Sn-Ag-Cu and Sn-Bi solder, indicating that the Sn-Zn system is more reliable under thermal cycling. These findings demonstrated that Sn-Zn solder is more suitable for industrial production of the complex printed circuit boards (PCBs) and has a better durability.

本文以工业生产条件为基础，分析了不同Sn-Zn、Sn-Ag-Cu和Sn-Bi焊料在热循环条件下的焊接可靠性。染色和拉拔试验结果表明，不同焊料焊接的不同组份接头的断口数量、断口类型和断口位置存在显著差异。由于优异的力学性能和独特的金属间化合物（IMC）组成，Sn-Zn焊点的断口数量明显低于Sn-Ag-Cu和Sn-Bi焊点，表明Sn-Zn体系在热循环下更加可靠。研究结果表明，锡锌焊料更适合于复杂印刷电路板的工业生产，并且具有更好的耐用性。

引用次数: 0

Exploring the use of extreme temperatures to facilitate fault propagation in ReRAMs 探索在reram中使用极端温度来促进故障传播

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-09-29 DOI: 10.1016/j.microrel.2025.115919

T.S. Copetti , A. Chordia , M. Fieback , M. Taouil , S. Hamdioui , L.M. Bolzani Poehls

Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories adopted in several emerging applications. Despite all their advantages – mainly CMOS process compatibility, zero standby power, and high scalability and density – the use of ReRAMs in real applications depends on guaranteeing their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, including defects and process variations, that can cause faulty behaviors different from those observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into conventional and unique faults, considering three different temperatures (25, 100, and -40 °C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.

电阻式随机存取存储器（reram）是补充和/或取代几种新兴应用中采用的基于cmos的存储器的有希望的候选者。尽管reram具有各种优势——主要是CMOS工艺兼容性、零待机功耗、高可扩展性和密度——但在实际应用中使用reram取决于在制造后保证其质量。正如在基于CMOS的存储器中观察到的那样，reram也容易受到制造偏差的影响，包括缺陷和工艺变化，这可能导致与CMOS技术中观察到的错误行为不同，不仅增加了制造测试的复杂性，而且增加了执行测试所需的时间。在此背景下，本文提出研究利用温度促进reram中的故障传播，减少所需的测试时间。采用基于130 nm预测技术模型（PTM）库实现的3x3基于单词的ReRAM外围电路的案例研究。在所提出的研究中，在ReRAM单元的不同位置注入了17个缺陷，并考虑到三种不同的温度（25、100和-40°C），将其各自的故障行为分为常规故障和独特故障。结果表明，根据缺陷的位置，温度可以促进故障的传播，从而减少了进行制造测试所需的时间。

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引用次数: 0

Ionizing radiation damage and accuracy degradation in PMOS dosimeter constant current sources under bias-dose rate coupling 偏置-剂量率耦合下PMOS剂量计恒流源电离辐射损伤与精度退化

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-09-25 DOI: 10.1016/j.microrel.2025.115922

Jing Sun , Xingyao Zhang , Mengjun Sun , Gang Yu , Yiyuan Wang , Lin Wen , Xuefeng Yu , Qi Guo , Yudong Li

As an important part of PMOS dosimeter, the radiation resistance of constant current source directly affects its measurement accuracy. This paper mainly analyzes the damage variation law of constant current source in space radiation environment, and studies the ionizing radiation effect of constant current source under different bias and dose rate. The results show that the three-terminal adjustable constant current source increases the percentage of current change caused by ionizing radiation when the constant current source is set to operate at a small current, causing more serious degradation.

恒流源作为PMOS剂量计的重要组成部分，其辐射电阻直接影响其测量精度。本文主要分析了恒流源在空间辐射环境中的损伤变化规律，研究了不同偏压和剂量率下恒流源的电离辐射效应。结果表明，当三端可调恒流源设置为小电流工作时，电离辐射引起的电流变化百分比增加，导致更严重的退化。

引用次数: 0

Effect of Bi element on microstructure, strength and failure mechanism of Sn-Cu-In solder alloy Bi元素对Sn-Cu-In钎料合金组织、强度及失效机理的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-09-25 DOI: 10.1016/j.microrel.2025.115924

Jinlong Zhang , Chenghao Zhang , Zhen Pan , Chun Li , Xiaoqing Si , Zongjing He , Yang Liu , Jian Cao

In this paper, the changes of the microstructure, wettability, and mechanical properties, of the Sn-0.5Cu-3In solder alloy were studied after adding 0.3–0.7 wt% Bi. The addition of Bi to Sn-0.5Cu-3In solder alloy resulted in changes to the microstructure, with a decrease in grain size and an increase in uniformity. The β-Sn phase size also decreased, and the distribution of intermetallic compounds became denser. When the amount of Bi element added is less than 0.5 wt%, the impact performance of the solder alloy changes little, and the impact work reaches a maximum of 62.2 J when 0.5 wt% Bi is added. The shear test results of the solder joints show that the addition of Bi element effectively improves the reliability of the solder joints, and the shear strength reaches a maximum value of 46.8 MPa at the addition of 0.5 wt% of Bi element. This is because the Bi and β-Sn forms a solid solution, resulting in solid solution strengthening. And the Bi element refines the grains of the solder alloy, so the shear strength of the solder joint is significantly improved.

本文研究了添加0.3 ~ 0.7 wt% Bi后Sn-0.5Cu-3In钎料合金的显微组织、润湿性和力学性能的变化。在Sn-0.5Cu-3In钎料合金中添加Bi后，钎料合金的显微组织发生了变化，晶粒尺寸减小，均匀性提高。β-Sn相尺寸减小，金属间化合物分布更加致密。当Bi元素添加量小于0.5 wt%时，钎料合金的冲击性能变化不大，当Bi元素添加量为0.5 wt%时，冲击功达到最大62.2 J。焊点的剪切试验结果表明，添加Bi元素有效提高了焊点的可靠性，当添加0.5% wt%的Bi元素时，焊点的剪切强度达到了46.8 MPa的最大值。这是因为Bi与β-Sn形成固溶体，导致固溶体强化。Bi元素细化了钎料合金的晶粒，显著提高了焊点的抗剪强度。

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引用次数: 0

Research on the lifetime model of IGBT modules based on coupling failure of bonding wire and solder layer 基于焊线与焊层耦合失效的IGBT模块寿命模型研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-09-24 DOI: 10.1016/j.microrel.2025.115923

Biao Li , Zhaolei Zheng , Feng Wang , Zhuangzhuang Li , Jun Liu

To address the issues of insulated gate bipolar transistor module failure and lifetime prediction, a physical model of the insulated gate bipolar transistor module has been established. Through thermo-electrical structural coupling simulations, the failure mechanisms of the bonding wire and solder layer have been analyzed. Based on the failure mechanisms of both components, a lifetime model for insulated gate bipolar transistor modules, considering the coupling failures of the bonding wire and solder layer, has been constructed. Additionally, the failure model has been fitted using data from power cycling tests, and a comparative analysis has been conducted between the parallel failure lifetime model and the energy-based lifetime model and Coffin-Manson lifetime model in terms of prediction accuracy. The results indicate that the insulated gate bipolar transistor module lifetime model based on parallel failures of the bonding wire and solder layer has an average error of less than 5 %, reducing the error by 7.74 % compared to the classical lifetime model. Furthermore, it shows a 59.38 % reduction in error compared to the energy-based lifetime model that considers only solder layer failure, significantly improving prediction accuracy. The development of the model and its results provide important reference significance for the reliability assessment of insulated gate bipolar transistor modules.

为了解决绝缘栅双极晶体管模块失效和寿命预测问题，建立了绝缘栅双极晶体管模块的物理模型。通过热电结构耦合仿真，分析了焊线和焊层的失效机理。基于这两种器件的失效机理，建立了考虑键合线和焊层耦合失效的绝缘栅双极晶体管模块寿命模型。利用动力循环试验数据拟合了失效模型，并将并联失效寿命模型与基于能量的寿命模型和Coffin-Manson寿命模型在预测精度方面进行了对比分析。结果表明，基于键合线和焊料层并行失效的绝缘栅双极晶体管模块寿命模型平均误差小于5%，比经典寿命模型误差减小7.74%。此外，与仅考虑焊料层失效的基于能量的寿命模型相比，该模型的误差降低了59.38%，显著提高了预测精度。该模型的建立及其结果对绝缘栅双极晶体管模块的可靠性评估具有重要的参考意义。

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引用次数: 0

An FPGA-based architecture for time-resolved polarization probing of FeRAM fatigue 基于fpga的FeRAM疲劳时间分辨极化探测结构

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-09-24 DOI: 10.1016/j.microrel.2025.115920

Yubin Liao , Zerong He , Xiangyin Chen , Zhongguang Xu

Traditional approaches to assessing Ferroelectric RAM (FeRAM) reliability rely on direct electrical access to individual capacitors. While effective on isolated test structures, such methods are infeasible for high-density, packaged memory arrays, creating a critical gap between device-level physics and system-level reliability assessment. To bridge this gap, we propose Time-Resolved Polarization Probing (TRPP), a novel indirect methodology that infers the internal polarization state by precisely measuring the minimum switching time accessible at the cell terminals. We implement TRPP on a custom FPGA-based platform that integrates a flexible MBIST engine for controlled fatigue stressing with a carry-chain programmable delay generator offering 53 ps resolution. Experimental results on FeRAM devices demonstrate that TRPP effectively quantifies the progressive degradation of polarization kinetics under stress up to

1 0^{9}

cycles. The measurements further reveal disproportionately severe degradation at lower operating voltages, underscoring critical implications for low-power and compute-in-memory applications. Overall, this work establishes TRPP as a high-resolution, scalable methodology for reliability characterization, bridging the gap between device physics and system-level deployment.

评估铁电RAM （FeRAM）可靠性的传统方法依赖于对单个电容器的直接电访问。虽然这种方法在孤立的测试结构上是有效的，但对于高密度、封装的存储器阵列来说是不可行的，这在设备级物理和系统级可靠性评估之间造成了严重的差距。为了弥补这一差距，我们提出了时间分辨极化探测（TRPP），这是一种新的间接方法，通过精确测量细胞终端可访问的最小开关时间来推断内部极化状态。我们在一个定制的基于fpga的平台上实现TRPP，该平台集成了一个灵活的MBIST引擎，用于控制疲劳应力和提供53 ps分辨率的携带链可编程延迟发生器。在FeRAM设备上的实验结果表明，TRPP可以有效地量化在109次循环的应力下极化动力学的逐步退化。测量进一步揭示了在较低工作电压下不成比例的严重退化，强调了低功耗和内存计算应用的关键含义。总的来说，这项工作将TRPP确立为一种高分辨率、可扩展的可靠性表征方法，弥合了设备物理和系统级部署之间的差距。

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引用次数: 0

The dynamic and static radiation damage of silicon carbide MOSFETs with different gate oxide thickness 不同栅氧化层厚度碳化硅mosfet的动态和静态辐射损伤

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-09-17 DOI: 10.1016/j.microrel.2025.115918

Dan Zhang , Yudong Li , Haonan Feng , Xiaowen Liang , Chengcheng Shi , Yu Song , Ying Wei , Dong Zhou , Jingyi Xu , Yongheng Luo , Jie Feng , Xuefeng Yu , Qi Guo , Teng Zhang , Bo Wang

Radiation effects are a critical issue for SiC MOSFETs in space and nuclear applications. The thickness of the oxide layer is an important factor affecting the radiation resistance of SiC MOSFETs. The thickness of the gate oxide layer will affect the radiation effects of Si MOSFETs, to study the effects of different gate oxide thickness (t_ox) on the total dose radiation damage of SiC MOSFETs, In this paper, we demonstrate the effects of two different t_ox with 50 nm and 70 nm on the dynamic and static characteristics of SiC vertical double-diffused MOS (VDMOS) after gamma irradiation, and the total dose effect radiation damage mechanism is revealed through experiments and simulations, the main reasons for the degradation of static parameters and dynamic characteristics of the devices are identified. The results indicate that gate oxide thickness will also impact the radiation effects of SiC MOSFETs significantly, a thicker gate oxide layer accumulates more captured charge under the total ionizing dose (TID), thus producing a more severe performance degradation. The results can provide a basis for the optimization of the gate oxide thickness and the application of TID radiation-resistant of SiC MOSFETs.

辐射效应是SiC mosfet在空间和核应用中的关键问题。氧化层厚度是影响SiC mosfet抗辐射性能的重要因素。栅氧化层的厚度会影响硅场效应管的辐射效应,研究不同的栅氧化层厚度的影响(托克斯)碳化硅的总剂量辐射损伤场效电晶体,在本文中,我们将演示两种不同的影响与50和70 nm托克斯SiC的动态和静态特性垂直双扩散MOS (VDMOS)γ辐照后,和总剂量效应辐射损伤机制是通过实验和模拟显示,找出了导致设备静态参数和动态特性退化的主要原因。结果表明，栅极氧化层厚度也会显著影响SiC mosfet的辐射效应，在总电离剂量（TID）下，越厚的栅极氧化层会积累更多的捕获电荷，从而导致更严重的性能下降。研究结果可为SiC mosfet栅极氧化层厚度的优化及抗TID辐射的应用提供依据。

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引用次数: 0

An informer network-based circuit boards fault detection method using infrared temperature series 基于信息网络的红外温度序列线路板故障检测方法

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-09-17 DOI: 10.1016/j.microrel.2025.115890

Shengze Yang , Chenxiao Li , Yangyi Zhu , Hangtian Shen , Liyong Fang

As industrial demand for circuit board fault detection increases, infrared thermography has become a crucial non-invasive technique for the efficient identification of internal faults. However, existing methods exhibit limitations in feature extraction, local detail capture, and the modeling of correlations between chips and faults. To address these challenges, a comprehensive method that integrates a preprocessing stage and an enhanced Informer-based model, termed Informer-Fault-Net, is proposed. This method begins with preprocessing the long-term time-series heating data of components, which is collected by infrared cameras during power-on cycles. Subsequently, the processed data is fed into the Informer-Fault-Net model to identify faulty components on circuit boards. Within this network, a Statistic-SENet module is designed to pre-condition the input data by leveraging multiple statistical characteristics of component temperatures, and a channel attention mechanism is embedded within this module to strengthen the correlation between different chips and faults, thereby improving detection accuracy and robustness. Simultaneously, a Fully Convolutional Network (FCN) and an improved distillation mechanism are incorporated into the Informer encoder to enhance the model's capacity for local feature extraction and to reduce computational cost. A multi-scale feature fusion strategy is also employed to improve the model's ability to capture features across multiple scales. To validate the effectiveness of the proposed method, we designed and implemented an experimental hardware platform to collect a temperature time-series dataset from the components of circuit boards for fault detection. Finally, a series of experiments showed that the proposed method achieved an accuracy of 0.990.

随着工业对电路板故障检测需求的增加，红外热成像技术已成为有效识别电路板内部故障的一种重要的非侵入性技术。然而，现有的方法在特征提取、局部细节捕获和芯片与故障之间的相关性建模方面存在局限性。为了应对这些挑战，提出了一种综合方法，该方法集成了预处理阶段和增强的基于信息者的模型，称为信息者-故障网络。该方法首先对上电周期红外摄像机采集的部件长期时序加热数据进行预处理。随后，处理后的数据被输入信息者-故障网络模型，以识别电路板上的故障组件。在该网络中，设计了Statistic-SENet模块，利用组件温度的多个统计特征对输入数据进行预处理，并在该模块中嵌入通道关注机制，增强不同芯片与故障之间的相关性，从而提高检测精度和鲁棒性。同时，在Informer编码器中引入了全卷积网络（FCN）和改进的蒸馏机制，增强了模型的局部特征提取能力，降低了计算成本。采用多尺度特征融合策略，提高了模型跨多尺度捕获特征的能力。为了验证该方法的有效性，我们设计并实现了一个实验硬件平台，从电路板组件中收集温度时间序列数据，用于故障检测。最后，一系列实验表明，该方法的准确率达到了0.990。

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引用次数: 0