Nano Communication Networks最新文献

MIMO systems in molecular communication are proposed and exhaustively investigated to increase the data rate. However, the misalignment problem between antennas decreases the performance of the system and has not been investigated adequately. This paper aims to correct the received signal in misaligned and distance-varying molecular 4x4 MIMO systems. By using multiple transmitter antennas and receivers, we can increase the data rate by utilizing higher-order modulation techniques that exploit spatial diversity. For the spatial modulation techniques, if there is a misalignment among the corresponding antennas, the signal quality degrades and decoding errors occur more frequently. Therefore, our main goal is to decode the received signal, while considering and compensating the misalignment of the system. To do so, we first estimate the misalignment along the rotation axis of our system and the distance between transmitter antennas and receivers. Then using these values, we process the received signal to eliminate the effects of misalignment. Additionally, we propose and investigate a method to detect active transmitter antennas that can be utilized for molecular index modulation under misalignment. We compare the performance of our proposed methods with the existing misalignment correction techniques.

The inputs use a non-blocking internal process to distribute the data using address of the port of the receiver using a non-blocking interior multistage transmission architecture known as a dual banyan network (DBN). The DBN is a primary component in many communication and switching applications because it efficiently routes and switches data packets. This study shows how to construct a single-layer DBN using QCA. A single layer 2 × 2 crossbar network (CBN) with two inputs and two outputs is suggested and developed in QCA to create the proposed communication architecture. In this study, a 2 × 2 CBN is used as a preliminary building block to create a 4 × 4 DBN. We present a detailed analysis of the DBN design, including its architecture, functionality, and performance evaluation. For a fault-free crossbar switch design, the consequence of a fault that affects the control line is noticed and surpassed. Similarly, the proposed architectures' fault tolerance has been described by considering fault scenarios at the 2 × 2 CBN control lines. Considering the logic gates, number of clock cycles, and device size complexity of the designs are measured. All of the designs were implemented using QCADesigner software. The power dissipation of the suggested layouts.

The Internet of nano-things communication has increased attention in recent years, serving different applications in many fields. Such applications need uplink and downlink communication between the nano-network and the macro-domain world through macro/nano-interfaces, where nano-sensors/actuators communicate with smart hybrid devices called micro/nano-gateways. The analytical evaluation of such gateways is mandatory, as it requires a precise study of their performance in handling traffic in the upstream/downstream directions. In this paper, an analytical evaluation of the micro/nano-gateway performance is studied using queueing theory to describe the behavior of the gateway handling the nano-network upstream traffic. The analytical investigation illustrates how different classes of upstream traffic will be processed by the gateway and distributed over three different queues according to traffic characteristics. The study shows the effect of the number of running servers inside each queue and the buffer size on the overall performance of the micro/nano-gateway.

Quantum Dot Cellular Automata (QCA) is a unique transistor less paradigm which effectively uses change in cell polarization to perform logical operations with high speed, low power and high intricacy. In recent years, the need of high performance memory cell is increased for improving the system performance. This paper presents the design of a QCA based memory cell with read write capabilities. In recent past, most of the QCA circuits are designed using the conventional three input majority voter. The conventional three input majority gate is not fault tolerant. Thus, we need an alternative design which can serve as the majority voter and also shows the fault tolerance. Moreover, the design of three input majority voter is not much addressed . In this paper, an alternative, simple structure of three input majority voter is presented which is better than the conventional one in terms of fault tolerance. In addition to this, the proposed three input majority voter is power aware and efficient to realize various digital circuits. The correctness of the proposed majority voter is validated through the physical proof. Moreover, the proposed gate is subjected to cell displacement defect to investigate the testability. The proposed gate is further used to implement rudimentary elements such as XOR gate, multiplexer and D latch. Finally, the design of Random Access Memory (RAM) cell with read, write, set and reset capabilities is proposed using the presented majority voter. The proposed circuits are further subjected to comprehensive analyses for estimation of cost functions and energy dissipation. The investigation of presented circuits manifests the use of proposed majority voter for next generation computing circuits.

In recent times, the Multiple-Input Multiple-Output (MIMO) system has played a vital role in wireless communication. MIMO antenna uses multiple antennas on both the sides of the transmitter and receiver. Mutual coupling occurs between two antenna elements to reduce the performance. The passage of current in the same direction on both neighbouring sides of the antennas increases the rate of mutual coupling. To decrease the mutual coupling, Split Ring Resonators (SRR) are located on the MIMO antenna. In this research paper, a MIMO antenna with SRR for Ultra Wide Band (UWB) applications with different frequency notches is proposed. Also, bandwidth and isolation are considered essential metrics for MIMO antennas. In the proposed 4 × 4 MIMO antenna design, SRR is located at the antenna's two sides, and the defected ground structure is on the bottom portion with a permittivity of 4.4 (FR4 substrate). The defected ground structure is proposed with stubs to enhance the characteristics of bandwidth and create notch bands in the frequency range of 3.1 GHz to 10.6 GHz. Placing SRRs adjacent to the feed line enhances the gain performance. The experimental results show that the ECC of the proposed antenna is less than 0.25, DG is higher than 9.8 dB, and the peak realized gain for 9.38 GHz is 11.3 dB, which is more reliable than other antenna designs. Therefore, experimental outcomes of the proposed antenna design enhance the applicability of band notching for wideband communication.

This paper presents a butler matrix-based microstrip hexagonal patch antenna with a direction of arrival (DOA) estimation approach for mm-wave application. The hexagonal-shaped patch antenna had been designed with a Z-shaped slot with an eight-port butler matrix. The DOA estimation is also done for the switched beam antenna using a novel direction of arrival (DOA) estimation algorithm known as Cramer-Rao lower bound (CRLB). The proposed design leads to significant size reduction and loss minimization. In addition to this, the design had the advantages of being low-cost, lightweight, and small-volume. The entire proposed design provides an operating frequency range of 28 GHz to 39 GHz with a center frequency of 33 GHz. The proposed work makes use of two butler matrices with two 45° phase shifters and 120° phase shifters. The effectiveness of the proposed algorithm and antenna design using the Butler matrix is evaluated for various performance metrics separately. The antenna is designed using Rogers RT/duroid 5880(tm) substrate, and the fabricated prototype is studied. The designed antenna attains high radiation efficiency, and it ranges between 97 and 98 % under both the measures and simulated scenarios under the operating frequency range of 28 GHz to 39 GHz.

In this research, a metamaterial polarization-rotator (MTMPR) wall is proposed for mutual coupling reduction in a $2\times 2$ multiple-input multiple-output (MIMO) antenna. A substrate integrated waveguide (SIW) based dielectric resonator antenna (DRA) is the preferred topology for the D-band frequency antenna design. The antenna elements are closely packed to achieve high antenna integration. The effect of the proposed isolation technique on the bandwidth performance and radiation characteristics of the antenna is investigated. Simulation results show that the proposed antenna exhibits a −10 dB impedance bandwidth of 19.5% (136.68 GHz–166.28 GHz), a gain of 11.06 dBi and a high efficiency of 84%. The antenna radiates in the broadside direction, with an isolation performance greater than 21.16 dB across the entire bandwidth of operation. Diversity metrics are also evaluated, indicating low correlation between the antenna elements and suitability of the proposed design for MIMO applications.

Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technology-based multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.

In a digital and automation era, on-chip multi-core architecture plays a vital role in effective communication in the field of very large-scale integrated circuits (VLSI). In this paper, we propose a unique mapping approach in which a probability-based core selection from the application benchmark into the center to eccentric way of placement of cores in the standard network architecture improves the performance of networks-on-chip (NoC). The proposed approach utilizes a structured mapping strategy, in contrast to the random mapping. This characteristic renders the proposed method a robust solution for a diverse range of NoC architectures irrespective of scale. The proposed approach provides better quality of service (QoS) with optimal total communication bandwidth and average hop count. The performance of the proposed mapping approach is validated with various experiments over standard and real-time benchmarks. The investigation results indicate that the total communication cost over real-time NoC benchmarks for the proposed mapping approach offers 43.06%, 22.75%, and 16.69% average improvement over CastNet, NMAP, and mapGtoM respectively. Furthermore, we adopt uniform geometric and shuffled traffic patterns to identify the latency and throughput of the proposed probability-based mapping approach. The investigation results indicate that the proposed mapping approach outperforms existing mapping procedures.

This manuscript presents a novel model for generating synthetic data for a biological molecular communication (MC) system to train a Neural Network (NN) for the purpose of discriminating transmitted bits. To achieve this, a deep learning algorithm was trained using the synthetic data and tested against experimentally measured data. The polynomial curve fitting coefficients are chosen as features. The featurization stage is followed by a NN that captures different aspects of the temporal correlation of the received signals. The real data was collected from an MC testbed that employed transfected Escherichia coli (E. coli) bacteria expressing the light-driven proton pump gloeorhodopsin from Gloeobacter violaceus. By stimulating the bacteria with externally controlled light, protons were secreted, which changed the pH level of the environment. A pH detector was then used to measure the pH of the environment. We propose the use of a deep convolutional neural network to detect the transmitted bits. This paper discusses the data augmentation, processing, and NNs that are pertinent to practical MC problems. The trained algorithm demonstrated an accuracy of over 99.9% in detecting transmitted bits from received signals at a bit rate of 1 bit/min, without requiring any specific knowledge of the underlying channel.