Integration-The Vlsi Journal最新文献

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Lossless grounded capacitance multipliers using two CFOAs and a grounded capacitor

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102375

Tolga Yucehan

Two new lossless grounded capacitance multipliers (GCMs) are proposed, in which a grounded capacitor and two current-feedback operational amplifiers (CFOAs) are used. Nevertheless, two floating resistors are used in the proposed GCMs. The proposed GCMs consist of three passive components. Thus, the proposed GCMs are obtained with a minimal quantity of passive components. The proposed GCMs have a high operating frequency range at a high multiplying factor. Identical passive component requirements are not needed in the proposed GCMs. In addition, the proposed GCMs can be controlled electronically by using the current-controlled current conveyor with a buffer instead of the second CFOA. However, there is no investigation on electronic tunability in this study. 0.18 μm CMOS technology parameters are employed for the CFOAs used in the proposed lossless GCMs. The layout area of the CFOA is 978.75 μm². All simulations are performed with the SPICE program. In all simulations, supply voltages of the CFOA are selected as ±1.25 V. The simulation results verified the theoretical results from about 30 Hz to 3 MHz. The simulation results show that temperature changes do not affect the proposed GCMs much. The proposed circuits consume 1.91 mW power. In addition, the GCMs in this paper are used in the first-order active low-pass filter, and experiments of these circuits are achieved with AD844s, which are commercial devices for the CFOAs. Also, the experimental results confirm the theoretical results from about 2.5 kHz to 1 MHz.

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引用次数: 0

CMOS multifunctional structure, with applications in analog signal processing

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102377

Cosmin Radu Popa

The paper will present an original multifunctional circuit that is able to implement (using the same functional core) a multitude of linear and nonlinear useful circuit functions: differential amplifiers and multiplier circuits with excellent linearity and extended range of the input amplitudes, squaring computational circuits, active resistors and function synthesizer structures with improved accuracy. The advantages of using this approach of designing analog signal processing structures are mainly related to the very important reducing of circuit complexity and accuracy for each developed circuit function. The circuits are designed for low-voltage low-power operations, being supplied at 0.7 V and consuming between 0.3uA and 0.9uA. They allow extremely large amplitude of the input signal (between −800mV and 800 mV), being able to obtain a very good accuracy of circuit functions implementations. The estimated theoretical results are confirmed by specific simulations, showing an excellent accuracy, correlated with a low-voltage low-power operation.

引用次数: 0

156 dB low-voltage low-power CMOS exponential function generator circuit

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102363

Cosmin Radu Popa

An original exponential function generator is presented, the original approach allowing to extremely accurate approximate the exponential function. The circuit output dynamic range is approximately 156 dB, for a maximal approximation error equal with 1 dB. The new proposed method uses a very precise superior-order approximation function, which is developed for requiring a very ressonable hardware resources for its implementation in CMOS technology. For further improving the accuracy of the proposed function generator circuit, an additional new method using a convenient variable changing is used. The proposed computational structure is designed for low-voltage low-power operation. The circuit is supplied at 1.1 V and its maximal power consumption is approximately 5 μW. The computational structure is developed for implementing in 0.18μ TSMC CMOS process, the approximately area being 1600 μm². The SPICE simulations of the exponential function generator operation confirm the theoretical estimated results.

引用次数: 0

Extrinsic calibration of complex machine vision system for mobile robot

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102370

Ruben Alaniz-Plata , Fernando Lopez-Medina , Oleg Sergiyenko , Wendy Flores-Fuentes , Julio C. Rodríguez-Quiñonez , Cesar Sepulveda-Valdez , José A. Núñez-López , David Meza-García , José Fabián Villa-Manríquez , Humberto Andrade-Collazo , Vera Tyrsa

Autonomous mobile robots are essential in industry, logistics, and service applications, such as infrastructure inspection, where navigation in dark and narrow environments is one of the most challenging tasks. This project presents the design and development of a patented artificial vision system for a mobile robot, which combines a high-precision laser scanner and a stereo-vision system. The objective is to enhance the robot’s surface scanning capabilities in complex environments. The proposed methodology allows to determine the relative position between systems to integrate data of the laser scanner with stereo-vision cameras and inertial sensors, providing robust and accurate environmental perception that enables the characterization of ventilation ducts surface. Experimental results show a mean correspondence error of

7.4515 mm

in absolute terms for the combined data.

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引用次数: 0

O.O: Optimized one-die placement for face-to-face bonded 3D ICs

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102371

Xingyu Tong , Yuhao Ren , Zhijie Cai , Peng Zou , Min Wei , Yuan Wen , Zhifeng Lin , Jianli Chen

As the miniaturization of integrated circuits (ICs) reaches its physical limits, the industry is entering a “more-than-Moore” era, demanding new Electronic Design Automation (EDA) tools. Existing TSV-based 3D placers focus on minimizing cuts while burgeoning F2F-bonded ICs feature dense interconnection between two planar die. Towards this novel structure, we proposed an integrated adaptation methodology upon mature one-die-based placement strategies. First, we instructively utilized a one-die placer to provide a statistical looking-ahead net diagnosis. The netlist henceforth shall be coarsened topologically and geometrically using a multi-level framework. Our multi-objective gain formulation guides a level-by-level refinement of the partition. This formulation considers factors like cut expectation, heterogeneous row heights, and balanced cell distribution, enabling efficient incremental calculations at each level. Given the partition, we synchronized the behavior of analytical planar placers by balancing the density and wirelength objective function among asymmetric layers. Finally, the result will be further improved by heuristic detail placement of bonding terminals and a post-place partition adjustment. Experimental results demonstrate that our fine-grained fusion of partitioning and placement techniques are competitive compared with the top three winners of the 2022 ICCAD CAD Contest, achieving the best normalized average wirelength with competitive runtime under various 3D architectural constraints.

随着集成电路（IC）的微型化达到物理极限，该行业正在进入一个 "超越摩尔 "的时代，需要新的电子设计自动化（EDA）工具。现有的基于 TSV 的 3D 贴片机侧重于最大限度地减少切割，而新兴的 F2F 粘合集成电路则以两个平面芯片之间的密集互连为特色。针对这种新型结构，我们在成熟的基于单裸片的贴片策略基础上提出了一种集成适应方法。首先，我们指导性地利用单晶片贴片机提供了一种统计前瞻性网络诊断。此后，我们将利用多层次框架对网表进行拓扑和几何粗化。我们的多目标增益公式指导着分区的逐级细化。该公式考虑了切割期望、异质行高和均衡单元分布等因素，从而实现了每一级的高效增量计算。在分区的基础上，我们通过平衡非对称层的密度和线长目标函数，同步了分析平面布局器的行为。最后，通过对接合端子的启发式细节放置和放置后的分区调整，进一步改进了结果。实验结果表明，与 2022 年 ICCAD CAD 竞赛的前三名获奖者相比，我们的细粒度分区与布局技术融合具有很强的竞争力，在各种三维架构约束条件下，我们实现了最佳归一化平均线长，运行时间也很有竞争力。

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引用次数: 0

Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-30 DOI: 10.1016/j.vlsi.2025.102372

C. Sánchez-López, R. Ochoa-Montiel, E. Reyes-Pérez, C. Muñiz-Montero

This article presents a comparison on the use of integer-order chaotic waveforms in collision-free robotic navigation methods. Each state-variable associated with the Lorenz’s, Rossler’s, Chen’s, Liu’s, Chua’s and Saturated Nonlinear Function Series system is used to compute the coverage, which represents the effectiveness over the amount of the total area covered by the mobile robot. As a result, it can be deduced which dynamic system and state-variable are most suitable to be used as randomness source within the robotic exploration methods. All positions of the mobile robot are generated by the state-variable of the chaotic dynamic system and the inverse Jacobian of the mobile robot is used as control law. The position error at each point of the chaotic path is iteratively reduced and the angular velocities for each motion are computed. Numerical simulations were performed in the Matlab environment and illustrate the usefulness of the best collisionless chaotic path generator with the largest coverage, which can be applied to various areas, such as household, agriculture, education, manufacturing, patrolling, medical care, military and so on.

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引用次数: 0

Simulation of fractional order chaotic oscillators applying the Grünwald–Letnikov definition and the Adams–Bashforth–Moulton method

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-27 DOI: 10.1016/j.vlsi.2025.102366

Alejandro Silva-Juarez , Sergio A. Rosales-Nunez , Luis C. Alvarez-Simon , Gregorio Zamora-Mejia , Victor H. Carbajal-Gomez , Alejandro I. Bautista-Castillo , Jose M. Rocha-Perez

This study presents the numerical simulation of chaotic behavior in autonomous nonlinear dynamic models with fractional-order derivatives, aiming to analyze the effectiveness of different numerical methods in obtaining chaotic attractors. Six fractional-order chaotic oscillators are examined, applying the Grünwald–Letnikov definition approximations and the Adams–Bashforth–Moulton method using a predictor–corrector scheme. Equilibrium points are analyzed, and eigenvalues are calculated to determine the minimum order of derivatives that guarantees chaotic behavior. The results show significant differences between the methods in terms of accuracy and efficiency, highlighting the importance of selecting the numerical method in the simulation of fractional systems.

引用次数: 0

A broadband low-noise VCO circuit based on a hybrid analog-digital control loop

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-27 DOI: 10.1016/j.vlsi.2025.102374

Lixia Zheng, Yuxiao Li, Zilu Zhao, Hehe Tian, Jin Wu, Weifeng Sun

To meet the need for high-performance, broadband PLL frequency synthesizers in modern RF transceivers, this paper designs a broadband, low-noise VCO circuit using 130 nm SiGe BiCMOS technology. The VCO system employs multi-core integration and switched-capacitor arrays, integrating seven narrowband VCOs for full wideband frequency coverage. To mitigate phase noise exacerbated by VCO output swing fluctuations with frequency and PVT, a digital-analog hybrid control loop is designed for dynamic swing calibration. A novel amplitude control module utilizes current mirroring to stabilize VCO cross-coupled transistors, replacing tail current sources, enhancing calibration accuracy and reducing phase noise. The VCO circuit was tested on a lock-in frequency synthesizer chip at room temperature, and the test results show that the tuning frequency range of the VCO system is 7.22–15.12 GHz, the absolute value of the voltage-controlled gain is less than 200 MHz/V, and the phase noise at the 14.5 GHz carrier with 1 MHz frequency deviation is −116.61 dBc/Hz.

引用次数: 0

High-speed serial interface equalization tuning using metaheuristics

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-25 DOI: 10.1016/j.vlsi.2025.102369

Adán Torralba-Ayance, Astrid Maritza González-Zapata, Alejandro Díaz-Sánchez

This work tests and confirms the capability of the Particle Swam Optimization (PSO) algorithm to find the equalization coefficients used in High-Speed Serial Interfaces (HSIO) to compensate the channel frequency dependent losses. To test the algorithm, a HSIO system with a Feed-Forward Equalizer (FFE), Continuous Time Linear Equalizer (CTLE) and Direct Feedback Equalizer (DFE) were modeled and tested for channels with different losses. Results indicate that the PSO algorithm successfully obtain the optimal equalization coefficients simultaneously.

引用次数: 0

Third-order resonance networks and their application to chaos generation

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-01-25 DOI: 10.1016/j.vlsi.2025.102348

Ahmed S. Elwakil , Brent J. Maundy , Costas Psychalinos , Amr Elsonbaty

In this work, we re-visit third-order RLC resonance networks depicting the set of four basic series and parallel resonance circuits where two circuits are admittance based (parallel resonance) and the other two are impedance-based (series resonance). We show that all circuits exhibit resonance at a single frequency and derive its expression. However, all circuits also have another below-resonance or above-resonance critical frequency at which the input impedance (or admittance) is zero. We call this frequency, the dip-frequency and a change in phase also occurs at this frequency. Therefore, the third-order resonance networks exhibit two phase changes: one at the resonance frequency and another at the dip frequency. An application in realizing third-order non-autonomous chaotic oscillators is described and experimental results are provided.

引用次数: 0

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