Integration-The Vlsi Journal最新文献_第2页

A method for mathematically synthesizing double-exponential signal generation on-the-fly on FPGA and its evaluation 一种基于FPGA的双指数信号生成数学合成方法及其评价

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-09 DOI: 10.1016/j.vlsi.2026.102661

Aydin Tarik Zengin

This paper introduces a high-precision, FPGA-based analog signal generator that fundamentally departs from conventional, template-based approaches by mathematically synthesizing each analog pulse in real time. Unlike systems relying on pre-recorded or pre-defined waveform memories, the proposed architecture dynamically computes every sample of double-exponential pulses on-the-fly within reconfigurable FPGA logic. Leveraging the AMD Xilinx ZYNQ 7010 SoC, the system ensures that every pulse is uniquely tailored on demand, with full control over rise time, decay time, amplitude, and pile-up effects. This real-time, parameter-driven signal generation enables the accurate emulation of complex detector signals, including overlapping events and user-defined spectral distributions, while guaranteeing deterministic timing and minimal processor overhead.

Experimental results demonstrate that the platform can precisely reproduce the analog characteristics and statistical features of diverse scintillation detector responses, outperforming commercial solutions limited to simple exponential or static waveform outputs. The modular, runtime-reconfigurable design supports dual-channel, high-fidelity operation and can be extended to broader application domains, including medical signal emulation and telecommunication waveform synthesis. By eliminating dependence on static pulse templates, this work establishes a new standard for flexibility, realism, and accuracy in embedded hardware testing and detector development.

本文介绍了一种高精度、基于fpga的模拟信号发生器，它通过实时数学合成每个模拟脉冲，从根本上改变了传统的基于模板的方法。与依赖于预记录或预定义波形存储器的系统不同，所提出的架构在可重构FPGA逻辑中动态计算双指数脉冲的每个样本。利用AMD Xilinx ZYNQ 7010 SoC，该系统确保每个脉冲都是根据需求量身定制的，完全控制上升时间，衰减时间，幅度和堆积效应。这种实时、参数驱动的信号生成能够精确模拟复杂的探测器信号，包括重叠事件和用户定义的光谱分布，同时保证确定性定时和最小的处理器开销。实验结果表明，该平台可以精确再现各种闪烁探测器响应的模拟特征和统计特征，优于仅限于简单指数或静态波形输出的商业解决方案。模块化、运行时可重构设计支持双通道、高保真操作，可扩展到更广泛的应用领域，包括医疗信号仿真和电信波形合成。通过消除对静态脉冲模板的依赖，这项工作为嵌入式硬件测试和检测器开发的灵活性、真实感和准确性建立了新的标准。

{"title":"A method for mathematically synthesizing double-exponential signal generation on-the-fly on FPGA and its evaluation","authors":"Aydin Tarik Zengin","doi":"10.1016/j.vlsi.2026.102661","DOIUrl":"10.1016/j.vlsi.2026.102661","url":null,"abstract":"<div><div>This paper introduces a high-precision, FPGA-based analog signal generator that fundamentally departs from conventional, template-based approaches by mathematically synthesizing each analog pulse in real time. Unlike systems relying on pre-recorded or pre-defined waveform memories, the proposed architecture dynamically computes every sample of double-exponential pulses on-the-fly within reconfigurable FPGA logic. Leveraging the AMD Xilinx ZYNQ 7010 SoC, the system ensures that every pulse is uniquely tailored on demand, with full control over rise time, decay time, amplitude, and pile-up effects. This real-time, parameter-driven signal generation enables the accurate emulation of complex detector signals, including overlapping events and user-defined spectral distributions, while guaranteeing deterministic timing and minimal processor overhead.</div><div>Experimental results demonstrate that the platform can precisely reproduce the analog characteristics and statistical features of diverse scintillation detector responses, outperforming commercial solutions limited to simple exponential or static waveform outputs. The modular, runtime-reconfigurable design supports dual-channel, high-fidelity operation and can be extended to broader application domains, including medical signal emulation and telecommunication waveform synthesis. By eliminating dependence on static pulse templates, this work establishes a new standard for flexibility, realism, and accuracy in embedded hardware testing and detector development.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102661"},"PeriodicalIF":2.5,"publicationDate":"2026-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FSMformer: An efficient direction-aware graph transformer for state register detection of gate-level netlist FSMformer：一种用于门级网表状态寄存器检测的高效方向感知图形变压器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-07 DOI: 10.1016/j.vlsi.2026.102656

Zongtai Li, Liang Yang, Hao Li, Mian Lou, Zeyu Yang, Weidong Xu

Although the use of third-party netlist IP can enhance the quality of integrated circuit products and reduce development cycles, it also introduces potential security vulnerabilities. Identifying state registers in sequential netlists is a commonly adopted technique to assist engineers in understanding the control logic of unknown gate-level netlists. Traditional graph theory-based detection methods, such as RELIC and FSMX-ultra, suffer from low accuracy and high computational complexity. Recent graph neural network-based detection methods, such as ReIGNN, also exhibit limited accuracy, with many data DFFs being misclassified as state DFFs. In this article, we propose a graph transformer-based method, FSMformer, which utilizes bidirectional message passing as the local module and direction-aware linear fast attention as the global module, to enable the simultaneous extraction of structural and functional features from sequential netlists, thereby achieving efficient and accurate detection of state DFFs in large-scale netlists. According to the experimental results, our proposed FSMformer outperforms not only the state-of-the-art graph theory-based method FSMX-ultra and the state-of-the-art GNN-based method ReIGNN, but also various advanced neural network baselines that we employed for state DFFs detection.

虽然使用第三方网表IP可以提高集成电路产品的质量，缩短开发周期，但也引入了潜在的安全漏洞。识别顺序网表中的状态寄存器是帮助工程师理解未知门级网表控制逻辑的一种常用技术。传统的基于图论的检测方法，如RELIC和FSMX-ultra，准确率低，计算量大。最近基于图神经网络的检测方法，如ReIGNN，也表现出有限的准确性，许多数据dff被错误地分类为状态dff。本文提出了一种基于图变换的FSMformer方法，该方法以双向消息传递为局部模块，以方向感知线性快速注意为全局模块，能够同时从序列网络列表中提取结构特征和功能特征，从而实现大规模网络列表中状态dff的高效、准确检测。根据实验结果，我们提出的FSMformer不仅优于最先进的基于图论的方法FSMX-ultra和最先进的基于gnn的方法ReIGNN，而且优于我们用于状态dff检测的各种先进的神经网络基线。

{"title":"FSMformer: An efficient direction-aware graph transformer for state register detection of gate-level netlist","authors":"Zongtai Li, Liang Yang, Hao Li, Mian Lou, Zeyu Yang, Weidong Xu","doi":"10.1016/j.vlsi.2026.102656","DOIUrl":"10.1016/j.vlsi.2026.102656","url":null,"abstract":"<div><div>Although the use of third-party netlist IP can enhance the quality of integrated circuit products and reduce development cycles, it also introduces potential security vulnerabilities. Identifying state registers in sequential netlists is a commonly adopted technique to assist engineers in understanding the control logic of unknown gate-level netlists. Traditional graph theory-based detection methods, such as RELIC and FSMX-ultra, suffer from low accuracy and high computational complexity. Recent graph neural network-based detection methods, such as ReIGNN, also exhibit limited accuracy, with many data DFFs being misclassified as state DFFs. In this article, we propose a graph transformer-based method, FSMformer, which utilizes bidirectional message passing as the local module and direction-aware linear fast attention as the global module, to enable the simultaneous extraction of structural and functional features from sequential netlists, thereby achieving efficient and accurate detection of state DFFs in large-scale netlists. According to the experimental results, our proposed FSMformer outperforms not only the state-of-the-art graph theory-based method FSMX-ultra and the state-of-the-art GNN-based method ReIGNN, but also various advanced neural network baselines that we employed for state DFFs detection.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102656"},"PeriodicalIF":2.5,"publicationDate":"2026-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A resource-constrained CNN accelerator for real-time license plate character recognition on FPGA platforms 基于FPGA平台的实时车牌字符识别CNN加速器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-06 DOI: 10.1016/j.vlsi.2026.102654

George B. Nardes, Thiago H. Rausch, Bruna H. Pereira, Douglas R. Melo, Cesar A. Zeferino

Convolutional Neural Networks (CNNs) are widely used in Automatic License Plate Recognition (ALPR) systems for Optical Character Recognition (OCR). Still, their computational cost often restricts deployment on edge devices. This work presents an 8-bit quantized CNN with a hardware-oriented dataflow designed specifically for OCR of Mercosur and Brazilian license plates. The model was trained using quantization-aware techniques and implemented on two FPGA platforms from different vendors, Altera Cyclone V and AMD Zynq UltraScale+, using the same VHDL architecture. The Zynq UltraScale+ implementation achieves 97.1% OCR accuracy, 2.12 ms latency, and 922 FPS in pipelined mode, while the Cyclone V version delivers 458 FPS with reduced BRAM and DSP usage. Energy measurements show 1.62 mJ per inference on Zynq UltraScale+ and 3.32 mJ on Cyclone V, confirming suitability for low-power, real-time ALPR. The results demonstrate that a portable 8-bit design can maintain accuracy comparable to that of floating-point models while achieving substantial gains in throughput and energy efficiency across heterogeneous FPGA devices.

卷积神经网络（cnn）广泛应用于车牌自动识别系统的光学字符识别（OCR）中。尽管如此，它们的计算成本往往限制了在边缘设备上的部署。这项工作提出了一个8位量化CNN，具有专门为南方共同市场和巴西车牌OCR设计的面向硬件的数据流。该模型使用量化感知技术进行训练，并在来自不同供应商的Altera Cyclone V和AMD Zynq UltraScale+两个FPGA平台上使用相同的VHDL架构实现。Zynq UltraScale+实现在流水线模式下实现97.1%的OCR精度，2.12 ms延迟和922 FPS，而Cyclone V版本提供458 FPS，减少BRAM和DSP使用。能量测量显示，Zynq UltraScale+上的每推断1.62 mJ， Cyclone V上的3.32 mJ，证实了低功耗、实时ALPR的适用性。结果表明，便携式8位设计可以保持与浮点模型相当的精度，同时在异构FPGA器件上实现吞吐量和能效的大幅提高。

{"title":"A resource-constrained CNN accelerator for real-time license plate character recognition on FPGA platforms","authors":"George B. Nardes, Thiago H. Rausch, Bruna H. Pereira, Douglas R. Melo, Cesar A. Zeferino","doi":"10.1016/j.vlsi.2026.102654","DOIUrl":"10.1016/j.vlsi.2026.102654","url":null,"abstract":"<div><div>Convolutional Neural Networks (CNNs) are widely used in Automatic License Plate Recognition (ALPR) systems for Optical Character Recognition (OCR). Still, their computational cost often restricts deployment on edge devices. This work presents an 8-bit quantized CNN with a hardware-oriented dataflow designed specifically for OCR of Mercosur and Brazilian license plates. The model was trained using quantization-aware techniques and implemented on two FPGA platforms from different vendors, Altera Cyclone V and AMD Zynq UltraScale+, using the same VHDL architecture. The Zynq UltraScale+ implementation achieves 97.1% OCR accuracy, 2.12 ms latency, and 922 FPS in pipelined mode, while the Cyclone V version delivers 458 FPS with reduced BRAM and DSP usage. Energy measurements show 1.62 mJ per inference on Zynq UltraScale+ and 3.32 mJ on Cyclone V, confirming suitability for low-power, real-time ALPR. The results demonstrate that a portable 8-bit design can maintain accuracy comparable to that of floating-point models while achieving substantial gains in throughput and energy efficiency across heterogeneous FPGA devices.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102654"},"PeriodicalIF":2.5,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Non-equilibrium oscillator with a diode: Dynamics and application 带二极管的非平衡振荡器：动力学与应用

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-06 DOI: 10.1016/j.vlsi.2026.102653

Viet-Thanh Pham , Victor Kamdoum Tamba , Luigi Fortuna

Non-equilibrium oscillators are special because of their hidden attractors. This work introduces a non-equilibrium oscillator, which is implemented using a reduced number of resistors. Its implementation requires a diode instead of analog multipliers. Our oscillator is easily realized with common off-the-shelf components in the laboratory, making it suitable for educational purposes. Dynamics of the oscillator are investigated to present its special features. In addition, the usage of the oscillator for generating random signal is presented illustrating its possible application.

非平衡振子的特殊之处在于它们的隐吸引子。这项工作介绍了一种非平衡振荡器，它是通过减少电阻数量来实现的。它的实现需要二极管而不是模拟乘法器。我们的振荡器很容易实现与常见的现成组件在实验室，使其适合教育目的。研究了该振荡器的动力学特性，揭示了它的特点。此外，还介绍了该振荡器产生随机信号的方法，并举例说明了其可能的应用。

引用次数: 0

Hybrid algorithm based optimization strategies for analog circuit sizing in low dropout regulators 基于混合算法的低差稳压器模拟电路尺寸优化策略

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-05 DOI: 10.1016/j.vlsi.2026.102646

S. Karipidis , A. Buzo , G. Pelz , T. Noulis

Analog and Mixed Signal circuit sizing with large-scale parameters requires a lot of simulations, especially in non-linear topology where large-signal analysis is a need. Reducing the number of simulations and in general the total design cycle time, is the main objective for optimal sizing of complicated circuits. In this work a circuit sizing automated design methodology is presented using the hybrid dual annealing and Nelder–Mead algorithm, significantly reducing the design cycle time and the required number of transient simulations. A customized hybrid algorithm environment using Dual Annealing and Nelder–Mead is developed where the optimization process is divided into different optimization sub-steps. The proposed hybrid algorithm based method achieves rapid convergence to the needed circuit performance specification. It uses combinations of direct search algorithms to separate metric evaluation accelerating the performance specifications convergence speed in a large parameter space. A complicated non-linear topology like a product level low-dropout (LDO) regulator, in 180 nm process node, with 30 parameters is used as the circuit vehicle to verify the proposed methodology. The sizing process converged with less than 1700 simulations having as input just the circuit schematic with no prior sizing knowledge. Sub optimization is also performed focused on each analysis type — DC, AC and transient, with a focus on reducing the number of transient simulations. The proposed combined algorithm method achieved 31 % faster convergence speed compared to the state-of-the-art methods and handles efficiently each simulation analysis.

具有大参数的模拟和混合信号电路需要大量的仿真，特别是在非线性拓扑中需要进行大信号分析。减少模拟次数和总体设计周期时间，是优化复杂电路尺寸的主要目标。在这项工作中，提出了一种使用混合双退火和Nelder-Mead算法的电路尺寸自动设计方法，显着减少了设计周期时间和所需的瞬态模拟次数。开发了一种基于双退火和Nelder-Mead的自定义混合算法环境，将优化过程划分为不同的优化子步骤。基于混合算法的方法能够快速收敛到所需的电路性能指标。它采用直接搜索算法的组合来分离度量评估，加快了性能指标在大参数空间中的收敛速度。采用复杂的非线性拓扑，如产品级低差（LDO）稳压器，在180 nm工艺节点上，30个参数作为电路载体来验证所提出的方法。尺寸过程融合了不到1700个模拟，只有电路原理图作为输入，没有事先的尺寸知识。还针对每种分析类型（直流、交流和瞬态）进行了子优化，重点是减少瞬态模拟的次数。该组合算法的收敛速度比现有方法快31%，并能有效地处理各种仿真分析。

{"title":"Hybrid algorithm based optimization strategies for analog circuit sizing in low dropout regulators","authors":"S. Karipidis , A. Buzo , G. Pelz , T. Noulis","doi":"10.1016/j.vlsi.2026.102646","DOIUrl":"10.1016/j.vlsi.2026.102646","url":null,"abstract":"<div><div>Analog and Mixed Signal circuit sizing with large-scale parameters requires a lot of simulations, especially in non-linear topology where large-signal analysis is a need. Reducing the number of simulations and in general the total design cycle time, is the main objective for optimal sizing of complicated circuits. In this work a circuit sizing automated design methodology is presented using the hybrid dual annealing and Nelder–Mead algorithm, significantly reducing the design cycle time and the required number of transient simulations. A customized hybrid algorithm environment using Dual Annealing and Nelder–Mead is developed where the optimization process is divided into different optimization sub-steps. The proposed hybrid algorithm based method achieves rapid convergence to the needed circuit performance specification. It uses combinations of direct search algorithms to separate metric evaluation accelerating the performance specifications convergence speed in a large parameter space. A complicated non-linear topology like a product level low-dropout (LDO) regulator, in 180 nm process node, with 30 parameters is used as the circuit vehicle to verify the proposed methodology. The sizing process converged with less than 1700 simulations having as input just the circuit schematic with no prior sizing knowledge. Sub optimization is also performed focused on each analysis type — DC, AC and transient, with a focus on reducing the number of transient simulations. The proposed combined algorithm method achieved 31 % faster convergence speed compared to the state-of-the-art methods and handles efficiently each simulation analysis.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102646"},"PeriodicalIF":2.5,"publicationDate":"2026-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-performance FIR filter designs using Brent Kung Adder and pipelined Vedic multiplier 高性能FIR滤波器设计使用布伦特孔加法器和流水线吠陀乘法器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-03 DOI: 10.1016/j.vlsi.2025.102645

J. Banumathi, G. Karthy

Signal processing widely uses Finite Impulse Response (FIR) filters because of their stability and linear phase. However, traditional FIR filter designs are limited by multiplication operations that lead to high hardware utilization and delay. To address this, modified FIR filters with optimized multipliers and adders are being developed to improve hardware resource utilization and delay performance. This paper presents novel designs for 8-tap and 16-tap FIR filters, leveraging Brent-Kung Adders (BKA) and Pipelined (P) Urdhva Triyakbhyam Vedic multipliers (UTVM) to achieve minimal delay and enhanced performance. Three architectures—Pipelined FIR using UTVM with BKA (PFIR-UTVM-BKA), FIR using PUTVM with BKA (FIR-PUTVM-BKA), and Pipelined FIR using PUTVM with BKA (PFIR-PUTVM-BKA)—were implemented with different device specifications on Kintex-7, Virtex-7, and Zynq 7000 platforms using Xilinx Vivado 2022.2 and ASIC 45 nm, simulated in Verilog. In FPGA, the proposed multiplier reduces delay by 43 %, 61.55 %, 73.01 %, and 78.51 % across different bit widths, and power, delay, and (power delay Product) PDP were reduced by 82.16 %,94.34 % and 98.99 % respectively, in ASIC. Additionally, the proposed FIR filter architectures achieve significant improvements, including 51.88 % and 27.13 % delay reduction, 75.40 % slice improvement, and 92.53 % and 97.03 % enhancement in slice registers for 8-tap and 16-tap 8-bit designs in FPGA, and power, delay, and PDP (Power Delay Product) were reduced by 87.97 %,97.59 % and 99.71 % respectively, in ASIC. These advancements make the proposed FIR filters highly suitable for high-speed digital signal processing (DSP) applications, where efficient processing and minimized latency are crucial. Integrating PVM and BKA plays a pivotal role in achieving these performance enhancements, positioning these filter designs as promising solutions for next-generation signal processing systems.

有限脉冲响应（FIR）滤波器由于其稳定性和相位线性而被广泛应用于信号处理。然而，传统的FIR滤波器设计受到乘法运算的限制，导致高硬件利用率和延迟。为了解决这个问题，正在开发带有优化乘法器和加法器的改进FIR滤波器，以提高硬件资源利用率和延迟性能。本文提出了8分频和16分频FIR滤波器的新设计，利用Brent-Kung加法器（BKA）和Pipelined (P) Urdhva Triyakbhyam Vedic乘法器（UTVM）实现最小的延迟和增强的性能。采用Xilinx Vivado 2022.2和45纳米ASIC，在Kintex-7、Virtex-7和Zynq 7000平台上以不同的设备规格实现了三种架构——使用UTVM和BKA的流水线FIR （PFIR-UTVM-BKA）、使用PUTVM和BKA的流水线FIR （FIR-PUTVM-BKA）和使用PUTVM和BKA的流水线FIR (pir -PUTVM-BKA)，并在Verilog中进行了模拟。在FPGA中，该乘法器在不同比特宽度下的时延分别降低了43%、61.55%、73.01%和78.51%，在ASIC中，功率、时延和（功率延迟积）PDP分别降低了82.16%、94.34%和98.99%。此外，所提出的FIR滤波器架构取得了显著的改进，包括FPGA中8分路和16分路8位设计的延迟降低51.88%和27.13%，切片改善75.40%，切片寄存器提高92.53%和97.03%，ASIC中的功耗，延迟和PDP（功率延迟产品）分别降低87.97%，97.59%和99.71%。这些进步使得所提出的FIR滤波器非常适合高速数字信号处理（DSP）应用，其中高效处理和最小化延迟至关重要。集成PVM和BKA在实现这些性能增强方面起着关键作用，将这些滤波器设计定位为下一代信号处理系统的有前途的解决方案。

{"title":"High-performance FIR filter designs using Brent Kung Adder and pipelined Vedic multiplier","authors":"J. Banumathi, G. Karthy","doi":"10.1016/j.vlsi.2025.102645","DOIUrl":"10.1016/j.vlsi.2025.102645","url":null,"abstract":"<div><div>Signal processing widely uses Finite Impulse Response (FIR) filters because of their stability and linear phase. However, traditional FIR filter designs are limited by multiplication operations that lead to high hardware utilization and delay. To address this, modified FIR filters with optimized multipliers and adders are being developed to improve hardware resource utilization and delay performance. This paper presents novel designs for 8-tap and 16-tap FIR filters, leveraging Brent-Kung Adders (BKA) and Pipelined (P) Urdhva Triyakbhyam Vedic multipliers (UTVM) to achieve minimal delay and enhanced performance. Three architectures—Pipelined FIR using UTVM with BKA (PFIR-UTVM-BKA), FIR using PUTVM with BKA (FIR-PUTVM-BKA), and Pipelined FIR using PUTVM with BKA (PFIR-PUTVM-BKA)—were implemented with different device specifications on Kintex-7, Virtex-7, and Zynq 7000 platforms using Xilinx Vivado 2022.2 and ASIC 45 nm, simulated in Verilog. In FPGA, the proposed multiplier reduces delay by 43 %, 61.55 %, 73.01 %, and 78.51 % across different bit widths, and power, delay, and (power delay Product) PDP were reduced by 82.16 %,94.34 % and 98.99 % respectively, in ASIC. Additionally, the proposed FIR filter architectures achieve significant improvements, including 51.88 % and 27.13 % delay reduction, 75.40 % slice improvement, and 92.53 % and 97.03 % enhancement in slice registers for 8-tap and 16-tap 8-bit designs in FPGA, and power, delay, and PDP (Power Delay Product) were reduced by 87.97 %,97.59 % and 99.71 % respectively, in ASIC. These advancements make the proposed FIR filters highly suitable for high-speed digital signal processing (DSP) applications, where efficient processing and minimized latency are crucial. Integrating PVM and BKA plays a pivotal role in achieving these performance enhancements, positioning these filter designs as promising solutions for next-generation signal processing systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102645"},"PeriodicalIF":2.5,"publicationDate":"2026-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RO-like ring-based TRNG with adaptive mode switching for enhanced entropy Harvesting 基于自适应模式切换的类ro环TRNG增强熵收集

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-03 DOI: 10.1016/j.vlsi.2025.102640

Jinlin Chen , Huaguo Liang , Yingchun Lu , Liang Yao

With the rise of the internet and electronic devices, the security of network information has garnered increasing attention. True Random Number Generators (TRNGs) play an increasingly important role in information security. TRNG entropy sources based on Ring Oscillator (RO) have attracted significant interest due to their simple circuit design and ease of implementation on FPGAs. However, most existing works suffer from high hardware overhead. A novel ultra-lightweight TRNG based on multi-mode switching of RO-like rings is proposed in this work, which can be automatically placed and routed on the Xilinx Artix-7 FPGA, using only 10 LUTs and 2 D flip-flops. The randomness of the entropy source is analyzed through a mathematical model, proving that the output sequence is an unordered random bit string under any circumstances. The output sequence of the TRNG successfully passed various tests, including autocorrelation tests, NIST SP800-22, NIST SP800-90B, AIS-31, and TESTU01, with favorable results.

随着互联网和电子设备的兴起，网络信息的安全性越来越受到人们的关注。真随机数发生器（trng）在信息安全中发挥着越来越重要的作用。基于环形振荡器（RO）的TRNG熵源由于其简单的电路设计和易于在fpga上实现而引起了人们的极大兴趣。然而，大多数现有的工作都受到高硬件开销的困扰。本文提出了一种基于类o环多模交换的新型超轻TRNG，该TRNG仅使用10个lut和2d触发器就可以在Xilinx Artix-7 FPGA上自动放置和路由。通过数学模型分析了熵源的随机性，证明了在任何情况下输出序列都是一个无序的随机位串。TRNG的输出序列成功通过了自相关测试、NIST SP800-22、NIST SP800-90B、AIS-31、TESTU01等测试，取得了良好的效果。

引用次数: 0

A heuristic approach for near Pareto-optimal design space exploration in Approximate High-Level Synthesis 近似高级综合中近似帕累托最优设计空间探索的启发式方法

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-02 DOI: 10.1016/j.vlsi.2025.102638

Tiago Almeida , Isaías Felzmann , Lucas Wanner

Approximate Computing can optimize resource usage in HLS (High-Level Synthesis) by mapping certain operations to components that have lower resource utilization but introduce small errors into application outputs. A fundamental challenge is identifying a set of approximate components for implementing operators in an accelerator design while achieving optimal resource utilization and accuracy. We introduce an input-aware heuristic approach that uses application inputs to model output errors more effectively. In this approach, operators in accelerators, such as adders and multipliers, are mapped to a library of precharacterized approximate components. Applications are executed with a set of training inputs and candidate solutions are selected based on a metric that combines output errors and estimated resource utilization. The results demonstrate that the approach can find appropriate approximate designs for a given error threshold. For image processing applications, the input-aware heuristic was able to save LUT and FF by up to 55% for less than 25% output degradation. Similar savings were shown for a CNN model with less than 0.8% accuracy degradation.

通过将某些操作映射到资源利用率较低但在应用程序输出中引入小错误的组件，Approximate Computing可以优化HLS（高级综合）中的资源使用情况。一个基本的挑战是在实现最佳资源利用率和精度的同时，确定一组近似组件，以实现加速器设计中的操作。我们引入了一种输入感知启发式方法，该方法使用应用程序输入更有效地建模输出错误。在这种方法中，加速器中的运算符，如加法器和乘法器，被映射到预表征的近似组件库。应用程序使用一组训练输入来执行，候选解决方案是根据结合输出误差和估计资源利用率的度量来选择的。结果表明，该方法可以在给定误差阈值的情况下找到合适的近似设计。对于图像处理应用程序，输入感知启发式能够将LUT和FF节省高达55%，而输出退化低于25%。对于准确度下降小于0.8%的CNN模型，也显示了类似的节省。

{"title":"A heuristic approach for near Pareto-optimal design space exploration in Approximate High-Level Synthesis","authors":"Tiago Almeida , Isaías Felzmann , Lucas Wanner","doi":"10.1016/j.vlsi.2025.102638","DOIUrl":"10.1016/j.vlsi.2025.102638","url":null,"abstract":"<div><div>Approximate Computing can optimize resource usage in HLS (High-Level Synthesis) by mapping certain operations to components that have lower resource utilization but introduce small errors into application outputs. A fundamental challenge is identifying a set of approximate components for implementing operators in an accelerator design while achieving optimal resource utilization and accuracy. We introduce an input-aware heuristic approach that uses application inputs to model output errors more effectively. In this approach, operators in accelerators, such as adders and multipliers, are mapped to a library of precharacterized approximate components. Applications are executed with a set of training inputs and candidate solutions are selected based on a metric that combines output errors and estimated resource utilization. The results demonstrate that the approach can find appropriate approximate designs for a given error threshold. For image processing applications, the input-aware heuristic was able to save LUT and FF by up to 55% for less than 25% output degradation. Similar savings were shown for a CNN model with less than 0.8% accuracy degradation.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102638"},"PeriodicalIF":2.5,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145895858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-temperature-drift voltage reference design using magnetic tunnel junctions 采用磁隧道结的低温漂移电压参考设计

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-02 DOI: 10.1016/j.vlsi.2025.102644

Yongliang Zhou , Yingxue Sun , Beibei Zhang , Wangyong Si , Jingxue Zhong , Weizhe Tan , Chunyu Peng , Xiulong Wu

This article primarily investigates the temperature characteristics of magnetic tunnel junctions (MTJ) and exploits their tunnel magneto-resistance (TMR) effect to compensate for temperature-induced mismatches arising from CMOS temperature variations. In this work, the beta-multiplier reference and Kuijk bandgap reference are simulated on the 28 nm node. The proposed designs achieve improvements in temperature stability while maintaining low-voltage operation. Specifically, the circuit was redesigned based on a beta-multiplier voltage-reference topology in which MTJs replace resistors, with the explicit aim of strengthening the negative-feedback loop. As a result, stable operation is achieved at a minimum supply voltage of 0.6 V over the temperature range 0 °C to 110 °C. The reference voltage exhibits a line sensitivity of 0.57%/V, a temperature coefficient of 35.2 ppm/°C, and a nominal output of 441.6 mV. Drawing on MTJ-based compensation techniques, the modified Kuijk bandgap reference replaces the BJT-based temperature-compensation element with an MTJ device, yielding a reference voltage with a line sensitivity of 0.096%/V, a temperature coefficient of 11.8 ppm/°C, and a nominal output of 1.65 V. Beyond the electrical benefits, the use of MTJs enables vertical integration of the compensating elements, delivering substantial area savings — approximately 50% reduction for the beta-multiplier implementation and about 66.5% for the modified bandgap — thereby producing a more compact and competitive solution for high-performance precision voltage references.

本文主要研究了磁隧道结（MTJ）的温度特性，并利用其隧道磁电阻（TMR）效应来补偿CMOS温度变化引起的温度诱导错配。在这项工作中，在28 nm节点上模拟了β乘法器参考和Kuijk带隙参考。所提出的设计在保持低压运行的同时提高了温度稳定性。具体来说，电路是基于β乘法器电压参考拓扑重新设计的，其中mtj取代电阻，明确的目的是加强负反馈回路。因此，在0°C至110°C的温度范围内，在0.6 V的最小电源电压下实现稳定运行。基准电压的线灵敏度为0.57%/V，温度系数为35.2 ppm/°C，标称输出为441.6 mV。利用基于MTJ的补偿技术，改进的Kuijk带隙基准用MTJ器件取代了基于bjt的温度补偿元件，产生的参考电压线灵敏度为0.096%/V，温度系数为11.8 ppm/°C，标称输出为1.65 V。除了电气方面的优势之外，MTJs的使用还可以实现补偿元件的垂直集成，从而节省大量面积——β乘法器的实现减少了约50%，改进带隙减少了约66.5%——从而为高性能精密电压参考提供了更紧凑、更有竞争力的解决方案。

{"title":"Low-temperature-drift voltage reference design using magnetic tunnel junctions","authors":"Yongliang Zhou , Yingxue Sun , Beibei Zhang , Wangyong Si , Jingxue Zhong , Weizhe Tan , Chunyu Peng , Xiulong Wu","doi":"10.1016/j.vlsi.2025.102644","DOIUrl":"10.1016/j.vlsi.2025.102644","url":null,"abstract":"<div><div>This article primarily investigates the temperature characteristics of magnetic tunnel junctions (MTJ) and exploits their tunnel magneto-resistance (TMR) effect to compensate for temperature-induced mismatches arising from CMOS temperature variations. In this work, the beta-multiplier reference and Kuijk bandgap reference are simulated on the 28 nm node. The proposed designs achieve improvements in temperature stability while maintaining low-voltage operation. Specifically, the circuit was redesigned based on a beta-multiplier voltage-reference topology in which MTJs replace resistors, with the explicit aim of strengthening the negative-feedback loop. As a result, stable operation is achieved at a minimum supply voltage of 0.6 V over the temperature range 0 °C to 110 °C. The reference voltage exhibits a line sensitivity of 0.57%/V, a temperature coefficient of 35.2 ppm/°C, and a nominal output of 441.6 mV. Drawing on MTJ-based compensation techniques, the modified Kuijk bandgap reference replaces the BJT-based temperature-compensation element with an MTJ device, yielding a reference voltage with a line sensitivity of 0.096%/V, a temperature coefficient of 11.8 ppm/°C, and a nominal output of 1.65 V. Beyond the electrical benefits, the use of MTJs enables vertical integration of the compensating elements, delivering substantial area savings — approximately 50% reduction for the beta-multiplier implementation and about 66.5% for the modified bandgap — thereby producing a more compact and competitive solution for high-performance precision voltage references.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102644"},"PeriodicalIF":2.5,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Genetic algorithm-optimized fuzzy controller for the calibration of pipelined ADCs 基于遗传算法优化的模糊控制器对流水线adc的标定

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-12-29 DOI: 10.1016/j.vlsi.2025.102643

Luotian Wu, Honghui Deng, Jiashen Li, Muqi Li, Long Li, Yongsheng Yin

This paper proposes a genetic algorithm-optimized fuzzy controller for calibrating nonlinear errors in pipelined ADCs. Given the correspondence between the sub-ADC quantization codes and the errors in pipelined ADCs, this study employs a single-input single-output fuzzy controller to establish the mapping between the sub-ADC quantization codes and the errors. To fully utilize the fitting capabilities of the fuzzy controller, genetic algorithms are used to determine the optimal design parameters of the fuzzy controller. The developed single-input single-output fuzzy controller can fully achieve the fitting of nonlinear errors while maintaining a simple structure and low hardware implementation complexity. The optimal fuzzy controller is implemented on a Xilinx Kintex-7 FPGA and applied to calibrate a 14-bit 61 MS/s pipelined ADC. Experimental results demonstrate that after calibration with the optimized fuzzy controller, SNDR and SFDR are improved by 29.6 dB and 44.7 dB, respectively.

本文提出了一种遗传算法优化的模糊控制器，用于校正流水线adc中的非线性误差。考虑到流水线adc中子adc量化码与误差之间的对应关系，本研究采用单输入单输出模糊控制器建立子adc量化码与误差之间的映射关系。为了充分发挥模糊控制器的拟合能力，采用遗传算法确定模糊控制器的最优设计参数。所开发的单输入单输出模糊控制器在保持结构简单、硬件实现复杂度低的同时，能充分实现非线性误差的拟合。在Xilinx Kintex-7 FPGA上实现了最优模糊控制器，并应用于校准14位61 MS/s的流水线ADC。实验结果表明，经优化后的模糊控制器标定后，SNDR和SFDR分别提高了29.6 dB和44.7 dB。

引用次数: 0