Pub Date : 2026-05-01Epub Date: 2026-01-29DOI: 10.1016/j.vlsi.2026.102668
Ahmed S. Elwakil , Abdulrahman A. Nutfaji , Brent J. Maundy
In this work, we introduce the set of four true canonical third-order oscillators based on third-order resonance networks with two capacitors and one inductor (2C-1L). Although a number of third-order LC oscillators are readily known, including some versions of the Colpitts oscillator, the unique set of four possible oscillators that are based on true canonical third-order resonance networks have never been explicitly introduced in the literature. This is because unlike second-order resonance networks, third-order ones are not in wide use and are hardly studied in basic circuit theory textbooks. We first recall the four elementary third-order canonical resonance networks and then focus on the two networks having a single inductor. Using these two networks, the set of four possible oscillators are derived and experimentally verified. An application in chaos generation is also presented and verified experimentally and via numerical simulations.
{"title":"True canonical third-order resonance-based oscillators and application to chaos generation","authors":"Ahmed S. Elwakil , Abdulrahman A. Nutfaji , Brent J. Maundy","doi":"10.1016/j.vlsi.2026.102668","DOIUrl":"10.1016/j.vlsi.2026.102668","url":null,"abstract":"<div><div>In this work, we introduce the set of four true canonical third-order oscillators based on third-order resonance networks with two capacitors and one inductor (2C-1L). Although a number of third-order LC oscillators are readily known, including some versions of the Colpitts oscillator, the unique set of four possible oscillators that are based on true canonical third-order resonance networks have never been explicitly introduced in the literature. This is because unlike second-order resonance networks, third-order ones are not in wide use and are hardly studied in basic circuit theory textbooks. We first recall the four elementary third-order canonical resonance networks and then focus on the two networks having a single inductor. Using these two networks, the set of four possible oscillators are derived and experimentally verified. An application in chaos generation is also presented and verified experimentally and via numerical simulations.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102668"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new design of a load-modulated balance doherty power amplifier (LM-BDPA) using a parallel coupled line (PCL) structure line coupler for 5G internet of things (IoT) applications. The proposed design aims to achieve high efficiency and wide bandwidth, which are critical for 5G communication systems. The LM-BDPA utilizes a PCL structure to enhance the load modulation capability, resulting in improved power-added efficiency (PAE) and linearity. The design also incorporates advanced thermal management techniques to ensure stable operation under high-power conditions. The performance of the proposed LM-BDPA is evaluated through both simulations and measurements. The fabricated prototype achieves a measured gain of 11.2–13.4 dB and a saturated output power of ∼41 dBm. A PAE of 46.4–56.5 % and 43.2–50.3 % is achieved at 6 dB and 8 dB output power back-off, respectively, across the designed frequency band.
{"title":"Design of a load modulated balance doherty power amplifier using parallel coupled line (PCL) structure line coupler for 5G IoT applications","authors":"Rajesh Kumar , Sachin Kumar , Binod Kumar Kanaujia","doi":"10.1016/j.vlsi.2026.102659","DOIUrl":"10.1016/j.vlsi.2026.102659","url":null,"abstract":"<div><div>This paper presents a new design of a load-modulated balance doherty power amplifier (LM-BDPA) using a parallel coupled line (PCL) structure line coupler for 5G internet of things (IoT) applications. The proposed design aims to achieve high efficiency and wide bandwidth, which are critical for 5G communication systems. The LM-BDPA utilizes a PCL structure to enhance the load modulation capability, resulting in improved power-added efficiency (PAE) and linearity. The design also incorporates advanced thermal management techniques to ensure stable operation under high-power conditions. The performance of the proposed LM-BDPA is evaluated through both simulations and measurements. The fabricated prototype achieves a measured gain of 11.2–13.4 dB and a saturated output power of ∼41 dBm. A PAE of 46.4–56.5 % and 43.2–50.3 % is achieved at 6 dB and 8 dB output power back-off, respectively, across the designed frequency band.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102659"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-11DOI: 10.1016/j.vlsi.2026.102655
Yingchun Lu , Hongliang Lu , Yujie Liu , Huaguo Liang , Zhengfeng Huang , Jinlin Chen , Xiumin Xu , Liang Yao
Strong Physical Unclonable Functions (PUFs) are vulnerable to modeling attacks using Machine Learning (ML), and PUF-based authentication protocols also face security risks. To address these issues, this paper proposes a PUF structure with resistance to modeling attacks based on Dynamic Obfuscation (DO), composed of Linear Feedback Shift Registers (LFSRs), PUFs, and several logic gates. The characteristics of DO are as follows: (1) the initial state of the LFSR is determined by the PUF's response, making it uncontrollable; (2) the updated state of the LFSR determines the obfuscated bit of each input challenge, achieving a dynamic mapping between challenges and responses. An Arbiter PUF (APUF) based on DO is implemented on Xilinx Artix-7 FPGA, and experimental results show that the structure can effectively resist modeling attacks from various ML algorithms, with prediction accuracy close to 50 %. In addition, this paper proposes a mutual authentication protocol based on PUF, suitable for Internet of Things (IoT) systems.
{"title":"Design of a dynamic obfuscation-based strong PUF resistant to modeling attacks and mutual authentication protocol","authors":"Yingchun Lu , Hongliang Lu , Yujie Liu , Huaguo Liang , Zhengfeng Huang , Jinlin Chen , Xiumin Xu , Liang Yao","doi":"10.1016/j.vlsi.2026.102655","DOIUrl":"10.1016/j.vlsi.2026.102655","url":null,"abstract":"<div><div>Strong Physical Unclonable Functions (PUFs) are vulnerable to modeling attacks using Machine Learning (ML), and PUF-based authentication protocols also face security risks. To address these issues, this paper proposes a PUF structure with resistance to modeling attacks based on Dynamic Obfuscation (DO), composed of Linear Feedback Shift Registers (LFSRs), PUFs, and several logic gates. The characteristics of DO are as follows: (1) the initial state of the LFSR is determined by the PUF's response, making it uncontrollable; (2) the updated state of the LFSR determines the obfuscated bit of each input challenge, achieving a dynamic mapping between challenges and responses. An Arbiter PUF (APUF) based on DO is implemented on Xilinx Artix-7 FPGA, and experimental results show that the structure can effectively resist modeling attacks from various ML algorithms, with prediction accuracy close to 50 %. In addition, this paper proposes a mutual authentication protocol based on PUF, suitable for Internet of Things (IoT) systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102655"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-05DOI: 10.1016/j.vlsi.2026.102646
S. Karipidis , A. Buzo , G. Pelz , T. Noulis
Analog and Mixed Signal circuit sizing with large-scale parameters requires a lot of simulations, especially in non-linear topology where large-signal analysis is a need. Reducing the number of simulations and in general the total design cycle time, is the main objective for optimal sizing of complicated circuits. In this work a circuit sizing automated design methodology is presented using the hybrid dual annealing and Nelder–Mead algorithm, significantly reducing the design cycle time and the required number of transient simulations. A customized hybrid algorithm environment using Dual Annealing and Nelder–Mead is developed where the optimization process is divided into different optimization sub-steps. The proposed hybrid algorithm based method achieves rapid convergence to the needed circuit performance specification. It uses combinations of direct search algorithms to separate metric evaluation accelerating the performance specifications convergence speed in a large parameter space. A complicated non-linear topology like a product level low-dropout (LDO) regulator, in 180 nm process node, with 30 parameters is used as the circuit vehicle to verify the proposed methodology. The sizing process converged with less than 1700 simulations having as input just the circuit schematic with no prior sizing knowledge. Sub optimization is also performed focused on each analysis type — DC, AC and transient, with a focus on reducing the number of transient simulations. The proposed combined algorithm method achieved 31 % faster convergence speed compared to the state-of-the-art methods and handles efficiently each simulation analysis.
{"title":"Hybrid algorithm based optimization strategies for analog circuit sizing in low dropout regulators","authors":"S. Karipidis , A. Buzo , G. Pelz , T. Noulis","doi":"10.1016/j.vlsi.2026.102646","DOIUrl":"10.1016/j.vlsi.2026.102646","url":null,"abstract":"<div><div>Analog and Mixed Signal circuit sizing with large-scale parameters requires a lot of simulations, especially in non-linear topology where large-signal analysis is a need. Reducing the number of simulations and in general the total design cycle time, is the main objective for optimal sizing of complicated circuits. In this work a circuit sizing automated design methodology is presented using the hybrid dual annealing and Nelder–Mead algorithm, significantly reducing the design cycle time and the required number of transient simulations. A customized hybrid algorithm environment using Dual Annealing and Nelder–Mead is developed where the optimization process is divided into different optimization sub-steps. The proposed hybrid algorithm based method achieves rapid convergence to the needed circuit performance specification. It uses combinations of direct search algorithms to separate metric evaluation accelerating the performance specifications convergence speed in a large parameter space. A complicated non-linear topology like a product level low-dropout (LDO) regulator, in 180 nm process node, with 30 parameters is used as the circuit vehicle to verify the proposed methodology. The sizing process converged with less than 1700 simulations having as input just the circuit schematic with no prior sizing knowledge. Sub optimization is also performed focused on each analysis type — DC, AC and transient, with a focus on reducing the number of transient simulations. The proposed combined algorithm method achieved 31 % faster convergence speed compared to the state-of-the-art methods and handles efficiently each simulation analysis.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102646"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-20DOI: 10.1016/j.vlsi.2026.102670
A.N. Busygin , S.Yu. Udovichenko , A.H.A. Ebrahim
Electric circuits of the encoding and decoding devices for converting information from binary representation into a spike sequence and back for hardware spiking neural networks are proposed. The devices differ from the known ones by using fully digital circuitry and memristor-diode crossbars, which potentially reduces energy consumption, provides greater integration of elements and, accordingly, a smaller occupied area on the chip. In addition, changing the states of the memristors makes it possible to arbitrarily set the functions of direct and reverse conversion of binary numbers into spike sequences. The operability of the encoding device is confirmed by numerical simulation of the process of encoding input four-digit number to the times of the first spikes and the average spike frequency. The decoding process is verified during the simulation of the extracting of a four-digit binary number encoded in spike times of three neurons.
{"title":"Encoding and decoding devices based on memristor-diode crossbar-array and CMOS logic for spiking neural networks","authors":"A.N. Busygin , S.Yu. Udovichenko , A.H.A. Ebrahim","doi":"10.1016/j.vlsi.2026.102670","DOIUrl":"10.1016/j.vlsi.2026.102670","url":null,"abstract":"<div><div>Electric circuits of the encoding and decoding devices for converting information from binary representation into a spike sequence and back for hardware spiking neural networks are proposed. The devices differ from the known ones by using fully digital circuitry and memristor-diode crossbars, which potentially reduces energy consumption, provides greater integration of elements and, accordingly, a smaller occupied area on the chip. In addition, changing the states of the memristors makes it possible to arbitrarily set the functions of direct and reverse conversion of binary numbers into spike sequences. The operability of the encoding device is confirmed by numerical simulation of the process of encoding input four-digit number to the times of the first spikes and the average spike frequency. The decoding process is verified during the simulation of the extracting of a four-digit binary number encoded in spike times of three neurons.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102670"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-19DOI: 10.1016/j.vlsi.2026.102664
Hakan Taşkıran, Engin Afacan
Analog and RF integrated circuit (IC) design requires the simultaneous optimization of multiple, conflicting objectives under highly nonlinear and tightly coupled constraints. While prior studies — including our own — have demonstrated the feasibility of applying multi-objective reinforcement learning (MORL) to analog circuit optimization, the specific impact of workflow-level design choices on convergence behavior, simulation cost, and Pareto-front characteristics has remained insufficiently explored. This paper reformulates the Multi-Objective Deep Deterministic Policy Gradient (MODDPG) approach not as a single fixed algorithm, but as a family of optimization workflows that share an identical multi-objective actor–critic learning core while systematically differing in their initialization strategy and environment evaluation mechanism. Within this unified formulation, three configurations are investigated: (i) a baseline MODDPG workflow with random initialization and direct SPICE evaluation, (ii) MODDPG-2, which employs analytically derived extreme solutions to guide early exploration, and (iii) MODDPG-3, which introduces an ANN-based pseudo-designer to generate boundary solutions directly from performance specifications. In addition, a Fully-ANN execution mode is examined, where an ANN-based pseudo-simulator replaces SPICE during policy learning to accelerate environment interaction. By preserving the same reinforcement learning architecture across all variants, the proposed framework isolates the effects of structured initialization and surrogate-based environments on optimization outcomes. The workflows are evaluated on three analog circuits (active-loaded differential amplifier, folded-cascode amplifier, and voltage comparator) and one RF circuit (CMOS cross-coupled LC oscillator), as well as on standard analytical benchmarks. Comparative results against NSGA-II and MOEA/D show that no single method universally dominates; however, the proposed workflows consistently reduce the number of required SPICE simulations by approximately 30%–75% while maintaining competitive Pareto-front quality. This efficiency gain indicates that the reinforcement-learning agent progressively acquires design intuition comparable to that of an experienced human designer—learning to avoid unpromising regions of the design space and focusing evaluations on high-value candidates. The results therefore demonstrate that, beyond the choice of learning algorithm, workflow-level design decisions critically shape how effectively RL can emulate expert design behavior, offering practical guidance for balancing solution quality and computational cost in automated analog and RF circuit design flows.
{"title":"MORL-IC: Multi-objective reinforcement learning approaches for analog integrated circuits optimization","authors":"Hakan Taşkıran, Engin Afacan","doi":"10.1016/j.vlsi.2026.102664","DOIUrl":"10.1016/j.vlsi.2026.102664","url":null,"abstract":"<div><div>Analog and RF integrated circuit (IC) design requires the simultaneous optimization of multiple, conflicting objectives under highly nonlinear and tightly coupled constraints. While prior studies — including our own — have demonstrated the feasibility of applying multi-objective reinforcement learning (MORL) to analog circuit optimization, the specific impact of workflow-level design choices on convergence behavior, simulation cost, and Pareto-front characteristics has remained insufficiently explored. This paper reformulates the Multi-Objective Deep Deterministic Policy Gradient (MODDPG) approach not as a single fixed algorithm, but as a family of optimization workflows that share an identical multi-objective actor–critic learning core while systematically differing in their initialization strategy and environment evaluation mechanism. Within this unified formulation, three configurations are investigated: (i) a baseline MODDPG workflow with random initialization and direct SPICE evaluation, (ii) MODDPG-2, which employs analytically derived extreme solutions to guide early exploration, and (iii) MODDPG-3, which introduces an ANN-based pseudo-designer to generate boundary solutions directly from performance specifications. In addition, a Fully-ANN execution mode is examined, where an ANN-based pseudo-simulator replaces SPICE during policy learning to accelerate environment interaction. By preserving the same reinforcement learning architecture across all variants, the proposed framework isolates the effects of structured initialization and surrogate-based environments on optimization outcomes. The workflows are evaluated on three analog circuits (active-loaded differential amplifier, folded-cascode amplifier, and voltage comparator) and one RF circuit (CMOS cross-coupled LC oscillator), as well as on standard analytical benchmarks. Comparative results against NSGA-II and MOEA/D show that no single method universally dominates; however, the proposed workflows consistently reduce the number of required SPICE simulations by approximately 30%–75% while maintaining competitive Pareto-front quality. This efficiency gain indicates that the reinforcement-learning agent progressively acquires design intuition comparable to that of an experienced human designer—learning to avoid unpromising regions of the design space and focusing evaluations on high-value candidates. The results therefore demonstrate that, beyond the choice of learning algorithm, workflow-level design decisions critically shape how effectively RL can emulate expert design behavior, offering practical guidance for balancing solution quality and computational cost in automated analog and RF circuit design flows.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102664"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-02-02DOI: 10.1016/j.vlsi.2026.102662
Thai N. Nguyen, Jun-Xiang Shi, Vinh T. Nguyen, Shao-I Chu , Bing-Hong Liu
Artificial neural networks (ANNs) have numerous advantages that make them a powerful tool in solving complex problems in many fields, such as image classification, object detection and natural language processing. However, ANNs are facing many challenges due to the increasing complexity of models and the demand to optimize hardware resources. To address these issues, spiking neural networks (SNNs) offers a potential solution to ANNs, which imitate the way the human brain processes information by exploiting the advantage of discrete spikes. This paper presents the sign-magnitude stochastic computing (SC)-based hardware architecture of SNN by the ANN–SNN conversion techniques. This paradigm avoids the complicated floating-point operations and has better computing accuracy as compared to conventional SC. A novel SC-based integrate-and-fire (IF) neuron is presented to construct the core architecture of SNNs, improving the hardware efficiency while reducing the area cost and computational complexity. Hardware implementation results show that the proposed architecture achieves an accuracy of 97.06% for MNIST hand-written digit recognition dataset. As compared with the state-of-the-art designs, the presented architecture has the reductions of at least 35% in chip area, 42% in power consumption, and 86% in core area. The second highest area and energy efficiency are achieved. The hardware efficiency outperforms the baseline by up to .
{"title":"Hardware-efficient architecture of spiking neural networks based on sign-magnitude stochastic computing","authors":"Thai N. Nguyen, Jun-Xiang Shi, Vinh T. Nguyen, Shao-I Chu , Bing-Hong Liu","doi":"10.1016/j.vlsi.2026.102662","DOIUrl":"10.1016/j.vlsi.2026.102662","url":null,"abstract":"<div><div>Artificial neural networks (ANNs) have numerous advantages that make them a powerful tool in solving complex problems in many fields, such as image classification, object detection and natural language processing. However, ANNs are facing many challenges due to the increasing complexity of models and the demand to optimize hardware resources. To address these issues, spiking neural networks (SNNs) offers a potential solution to ANNs, which imitate the way the human brain processes information by exploiting the advantage of discrete spikes. This paper presents the sign-magnitude stochastic computing (SC)-based hardware architecture of SNN by the ANN–SNN conversion techniques. This paradigm avoids the complicated floating-point operations and has better computing accuracy as compared to conventional SC. A novel SC-based integrate-and-fire (IF) neuron is presented to construct the core architecture of SNNs, improving the hardware efficiency while reducing the area cost and computational complexity. Hardware implementation results show that the proposed architecture achieves an accuracy of 97.06% for MNIST hand-written digit recognition dataset. As compared with the state-of-the-art designs, the presented architecture has the reductions of at least 35% in chip area, 42% in power consumption, and 86% in core area. The second highest area and energy efficiency are achieved. The hardware efficiency outperforms the baseline by up to <span><math><mrow><mn>392</mn><mo>×</mo></mrow></math></span>.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102662"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2025-12-15DOI: 10.1016/j.vlsi.2025.102633
M. Maria Rubiston , B.R. Tapas Bapu
Hardware security remains a significant concern because Very Large Scale Integration (VLSI) circuits have become increasingly complex, and industries have begun utilizing untrusted third-party Intellectual Property. Security threats from Hardware Trojans (HTs) remain particularly dangerous since these devices create unethical modifications that break circuit integrity while challenging reliability and damaging confidentiality. Current HT detection methods struggle to scale properly and maintain high accuracy rates due to malicious Trojan design strategies, as well as the constraints of functional testing, side-channel evaluation, and formal verification techniques. To address these challenges, this research introduces DGCoNet-GBOA, a Diffusion Kernel Attention Network with Deformable Graph Convolutional Network-Based Security Framework optimized using the Gooseneck Barnacle Optimization Algorithm (GBOA) for real-time and highly accurate HT detection. The proposed framework extracts structural, power, and transition probability features using Scale-aware Modulation Meet Transformer (S-ammT) and balances the dataset using Diminishing Batch Normalization (DimBN). The DGCoNet framework analyses gate-level netlists (GLNs) as graphical networks to identify HT development changes, and GBOA uses optimization methods that boost detection precision capabilities. The model displays precise Trojan detection abilities, achieving 99.87 % accuracy with just 0.12 % false positive occurrences and 99.91 % precision when testing ISCAS'85 and ISCAS'89 benchmark systems. The proposed DGCoNet-GBOA method achieves an average 0.7–4.5 % improvement in accuracy over existing state-of-the-art approaches across ISCAS'85 and ISCAS'89 benchmarks. The framework built in this research provides scalable, high-reliability HT detection capabilities to safeguard VLSI circuits from present-day hardware security threats during semiconductor design.
{"title":"Identifying malicious modules using deformable graph convolutional network-based security framework for reliable VLSI circuit protection","authors":"M. Maria Rubiston , B.R. Tapas Bapu","doi":"10.1016/j.vlsi.2025.102633","DOIUrl":"10.1016/j.vlsi.2025.102633","url":null,"abstract":"<div><div>Hardware security remains a significant concern because Very Large Scale Integration (VLSI) circuits have become increasingly complex, and industries have begun utilizing untrusted third-party Intellectual Property. Security threats from Hardware Trojans (HTs) remain particularly dangerous since these devices create unethical modifications that break circuit integrity while challenging reliability and damaging confidentiality. Current HT detection methods struggle to scale properly and maintain high accuracy rates due to malicious Trojan design strategies, as well as the constraints of functional testing, side-channel evaluation, and formal verification techniques. To address these challenges, this research introduces DGCoNet-GBOA, a Diffusion Kernel Attention Network with Deformable Graph Convolutional Network-Based Security Framework optimized using the Gooseneck Barnacle Optimization Algorithm (GBOA) for real-time and highly accurate HT detection. The proposed framework extracts structural, power, and transition probability features using Scale-aware Modulation Meet Transformer (S-ammT) and balances the dataset using Diminishing Batch Normalization (DimBN). The DGCoNet framework analyses gate-level netlists (GLNs) as graphical networks to identify HT development changes, and GBOA uses optimization methods that boost detection precision capabilities. The model displays precise Trojan detection abilities, achieving 99.87 % accuracy with just 0.12 % false positive occurrences and 99.91 % precision when testing ISCAS'85 and ISCAS'89 benchmark systems. The proposed DGCoNet-GBOA method achieves an average 0.7–4.5 % improvement in accuracy over existing state-of-the-art approaches across ISCAS'85 and ISCAS'89 benchmarks. The framework built in this research provides scalable, high-reliability HT detection capabilities to safeguard VLSI circuits from present-day hardware security threats during semiconductor design.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102633"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-03DOI: 10.1016/j.vlsi.2025.102645
J. Banumathi, G. Karthy
Signal processing widely uses Finite Impulse Response (FIR) filters because of their stability and linear phase. However, traditional FIR filter designs are limited by multiplication operations that lead to high hardware utilization and delay. To address this, modified FIR filters with optimized multipliers and adders are being developed to improve hardware resource utilization and delay performance. This paper presents novel designs for 8-tap and 16-tap FIR filters, leveraging Brent-Kung Adders (BKA) and Pipelined (P) Urdhva Triyakbhyam Vedic multipliers (UTVM) to achieve minimal delay and enhanced performance. Three architectures—Pipelined FIR using UTVM with BKA (PFIR-UTVM-BKA), FIR using PUTVM with BKA (FIR-PUTVM-BKA), and Pipelined FIR using PUTVM with BKA (PFIR-PUTVM-BKA)—were implemented with different device specifications on Kintex-7, Virtex-7, and Zynq 7000 platforms using Xilinx Vivado 2022.2 and ASIC 45 nm, simulated in Verilog. In FPGA, the proposed multiplier reduces delay by 43 %, 61.55 %, 73.01 %, and 78.51 % across different bit widths, and power, delay, and (power delay Product) PDP were reduced by 82.16 %,94.34 % and 98.99 % respectively, in ASIC. Additionally, the proposed FIR filter architectures achieve significant improvements, including 51.88 % and 27.13 % delay reduction, 75.40 % slice improvement, and 92.53 % and 97.03 % enhancement in slice registers for 8-tap and 16-tap 8-bit designs in FPGA, and power, delay, and PDP (Power Delay Product) were reduced by 87.97 %,97.59 % and 99.71 % respectively, in ASIC. These advancements make the proposed FIR filters highly suitable for high-speed digital signal processing (DSP) applications, where efficient processing and minimized latency are crucial. Integrating PVM and BKA plays a pivotal role in achieving these performance enhancements, positioning these filter designs as promising solutions for next-generation signal processing systems.
{"title":"High-performance FIR filter designs using Brent Kung Adder and pipelined Vedic multiplier","authors":"J. Banumathi, G. Karthy","doi":"10.1016/j.vlsi.2025.102645","DOIUrl":"10.1016/j.vlsi.2025.102645","url":null,"abstract":"<div><div>Signal processing widely uses Finite Impulse Response (FIR) filters because of their stability and linear phase. However, traditional FIR filter designs are limited by multiplication operations that lead to high hardware utilization and delay. To address this, modified FIR filters with optimized multipliers and adders are being developed to improve hardware resource utilization and delay performance. This paper presents novel designs for 8-tap and 16-tap FIR filters, leveraging Brent-Kung Adders (BKA) and Pipelined (P) Urdhva Triyakbhyam Vedic multipliers (UTVM) to achieve minimal delay and enhanced performance. Three architectures—Pipelined FIR using UTVM with BKA (PFIR-UTVM-BKA), FIR using PUTVM with BKA (FIR-PUTVM-BKA), and Pipelined FIR using PUTVM with BKA (PFIR-PUTVM-BKA)—were implemented with different device specifications on Kintex-7, Virtex-7, and Zynq 7000 platforms using Xilinx Vivado 2022.2 and ASIC 45 nm, simulated in Verilog. In FPGA, the proposed multiplier reduces delay by 43 %, 61.55 %, 73.01 %, and 78.51 % across different bit widths, and power, delay, and (power delay Product) PDP were reduced by 82.16 %,94.34 % and 98.99 % respectively, in ASIC. Additionally, the proposed FIR filter architectures achieve significant improvements, including 51.88 % and 27.13 % delay reduction, 75.40 % slice improvement, and 92.53 % and 97.03 % enhancement in slice registers for 8-tap and 16-tap 8-bit designs in FPGA, and power, delay, and PDP (Power Delay Product) were reduced by 87.97 %,97.59 % and 99.71 % respectively, in ASIC. These advancements make the proposed FIR filters highly suitable for high-speed digital signal processing (DSP) applications, where efficient processing and minimized latency are crucial. Integrating PVM and BKA plays a pivotal role in achieving these performance enhancements, positioning these filter designs as promising solutions for next-generation signal processing systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102645"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-16DOI: 10.1016/j.vlsi.2026.102669
Jie Zhang, Jiliang Lv, Nana Cheng, Liu Yang
Using a quadratic memristor as the connection weight between cells, a 4D memristive cellular neural network (CNN) chaotic system is constructed. Through a series of dynamical analyses, it is found that the system exhibits relatively rich dynamical characteristics. In this study, offset boosting is achieved by adding an offset parameter. Furthermore, the system’s amplitude control and attractor rotation are also realized. Based on the fundamental theory of attractor rotation, a multi-wing attractor transformation of the chaotic system is achieved. Additionally, circuit simulation software is used to design and implement a simulation circuit for the 4D memristive chaotic system, and the simulation results verified the physical feasibility of the constructed system. Finally, feedback control is implemented using the control principle. Validation confirms that the designed controller can effectively counteract external disturbances and stabilize the system output.
{"title":"Design of a memristive CNN chaotic system: From chaotic behavior analysis to circuit implementation and robust control","authors":"Jie Zhang, Jiliang Lv, Nana Cheng, Liu Yang","doi":"10.1016/j.vlsi.2026.102669","DOIUrl":"10.1016/j.vlsi.2026.102669","url":null,"abstract":"<div><div>Using a quadratic memristor as the connection weight between cells, a 4D memristive cellular neural network (CNN) chaotic system is constructed. Through a series of dynamical analyses, it is found that the system exhibits relatively rich dynamical characteristics. In this study, offset boosting is achieved by adding an offset parameter. Furthermore, the system’s amplitude control and attractor rotation are also realized. Based on the fundamental theory of attractor rotation, a multi-wing attractor transformation of the chaotic system is achieved. Additionally, circuit simulation software is used to design and implement a simulation circuit for the 4D memristive chaotic system, and the simulation results verified the physical feasibility of the constructed system. Finally, feedback control is implemented using the <span><math><msub><mrow><mi>H</mi></mrow><mrow><mi>∞</mi></mrow></msub></math></span> control principle. Validation confirms that the designed controller can effectively counteract external disturbances and stabilize the system output.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102669"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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