Integration-The Vlsi Journal最新文献

It is a universally acknowledged fact that memristor is widely used in neural networks owing to its memory functions similar to synapses. This paper aims to construct a memristive neural network (MNN) with special dynamic behaviors and structure, which consists of four cyclic neurons and one unidirectional memristive synapse. In this study, we explored the dynamic behaviors, including asymmetric coexisting attractors and parameter-relied large-scale amplitude control. Specially, we found that there are four different types of asymmetric coexisting attractors, namely coexisting double-point (or periodic or chaotic) attractors and coexisting periodic and chaotic attractors. In order to reveal the characteristics of large-scale amplitude control, we used analysis methods such as phase plane plots and time sequences. The existence of this phenomenon is closely related to system parameters and initial values. Meanwhile, a specific circuit experiment is implemented to verify the feasibility of our designation.

This work aims to improves the chaotic behavior of classical logistic chaotic system for voice encryption. In this study, the classical chaotic system was enhanced. This enhanced map has many advantages like a wider chaotic range, more unpredictable, and better ergodicity than many existing chaotic maps (i.e. including 1D and 2D maps). The effectiveness of the improved chaotic system was verified by the bifurcation diagram, performing NIST SP 800-22 and Lyapunov exponent. On this basis, an efficient tweakable voice encryption algorithm was proposed to protect the security of digital voice transmission. The proposed scheme is based on the speech signal being pre-processed to automatically remove silent or voiceless segments, resulting in the extraction of relevant parts of speech for encryption. This leads to a significant reduction in both computing time and resources requirements, as well as the confusion-diffusion architecture. With the aid of the tweak, where each original voice has multiple different encrypted voices using the same secret key which saves time and makes the cost lower compared to changing the key to the proposed scheme. These features make the proposed speech encryption algorithm suitable for real-time communication. In this manner, it is demonstrated that our encryption system effectively withstands known/chosen plaintext attacks. The experimental results demonstrate that the proposed algorithm can withstand several types of attacks through voice encryption. The research results shed new light on the data security in the transmission of voices.

Nowadays, the ASIC design is increasing in complexity, and PPA targets are pushed to the limit. The lack of physical information at the early design stages hinders precise timing predictions and may lead to design re-spins. In previous work, we successfully improved timing prediction at the post-placement stage using the Random Forest model, achieving 91.25% cell delay accuracy. Building upon this, we further investigate the potential of Ensemble Tree-based algorithms, specifically focusing on “Extremely Randomized Trees” and “Gradient Boosting”, to close the gap in cell delay accuracy. In this paper, we enrich the training dataset with new 16 nm industrial designs. The results demonstrate a substantial improvement, with an average cell delay accuracy of 92.01% and 84.26% on unseen data. The average Root-Mean-Square-Error is significantly reduced from 12.11 to 3.23 and 7.76 on unseen data.

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard.

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

Fractional order filters offer greater freedom of design and a precise control over stopband attenuation in electronic circuits and systems. This paper presents the design of a fractional order low pass Chebyshev filter (FOLCF) that achieves near-ideal response characteristics. The methodology introduced utilizes metaheuristic optimization methods, including particle swarm optimization, firefly algorithm, and grey wolf optimization. These techniques are employed to precisely adjust the filter coefficients for the orders (1+α), (2+α), and (3+α). The adjustment is carried out by comparing the desired behaviour of the FOLCF with generalized fractional order low pass transfer functions. Throughout these instances, the parameter α is varied within the range of (0, 1). The designed filters are then tested and compared on the basis of various factors. Simulation results demonstrate that the designed filters closely follow the behaviour of an ideal Chebyshev filter with maximum passband and stopband magnitude errors being −31.93 dB and −52.74 dB respectively for (1+α) order filters. These values for (2+α) and (3+α) order FOLCF have been observed to be −30.04 dB and −55.91 dB; −17.72 dB and −49.52 dB respectively. Furthermore, it has been observed that the proposed work outperforms existing state-of-the-art approaches in various aspects, including magnitude error, stopband attenuation, and cut-off frequency. The stability of the designed filters has been verified through stability analysis. Additionally, practical feasibility of the proposed FOLCF is demonstrated through SPICE simulations for α = [0.2,0.5,0.8] using second generation current conveyor (CCII) and operational transconductance amplifier (OTA) based topologies while approximating the constant phase element using fifth order continued fraction expansion. The SPICE implementations closely follow the behaviour of ideal filter with −48.67 dB and −62.8 dB as mean square errors for CCII and OTA circuits respectively, showcasing the proposed filters' superiority and practical applicability in advanced electronic design.

In low-power designs, the SRAM performance suffers from the process variation. Statistical analysis for the yield of circuit block (e.g., static random-access memory) is extremely time-consuming due to the expensive simulations since the variation space is high-dimensional. In this paper, we construct a mixed neural network to substitute the simulation. We present Mixer. It mainly contains two types of layers: one with regularized sub-radial basis function networks (sub-RBFs) applied independently to extract the effects on circuit performance of the subsets of input process variables, and the other one with multi-layer perceptron (MLP) applied to learn the connection of these extracted effects. When trained with small datasets of high dimension generated from 28 nm memory circuits, our Mixer shows competitive accuracy and efficiency compared with other state-of-the-art models.*

A single-sided Schmitt-trigger driven 10-transistor (ST 10T) static random access memory cell (SRAM) exhibiting lower power consumption, better read and write access time, improved hold and write stability are presented. Using a Schmitt-trigger inverter and a power gating approach, it has better read and write access time and stability. The single bitline structure with stacking effect lowers the proposed cell’s leakage power. The proposed ST 10T cell has a maximum reduction in power consumption of up to 9667.52 times than the considered structure. Furthermore, improvements in write ability and hold stability of up to 1.62 and 1.17 times respectively, are obtained over compared SRAM cells. The cell reduces read and write access times by up to 1.66 and 45.85 times, respectively. The Monte-Carlo (MC) simulations demonstrate the proposed cell’s resilient performance. The simulation is performed using Cadence Virtuoso GPDK 45 nm CMOS technology.

The field of digital signal processing has been receiving increasing attention over the years because of its widespread applications in various fields of science, engineering and technology. In connection to this, design of finite impulse response (FIR) filter has drawn enough attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this work, one novel Right to Left (R2L) algorithm is proposed which can minimize the number of multiplier-adders for the powers-of-two FIR filter. The requirement of such adders essentially depends upon the number of such non-zero entries and the word-length of the input signal. Comparative study has been performed amongst few such hardware efficient realizations of digital filters. Finally, the proposed approach has been implemented using Xilinx Plan Ahead 14.7 so as to have a clear understanding about the requirement of different hardware blocks on a field programmable device.