Integration-The Vlsi Journal最新文献

—Millimeter-wave and terahertz interconnects implemented in advanced complementary metal oxide semiconductor (CMOS) technologies have emerged as promising solutions to fix the issues encountered by baseband interconnects and optical interconnects across specific communication ranges. Over the last decade, significant attempts to advance millimeter-wave and terahertz electronics and platforms have been made. Notably, there have been ground-breaking advancements in active components, including modulation techniques, low-noise receivers, efficient and high-output-power signal generators, and high-frequency clock synthesizers. Nevertheless, since energy efficiency is of paramount importance for interconnect applications, it is necessary to prioritize efficiency enhancements over improvements in signal power, signal integrity and noise related performance. Strategies to improve system output power and phase noise as well as strategies to reduce channel loss and channel electromagnetic crosstalk should leverage alternative approaches, such as architectural optimizations and array configurations, rather than prioritizing energy efficiency. As such, the progression of passive channel technology is equally vital. While reducing channel insertion loss is essential for extending communication reach, channel dispersion and crosstalk limitations at the interface level present critical challenges to achieving optimal bandwidth over distances of up to a few meters. This underscores the need for a balanced focus on both active and passive component innovations to fully harness the potential of millimeter-wave and terahertz interconnects in overcoming the limitations of current CMOS technologies.

Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer. On industrial benchmarks, our algorithm can also achieve a 10.6% improvement in routing wirelength, 27.3% in WNS, and 34.4% in TNS.

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than $70$° phase margin and more than $10\mathrm{dB}$ gain margin with a load capacitor range of 0 to $500\mathrm{pF}$ and consumes less quiescent current. The proposed OTA uses a smaller SMC of $2\mathrm{pF}$ to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC $90\mathrm{nm}$ CMOS technology with BSIM4 MOSFETs.

This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) g_m enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm² of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.

This article deals with the analysis of irregularly shaped single turn octagonal spiral inductors for millimeter-wave and sub-THz CMOS IC designs. Simulations and experimental results, along with theoretical formulations, are used to characterize these irregular structures. This article proposes a novel approach for efficient use of silicon chip area by reshaping the on-chip inductors used in millimeter wave (mm-wave) applications without compromising the performance of the inductors. Especially in CMOS RFICs when a space constraint exists in either $X$- or $Y$-direction in their layout, such reshaping can be attempted. Moreover, two novel methods of reshaping the inductors are proposed and studied thoroughly. The study of these irregular shapes has interesting conclusions, which are validated through on-wafer measurements. Certain methods of reshaping result in inductors which do not have degradation in their quality factors ($Q$), while other approaches degrade the $Q$. Based on these insights, a design methodology is proposed for designers who need to reshape their inductors to irregular structures while not compromising on the quality factor. The measurement results agree with the simulations and prove that the proposed reshaping is practically possible.

Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary to sharply reduce time and memory overhead, and leverages a dedicated Pure MaxSAT solver to re-compact the test patterns generated by ATPG tools. We also observe that ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficiency. In our experiments conducted on benchmark circuits ISCAS89, ITC99, and an open-source RISC-V CPU, we employed two methodologies. For commercial tool, we utilized a non-intrusive approach, while we adopted an intrusive method for open-source ATPG. Under the non-intrusive approach, our method achieved a maximum reduction of 34.69% in pattern count and a maximum 29.80% decrease in test cycles as evaluated by a leading commercial tool. Meanwhile, under the intrusive approach, our method attained a maximum 71.90% reduction in pattern count as evaluated by an open-source ATPG tool. Notably, fault coverage remained unchanged throughout the experiments. Furthermore, our approach demonstrates improved performance compared with existing methods.

In response to the evolving technological landscape, the traditional clock network architecture faces challenges in meeting the complexities of modern System-on-Chip (SoC) designs. While the clock mesh topology offers resilience against On-Chip Variation (OCV) fluctuations, its manual implementation leaves room for advancements in methodology and swift analytical techniques. This paper introduces an innovative clock mesh synthesis approach, leveraging dynamic programming algorithms and emphasizing compliance with critical physical implementation parameters. Our experimental results demonstrate a significant 26.6% reduction in power consumption compared to baseline methodologies. Moreover, it achieves an impressive average runtime reduction of 78.0% when contrasted with traditional simulation methods. These findings underscore the potential of our methodology to enhance the efficiency and power management of clock mesh designs.

In recent years, the application of deep learning (DL) models has sparked considerable interest in timing prediction within the place-and-route (P&R) flow of IC chip design. Specifically, at the pre-route stage, an accurate prediction of post-route timing is challenging due to the lack of sufficient physical information. However, achieving precise timing prediction significantly accelerates the design closure process, saving considerable time and effort. In this work, we propose pre-route timing prediction and optimization framework with graph neural network (GNN) models combined with convolution neural network (CNN). Our framework is divided into two main stages, each of which is further subdivided into smaller steps. Precisely, our GNN-driven arc delay/slew prediction model is divided into two levels: in level-1, it predicts net resistance (net R) and net capacitance (net C) using GNN while the arc length is predicted using CNN. These predictions are hierarchically passed on to level-2 where delay/slew is estimated with our GNN based prediction model. The timing optimization model utilizes the precise delay/slew predictions obtained from the GNN-driven prediction model to accurately set the path margin during the timing optimization stage. This approach effectively reduces unnecessary turn-around iterations in the commercial EDA tools. Experimental results show that by using our proposed framework in P&R, we are able to improve the pre-route prediction accuracy by 42%/36% on average on arc delay/slew, and improve timing metrics in terms of WNS, TNS, and the number of timing violation paths by 77%, 77%, and 64%, which are an increase of 32%/35% on arc delay/slew and 30%, 20% and 31% on timing optimization compared with the existing DL prediction model.

In global routing, congestion and running time are the key factors that affect the quality of the solution. With the rapid growth of integrated chip scale, striking a balance between running time and congestion has become a bottleneck in improving design quality. In this paper, we propose a highly efficient and effective global router to address this challenge. We first propose an efficient R-tree-based compatible routing region partitioning algorithm for collecting routable regions, which offers robust support for ideal parallel routing scheduling. Then, taking into account the effect of the barrel effect on congestion evaluation and the detrimental impact of loops, a congestion-driven initial parallel routing scheme is proposed to enhance routability in the triaxial pattern routing structure. After that, we develop an accurate congestion estimation model and an optimized path-searching scheme, which are instrumental in effectively managing smaller congestion gradient variations and guiding efficient congestion reduction. We evaluate the performance of our algorithm on the ISPD 2018 and ISPD 2019 contest benchmark suites and compare it with the state-of-the-art work. Experimental results show that our proposed algorithm significantly reduces 71% overflows, improving 65% running time, and the total wirelength is even smaller.

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.