Integration-The Vlsi Journal最新文献

In this manuscript, a low noise amplifier (LNA) circuit with low power consumption of 5.3 mW for 3–12 GHz ultra-wideband (UWB) is designed in 90 nm standard CMOS process. A noise-canceling (NC) approach consisting of both common-gate (CG) and common-source (CS) as input stage, followed by the g_m-boosted current-reused stage to enhance the gain performance, is used in the proposed design. After noise-canceling, the achieved noise-figure (NF) is ranging from 2.28 to 3.55 dB for 3.1–10.6 GHz and a maximum of 4.0 dB at 12 GHz. Input-reflection coefficient (S₁₁) of < −12.57 dB is achieved from this CG-CS input-matching stage. With the use of parallel-series LC matching with series-peaking-inductor followed by the g_m-boosting stage improves the gain-bandwidth and delivers a flat power-gain (S₂₁) of 18.33 ± 0.76 dB over 3–12 GHz. The CG configuration at the input side provides a high reverse-isolation (S₁₂) of less than −78.23 dB and common-drain configuration with NMOS load at the output side ensures less than −11.79 dB output-reflection coefficient (S₂₂) over the proposed frequency range. The proposed LNA is operated with 0.7 V V_dd and the achieved intercept points for input (IIP3) and output (OIP3) are −11.1 dBm and +6.2 dBm, respectively.

This paper explicates the design and implementation of a switch capacitor DC–DC converter system for Radio Frequency (RF) energy harvesting applications for an input voltage in the sub-150 mV range, using 180-nm CMOS triple-well BCD technology. The proposed system incorporates a charge pump architecture that employs an improvised Dynamic Gate Biasing (DGB), Forward and Reverse Body Bias technique (FRBB), along with a time axis symmetrical clocking scheme implemented using an advanced bootstrapped CMOS driver to enhance the overall drive capability of the system at low input voltages. Post-layout extracted simulations demonstrate that the proposed system achieves higher overall efficiency, delivering a peak Power Conversion Efficiency (PCE) of 85.8% at 125 mV input voltage, outperforming other state-of-the-art architectures in similar voltage ranges. Moreover, the proposed system exhibits reliable operation even at input voltages as low as 85 mV, while maintaining good overall efficiency.

The increasing connectivity of devices on the Internet of Things (IoT) has created a favorable field for attacks. Consequently, current anomaly-based intrusion detection systems (AIDS) integrate artificial intelligence algorithms, such as machine learning (ML) and deep learning (DL), to manage high data volumes, recognize complex patterns, and detect unknown anomalies. However, the effectiveness of these methods is contingent upon the quality and meaningfulness of the extracted features from IoT-based communications. Also, with the growth of the IoT, feature extraction and selection are becoming increasingly difficult due to data heterogeneity, the generation of massive amounts of information, and the lack of feature standardization. Moreover, current proposals rely on complex feature extraction and selection techniques. As a result, this study introduces a novel approach for ML modeling, including decision trees and random forests, to detect anomalies in IoT. This study aims to overcome feature extraction and selection process dependency by integrating fingerprinting techniques based on locality-sensitive hashing (LSH) to represent network packet information in a suitable format for ML modeling and detecting harmful sequential network packets. The anomaly detection performance was assessed using two benchmark IoT datasets, ToN-IoT and MQTT-IoT, which contain cyberattacks threatening IoT networks. The proposal outperforms other methods regarding accuracy, precision, and FPR with values of 99.82%, 99.93%, and 0.13%, respectively.

In this work, a new subsampling PLL is presented which samples the reference signal by the oscillator’s phase and then again by the divided oscillator phase. The operation is robust due to the action of a frequency divider in the loop. Fractional synthesis can also be easily implemented by modifying the loop containing the frequency divider using a $\Delta \Sigma$ modulator. Post-layout simulations are performed in CMOS 90 nm technology with a 1 GHz ring oscillator. Peak-to-peak jitter over 1000 cycles of the free running ring oscillator is 87 ps. It is reduced to 28 ps through the action of the proposed architecture.

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The $\varphi$-V characteristics of the PFD were found to have better linearity across the range of $-\pi$ to $\pi$ due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 $\mu$W of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of $2.95\mu s$, and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 ${\mathrm{mm}}^2$. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems.

This paper describes a four-wing chaotic oscillator-based DCSK-CDMA modulation technique for image encryption and decryption. The system consists of a transmission module for the encrypted and modulated color matrices, and a reception module for the decrypted and demodulated original data. Among our main contributions is the integration for the first time in the state of the art of DCSK chaotic modulation techniques with the CDMA communication scheme, as well as the implementation of our DCSK and CDMA algorithms in VHDL language for Xilinx FPGA cards. The DCSK-CDMA technique enables demodulation and decryption without any loss in the original data. Other contributions arising from this investigation are the encryption process implemented using DCSK-CDMA techniques based on a four-wing chaotic oscillator and the realization on the FPGA of a chaos-based communications system for the secure transmission of images of grayscale and RGB formats using DCSK-CDMA techniques. The system architecture in this work was designed using fixed-point binary arithmetic, with the application of the 4th order Runge–Kutta numerical method for the four-wing chaotic oscillator. The analysis of the correlation coefficients between the original and encrypted information indicates the values of $5.367\times 10^{-4}$ and $-2.205\times 10^{-7}$ for grayscale and RGB images, respectively, with a full recovery of the original information. The results of simulations in MATLAB/Simulink coincide with the implementation of the complete system in VHDL on the Xilinx Artix-7 AC701 board.

In recent years, chaotic synchronization has received a lot of interest in applications in different fields such as digital applications. The purpose of this work is to achieve the synchronization of the discretized version (DV) of the Méndez–Arellano–Cruz–Martínez (MACM) 3D chaotic system (CS) as master which is coupled to one or more MACM 3D CSs as slaves for three different applications. The Lyapunov Exponents (LEs) analysis is conducted using the numerical-algorithm in MATLAB in order to verify the chaos existence is preserved in the Continuous Version(CV) and DV of the two master–slave MACM CSs once that they are synchronized. Subsequently, the algorithm of the MACM CSs are implemented in two or more isolated embedded systems (ESs) using PIC-24 16-bit microcontrollers which are communicated using the Serial Peripheral Interface (SPI) protocol setting in 16-bits, and the synchronization is validated using the state-variables depicted in digital-to-analog converters (DACs), and the secret-image messages are validated in thin-film-transistor-liquid-crystal displays (TFT-LCDs) depending of the conducted application. In addition, one k-parameter switch is proposed in order to validate the enabled or disabled the synchronization between the master with one or many slave microcontrollers using a 16-bit numerical scaling-arrangement. The first application is the electronic-digital-implementation of the synchronization in real-time of 5 PIC-24 microcontrollers coupled in star-topology, 1 MACM-CS master-node, and 4 MACM-CSs slave-nodes. The second application is the synchronization of the two MACM CSs which are coupled and implemented in two PIC-24 microcontrollers, the master-node is setting to encrypt and transmit a secret-message which involves data to achieve the synchronization and to re-built an image once that the image is received, decrypted and depicted in the TFT-LCD in the slave-node in real-time. The third application is showing the synchronization of the 2 nodes where the message is an decomposed-image stored in a vector-data block in the SRAM (Static Random Access Memory, the stored-data remain in the memory only if the PIC-24 microcontrollers are powered) of the PIC-24 microcontrollers which the process is conducted encrypting and transmitting a secret-message using data to achieve the synchronization and elements of a pixel per finite sample-iterations to receive and decrypt the message in the PIC-24 microcontroller as slave-node, and later the message is re-built in a TFT-LCD. Finally, all the numerical results of the LE studies, comparative security analysis, and the numerical and experimental synchronization of the proposed three applications were validated in the ESs.

This work proposes a novel approach to the hardware implementation of packet classification in ASICs, using NAND-NOR logic at each stage. The proposed design utilizes modified ternary encoding to process the prefix field, resulting in a two-level NAND-NOR logic for prefix processing. The field representation based on classbench rules helps reduce memory usage by almost 45% compared to conventional prefix representations. Additionally, an efficient range matching solution is implemented using a carry tree logic that relies on 1’s and 2’s Complement subtraction. The integration of a carry-based range comparator enhances hardware optimization for range processing without the need for prefix conversion. Additionally, match inversion logic streamlines the processing of exceptional or inverse fields without incurring extra hardware overhead. This work also presents a specialized logic circuit for ternary and range matching, complemented by a specialized priority grouping technique. The proposed architecture, including TYPE1 and TYPE2, achieves throughput rates of 9.9 BPPS and 6.6 BPPS, respectively, while supporting both best-match and multi-match addresses within the same hardware environment.

Traditional digital multipliers are often designed in array forms or other variants. Timing of array-form multipliers can be analyzed by static timing analysis (STA), but the obtained timing result is conservative and pessimistic. Although statistical static timing analysis (SSTA) can partly solve the pessimism, it still does not generate test patterns for those near-to-longest delay paths. Finding near-to-longest delay paths can be helpful to designing error tolerant circuits, with which aggressive timing (with timing violation) can be exploited. In such design scenarios one should find test vectors to activate those near-to-longest delay paths in order to further run SPICE-precision diagnose on those potential timing violating critical paths. Test vector generation for such a testing problem is essentially an exhaustive enumeration problem when dealing with different forms of array multipliers. However, large size multipliers would result in an extremely large enumeration space for finding the longest delay path (LDP) test vectors. Currently there is no deterministic method that can guarantee to find test vectors for exact LDPs of a large size multiplier. Only very few research papers have addressed this problem, proposals are limited to heuristic methods without guarantee of finding the LDPs with the testing vectors. This paper investigates the potential of a genetic algorithm (GA) for searching the extensive test pattern space. By a fine design of GA, experimental running shows that a combination of well tuned evolutionary operators does empower the possibility of finding the LDPs for a set of moderate size carry-save adders (CSA) multipliers with the wordlength (WL) up to 25 bits on a plain laptop computer. Statistical properties of the proposed GA are examined.

It is well known that addition is an essential arithmetic operation in multi-medium applications, wireless applications and multiplication. Based on the predictable sum bits in the addition of two n-bit integers, the logical circuit of an n-bit sum-prediction adder can be constructed and the hardware overhead and the static timing delay of the proposed n-bit sum-prediction adder can be analyzed. In the design of an n-bit sum-prediction adder, the predictable carry bits can lead to the generation of the predictable sum bits in the addition of two n-bit integers. Based on the generation of the predictable sum bits, the carry propagation on a longer link of NMOS transistors can be separated into some carry propagation on some shorter links and the unknown sum bits can be divided into some sum blocks. Furthermore, the unknown sum bits inside each sum block can be generated by propagating the predicted sum bits. For the comparison of the average power and the timing delay in 90 nm technology on the RCAs using full adders, 2-bit CLA blocks, 4-bit CLA blocks, 1-bit CSA blocks, 2-bit CSA blocks or 4-bit CSA blocks, the proposed sum-prediction adder can reduce 5.9 %, 30.7 %, 45.0 %, 18.1 %, 18.8 % and 19.0 % of the average power and reduce 35.0 %, 41.4 %, 12.5 %, 72.3 %, 67.1 % and 62.7 % of the timing delay on the average, respectively.