Pub Date : 2026-01-01Epub Date: 2025-09-08DOI: 10.1016/j.vlsi.2025.102539
Arockia Twinkle J , Srinivasan R , Premanand V. Chandramani
Delta Sigma Modulator (ΔΣM) has in-built noise shaping feature, which is defined by Noise Transfer Function (NTF). Optimization of NTF directly improves the noise shaping property of the ΔΣM and its overall performance. The proposed method employs PSO algorithm for optimizing the NTF. By utilizing its robust global optimization abilities, the PSO algorithm efficiently navigates the design space, converging on optimal NTF that yields Signal to Quantization Noise (SQNR) of 62.7244 dB. Additionally, Cascade of Resonators with Feed-Forward (CRFF) M synthesized with the proposed NTF achieves peak-to-peak SNR ()/peak signal-to-noise ratio (Peak SNR)/average SNR (Peak SNR) of 92.5 dB/82.9594 dB/82.1 dB with reduced computational complexity. The proposed method achieves higher SQNR × Over load level for different Oversampling Ratio (OSR) values when compared to the existing methods.
{"title":"Optimization of fourth order noise transfer function using PSO algorithm for delta sigma modulator","authors":"Arockia Twinkle J , Srinivasan R , Premanand V. Chandramani","doi":"10.1016/j.vlsi.2025.102539","DOIUrl":"10.1016/j.vlsi.2025.102539","url":null,"abstract":"<div><div>Delta Sigma Modulator (ΔΣM) has in-built noise shaping feature, which is defined by Noise Transfer Function (NTF). Optimization of NTF directly improves the noise shaping property of the ΔΣM and its overall performance. The proposed method employs PSO algorithm for optimizing the NTF. By utilizing its robust global optimization abilities, the PSO algorithm efficiently navigates the design space, converging on optimal NTF that yields Signal to Quantization Noise (SQNR) of 62.7244 dB. Additionally, Cascade of Resonators with Feed-Forward (CRFF) <span><math><mrow><mo>Δ</mo><mi>Σ</mi></mrow></math></span>M synthesized with the proposed NTF achieves peak-to-peak SNR (<span><math><mrow><msub><mtext>SNR</mtext><mrow><mi>p</mi><mn>2</mn><mi>p</mi></mrow></msub></mrow></math></span>)/peak signal-to-noise ratio (Peak SNR)/average SNR (Peak SNR) of 92.5 dB/82.9594 dB/82.1 dB with reduced computational complexity. The proposed method achieves higher SQNR × Over load level for different Oversampling Ratio (OSR) values when compared to the existing methods.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102539"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-10-22DOI: 10.1016/j.vlsi.2025.102588
Neha Maheshwari , Ambika Prasad Shah , Santosh Kumar Vishvakarma
In this paper, we explore an SRAM-based ring oscillator design based on gate logic. The gating logic not only ensures stable operation but also provides flexibility in managing the activation and deactivation of the oscillator, thus reducing power consumption during idle periods. The proposed Gated Logic-based SRAM cell consumes 1.17 and 1.02 lower read and write power respectively than conventional 6T SRAM. A detailed analysis validates this proposed SRAM cell can be a good candidate for implementing the memory-based RO with less number of memory cell utilization. The frequency in the schematic is 1.24 that of the post-layout and frequency variation with temperature and aging to ensure the reliability of the proposed ring oscillator. Further proposed GL-SRAM-RO consumes less power and area utilization than the previous design. The simulation results show bidirectional behavior, making it a suitable candidate for security and power efficiency requirements and integration into resource-constrained environments and embedded systems.
{"title":"Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators","authors":"Neha Maheshwari , Ambika Prasad Shah , Santosh Kumar Vishvakarma","doi":"10.1016/j.vlsi.2025.102588","DOIUrl":"10.1016/j.vlsi.2025.102588","url":null,"abstract":"<div><div>In this paper, we explore an SRAM-based ring oscillator design based on gate logic. The gating logic not only ensures stable operation but also provides flexibility in managing the activation and deactivation of the oscillator, thus reducing power consumption during idle periods. The proposed Gated Logic-based SRAM cell consumes 1.17<span><math><mo>×</mo></math></span> and 1.02<span><math><mo>×</mo></math></span> lower read and write power respectively than conventional 6T SRAM. A detailed analysis validates this proposed SRAM cell can be a good candidate for implementing the memory-based RO with less number of memory cell utilization. The frequency in the schematic is 1.24<span><math><mo>×</mo></math></span> that of the post-layout and frequency variation with temperature and aging to ensure the reliability of the proposed ring oscillator. Further proposed GL-SRAM-RO consumes less power and area utilization than the previous design. The simulation results show bidirectional behavior, making it a suitable candidate for security and power efficiency requirements and integration into resource-constrained environments and embedded systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102588"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-09-27DOI: 10.1016/j.vlsi.2025.102566
Meeniga Srikanth Reddy , Debanjali Nath , Debajit Deb
In this paper we propose a two-level power gating technique which could incorporate significant leakage power reduction in pass transistor (PTL) and transmission gate (T-Gate) based look up table (LUT), designed using 45 nm generic library from cadence. First level power gating at SRAM array resulted in reduced subthreshold and gate leakage across the devices. A novel Header/Footer logic has been implemented to power-gate MUX logic of LUT. Unlike conventional header/footer schemes that only cut off the supply or ground to reduce leakage, our diode-connected header and feedback-controlled footer enable parallel output level restoration while simultaneously suppressing leakage. The feedback-controlled footer (NFD) ensures that weak logic levels from the multiplexer do not propagate to the output buffer, thereby reducing subthreshold and gate leakage. The Power-gated SRAM average power dissipation has been observed to reduce from 6.09 pW to 1.884 pW (write-1 operation). Power gating in the SRAM array resulted in a three order magnitude reduction in average power from 17.01 W to 153.05 nW at pass transistor-based LUT level. Similar average power reduction up to 3-orders have also been observed for T-Gate based MUX-LUT with power gated SRAMs from 16.42 W to 688.3 nW. The values were further reduced by more than three orders for both PTL and T-Gate based designs when novel header/footer logic was applied at the MUX level. Post-layout simulations further validate that parasitic effects reduce overall power dissipation compared to the pre-layout results for conventional and gated SRAM based LUTs. Additionally, the CLB implementation demonstrates ultra-low power of 389.8 pW in low-performance mode (HP=0), highlighting the practical advantage of the proposed architecture over conventional LUT-based designs. The implementation of proposed design impose no observable delay of data transfer between input of SRAM to final output of CLB.
{"title":"Power Gated-SRAM and novel header–footer multiplexer based ultra low power Look-Up Table design","authors":"Meeniga Srikanth Reddy , Debanjali Nath , Debajit Deb","doi":"10.1016/j.vlsi.2025.102566","DOIUrl":"10.1016/j.vlsi.2025.102566","url":null,"abstract":"<div><div>In this paper we propose a two-level power gating technique which could incorporate significant leakage power reduction in pass transistor (PTL) and transmission gate (T-Gate) based look up table (LUT), designed using 45 nm generic library from cadence. First level power gating at SRAM array resulted in reduced subthreshold and gate leakage across the devices. A novel Header/Footer logic has been implemented to power-gate MUX logic of LUT. Unlike conventional header/footer schemes that only cut off the supply or ground to reduce leakage, our diode-connected header and feedback-controlled footer enable parallel output level restoration while simultaneously suppressing leakage. The feedback-controlled footer (NFD) ensures that weak logic levels from the multiplexer do not propagate to the output buffer, thereby reducing subthreshold and gate leakage. The Power-gated SRAM average power dissipation has been observed to reduce from 6.09 pW to 1.884 pW (write-1 operation). Power gating in the SRAM array resulted in a three order magnitude reduction in average power from 17.01<span><math><mi>μ</mi></math></span> W to 153.05 nW at pass transistor-based LUT level. Similar average power reduction up to 3-orders have also been observed for T-Gate based MUX-LUT with power gated SRAMs from 16.42<span><math><mi>μ</mi></math></span> W to 688.3 nW. The values were further reduced by more than three orders for both PTL and T-Gate based designs when novel header/footer logic was applied at the MUX level. Post-layout simulations further validate that parasitic effects reduce overall power dissipation compared to the pre-layout results for conventional and gated SRAM based LUTs. Additionally, the CLB implementation demonstrates ultra-low power of 389.8 pW in low-performance mode (HP=0), highlighting the practical advantage of the proposed architecture over conventional LUT-based designs. The implementation of proposed design impose no observable delay of data transfer between input of SRAM to final output of CLB.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102566"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145221216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The nonlinear constitutive relations and multistable memory characteristics of memristors that render them ideal for chaotic systems, this paper introduces the modular arithmetic operations to the memristor and constructs a parameter controlled multiscroll memristive chaotic system (PCMMCS). The unique nonlinearity of modular arithmetic operations endows the system with distinctive dynamical behaviors. Specifically, PCMMCS exhibits a multiplicity of equilibrium points, the types and locations can be regulated via parametric modulation. This mechanism enables precise control over the number of multiscroll attractors, thereby establishing a direct parametric dependency for attractor configuration. The heterogeneous, homogeneous coexisting attractors and infinite coexisting attractors in the system are formatted via initial value manipulation. A hardware realization of the system has been developed, with multiscroll attractor dynamics successfully observed and characterized on an oscilloscope. The PCMMCS was further developed into a dynamic carrier-differential frequency chaos keying (DC-DFCK) secure communication scheme, and experimental results confirming its operational validity, thereby demonstrating the practical applicability of PCMMCS.
{"title":"Dynamical analysis and secure communication application of parameter-controlled multiscroll attractors in memristive chaotic system","authors":"Yijin Liu, Qiang Lai, Huangtao Wang, Yongxian Zhang","doi":"10.1016/j.vlsi.2025.102577","DOIUrl":"10.1016/j.vlsi.2025.102577","url":null,"abstract":"<div><div>The nonlinear constitutive relations and multistable memory characteristics of memristors that render them ideal for chaotic systems, this paper introduces the modular arithmetic operations to the memristor and constructs a parameter controlled multiscroll memristive chaotic system (PCMMCS). The unique nonlinearity of modular arithmetic operations endows the system with distinctive dynamical behaviors. Specifically, PCMMCS exhibits a multiplicity of equilibrium points, the types and locations can be regulated via parametric modulation. This mechanism enables precise control over the number of multiscroll attractors, thereby establishing a direct parametric dependency for attractor configuration. The heterogeneous, homogeneous coexisting attractors and infinite coexisting attractors in the system are formatted via initial value manipulation. A hardware realization of the system has been developed, with multiscroll attractor dynamics successfully observed and characterized on an oscilloscope. The PCMMCS was further developed into a dynamic carrier-differential frequency chaos keying (DC-DFCK) secure communication scheme, and experimental results confirming its operational validity, thereby demonstrating the practical applicability of PCMMCS.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102577"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-09-12DOI: 10.1016/j.vlsi.2025.102520
Mariam Maurice , Rich Edelman , Mohamed Dessouky , Ashraf Salem
Functional verification of analog devices has become a crucial step in validating mixed-signal SoCs. Waiting for the completion of the analog transistor level can delay time-to-market, as digital verification engineers need to ensure both analog and digital systems function correctly when integrated. Given the availability of efficient, reusable, and reliable digital functional verification methodologies — such as Constrained Random Verification (CRV), functional coverage, assertions/checkers, and Universal Verification Methodology (UVM) — this paper explores how these approaches can be applied to an analog-modeled Device Under Test (DUT) to guarantee its functional correctness. The DUT in question is an Analog Phase-Locked Loop (APLL), a vital component in any Integrated Circuit (IC) system. Its complexity, due to its feedback and closed-loop nature, makes it an ideal example for demonstrating functional verification on a modeled analog DUT.
{"title":"Enhanced functional verification models that ensure the full functionality of an A-PLL device","authors":"Mariam Maurice , Rich Edelman , Mohamed Dessouky , Ashraf Salem","doi":"10.1016/j.vlsi.2025.102520","DOIUrl":"10.1016/j.vlsi.2025.102520","url":null,"abstract":"<div><div>Functional verification of analog devices has become a crucial step in validating mixed-signal SoCs. Waiting for the completion of the analog transistor level can delay time-to-market, as digital verification engineers need to ensure both analog and digital systems function correctly when integrated. Given the availability of efficient, reusable, and reliable digital functional verification methodologies — such as Constrained Random Verification (CRV), functional coverage, assertions/checkers, and Universal Verification Methodology (UVM) — this paper explores how these approaches can be applied to an analog-modeled Device Under Test (DUT) to guarantee its functional correctness. The DUT in question is an Analog Phase-Locked Loop (APLL), a vital component in any Integrated Circuit (IC) system. Its complexity, due to its feedback and closed-loop nature, makes it an ideal example for demonstrating functional verification on a modeled analog DUT.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102520"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-09-16DOI: 10.1016/j.vlsi.2025.102551
Xin Xiong, Hongjian Zhou, Pingqiang Zhou
Analog integrated circuit design typically involves extensive analytical derivations to evaluate circuit performance metrics. Although SPICE simulations facilitate efficient prediction of these metrics, the simulation process remains time-consuming as the dimensionality of circuit parameters increases. In this article, we propose integrating Graph Neural Networks (GNN) with Equation Learner Networks (EQL), employing them as pretrained models within a limited range of design parameters. Our results demonstrate that datasets constructed using the method capture design points more efficiently compared to the random sampling of width-to-length () ratios. Furthermore, experimental validation indicates that the pretrained GNN-EQL model achieves superior performance compared to other pretrained models when the parameter range expands across three different amplifier designs. Finally, our approach significantly reduces the required samples by up to 20X when adapting the pretrained model to broader parameter ranges, compared to training a new model from scratch.
{"title":"Few-shot learning GNN-EQL model with gm/ID method for analog integrated circuit design","authors":"Xin Xiong, Hongjian Zhou, Pingqiang Zhou","doi":"10.1016/j.vlsi.2025.102551","DOIUrl":"10.1016/j.vlsi.2025.102551","url":null,"abstract":"<div><div>Analog integrated circuit design typically involves extensive analytical derivations to evaluate circuit performance metrics. Although SPICE simulations facilitate efficient prediction of these metrics, the simulation process remains time-consuming as the dimensionality of circuit parameters increases. In this article, we propose integrating Graph Neural Networks (GNN) with Equation Learner Networks (EQL), employing them as pretrained models within a limited range of design parameters. Our results demonstrate that datasets constructed using the <span><math><mrow><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></mrow></math></span> method capture design points more efficiently compared to the random sampling of width-to-length (<span><math><mrow><mi>W</mi><mo>/</mo><mi>L</mi></mrow></math></span>) ratios. Furthermore, experimental validation indicates that the pretrained GNN-EQL model achieves superior performance compared to other pretrained models when the parameter range expands across three different amplifier designs. Finally, our approach significantly reduces the required samples by up to 20X when adapting the pretrained model to broader parameter ranges, compared to training a new model from scratch.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102551"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
3D-Mesh NoCs containing hundreds of cores suffer from excessive traffic loads in the routers which often lead to the creation of thermal hotspots as well as severe routing congestion issues. The state-of-the-art deterministic routing techniques fail to balance this huge traffic loads due to their rigid path selection policy. On the other hand, adaptive routing techniques require additional temperature- and traffic-detection and management circuits as well as computation-intensive router architectures. Therefore, to harness the fundamental benefits of Network-on-Chip (NoC) architectures such as simplicity and scalability, this work implements a novel deterministic routing technique which efficiently adjusts the routing paths for a target application by adding a halt router in the path between the source and destination routers. A combination of Discrete Particle Swarm Optimization (DPSO) and Simulated Annealing (SA) algorithms have been used to optimally select the halt routers’ positions such that both the traffic load variance of the network and the peak temperature of the chip get reduced. Based on the offline positioning of halt routers a halted routing algorithm has been used to transfer the packets from source to halt router and then halt to destination router. PARSEC and SPLASH-2 benchmarks are used to generate the target traffic patterns. The experimental results show that the proposed halted routing strategy is able to produce significant reduction in both chip temperature (up to 10 °C) and traffic-load variance (up to 42%) when applied on the standard deterministic routing techniques - Thermal-aware Selective Detour (), Downward-XYZ (), , and routings.
{"title":"Thermal and Congestion-aware Deadlock-free Application-specific Novel Halted Routing Strategy in 3D NoCs","authors":"Priyajit Mukherjee , Sayani Ghosh , Hafizur Rahaman , Santanu Chattopadhyay","doi":"10.1016/j.vlsi.2025.102534","DOIUrl":"10.1016/j.vlsi.2025.102534","url":null,"abstract":"<div><div>3D-Mesh NoCs containing hundreds of cores suffer from excessive traffic loads in the routers which often lead to the creation of thermal hotspots as well as severe routing congestion issues. The state-of-the-art deterministic routing techniques fail to balance this huge traffic loads due to their rigid path selection policy. On the other hand, adaptive routing techniques require additional temperature- and traffic-detection and management circuits as well as computation-intensive router architectures. Therefore, to harness the fundamental benefits of Network-on-Chip (NoC) architectures such as simplicity and scalability, this work implements a novel deterministic routing technique which efficiently adjusts the routing paths for a target application by adding a halt router in the path between the source and destination routers. A combination of Discrete Particle Swarm Optimization (DPSO) and Simulated Annealing (SA) algorithms have been used to optimally select the halt routers’ positions such that both the traffic load variance of the network and the peak temperature of the chip get reduced. Based on the offline positioning of halt routers a halted routing algorithm has been used to transfer the packets from source to halt router and then halt to destination router. PARSEC and SPLASH-2 benchmarks are used to generate the target traffic patterns. The experimental results show that the proposed halted routing strategy is able to produce significant reduction in both chip temperature (up to 10 °C) and traffic-load variance (up to 42%) when applied on the standard deterministic routing techniques - Thermal-aware Selective Detour (<span><math><mrow><mi>T</mi><mi>S</mi><mi>D</mi></mrow></math></span>), Downward-XYZ (<span><math><mrow><mi>D</mi><mi>R</mi></mrow></math></span>), <span><math><mrow><mi>X</mi><mi>Y</mi><mi>Z</mi></mrow></math></span>, and <span><math><mrow><mi>Z</mi><mi>X</mi><mi>Y</mi></mrow></math></span> routings.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102534"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-11-01DOI: 10.1016/j.vlsi.2025.102586
Ayush Dahiya, Poornima Mittal, Rajesh Rohilla
The SRAM cell structure in itself offers huge performance improvements in the memory array. An eight transistor SRAM cell (8TP) is presented with high- PMOS transistors used together with nominal- NMOS transistors. The 8TP cell offers a process variation resistant structure which offers a good balance between stability, delay, write margin, leakage and power consumption over other cell structures over a wide range of supply voltages for 0.6 V to 1.2 V. A number of 2000-point Monte Carlo simulations were performed for highlighting the impact of process, voltage and temperature variations on the cell architecture. The 8TP cell has a write-1/write-0 margin (WM) of 0.4091 V/ 0.4092 V at supply of 0.8 V. The stability of the cell is shown by its static noise margin (SNM) which shows a 6 deviation for a temperature range of to 100°C. The cell offers excellent read and write performance compared to various other SRAM cells. The 8TP cell also demonstrates low leakage and power consumption compared among other 8T cells. The 8TP cell exhibits a good balance between speed and stability while having a competitive area footprint as well as half-select resilience which makes it a good choice for low-power applications.
{"title":"A low-power half-select free 8T SRAM cell with process-induced variation resistance for voltage scaling at 32 nm technology node","authors":"Ayush Dahiya, Poornima Mittal, Rajesh Rohilla","doi":"10.1016/j.vlsi.2025.102586","DOIUrl":"10.1016/j.vlsi.2025.102586","url":null,"abstract":"<div><div>The SRAM cell structure in itself offers huge performance improvements in the memory array. An eight transistor SRAM cell (8TP) is presented with high-<span><math><msub><mrow><mi>V</mi></mrow><mrow><mtext>T</mtext></mrow></msub></math></span> PMOS transistors used together with nominal-<span><math><msub><mrow><mi>V</mi></mrow><mrow><mtext>T</mtext></mrow></msub></math></span> NMOS transistors. The 8TP cell offers a process variation resistant structure which offers a good balance between stability, delay, write margin, leakage and power consumption over other cell structures over a wide range of supply voltages for 0.6 V to 1.2 V. A number of 2000-point Monte Carlo simulations were performed for highlighting the impact of process, voltage and temperature variations on the cell architecture. The 8TP cell has a write-1/write-0 margin (WM) of 0.4091 V/ 0.4092 V at supply of 0.8 V. The stability of the cell is shown by its static noise margin (SNM) which shows a 6<span><math><mi>σ</mi></math></span> deviation for a temperature range of <span><math><mrow><mo>−</mo><mn>25</mn><mo>°</mo><mtext>C</mtext></mrow></math></span> to 100°C. The cell offers excellent read and write performance compared to various other SRAM cells. The 8TP cell also demonstrates low leakage and power consumption compared among other 8T cells. The 8TP cell exhibits a good balance between speed and stability while having a competitive area footprint as well as half-select resilience which makes it a good choice for low-power applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102586"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145519609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-10-20DOI: 10.1016/j.vlsi.2025.102585
Mahendra Rathor
Hardware watermarking helps detect various hardware security threats such as piracy, cloning, counterfeiting, and false claim of ownership of semiconductor intellectual property (IP) cores. However, a watermark cannot be uniquely associated with the vendor's identity unless it is created using an individual's unique features. Further, ideally, a watermarking approach should not incur design overhead after incorporating the security features. Therefore, this paper proposes ‘EASY- a zero-cost high level synthesis (HLS) based hardware watermarking scheme based on voice image features’ which not only uses unique features of an individual's voice sample but also offers seamless verification. The proposed verification process is independent of the potential variations in the biometric features values as it regenerates the feature values using a pre-stored voice image for verification. The proposed watermarking is also aware of the interconnect minimization during the embedding process and incurs zero design overhead. The results reveal that the strength of watermark achieved for the proposed approach is on an average 87 % and is considerably higher than the related works. Further, an average reduction in interconnect requirement for the registers sharing is achieved to be around 24.5 %. The proposed work offers the higher security and zero design cost overhead in contrast to the related works.
{"title":"EASY: Exploring zero-cost watermarking using voice image features for hardware security","authors":"Mahendra Rathor","doi":"10.1016/j.vlsi.2025.102585","DOIUrl":"10.1016/j.vlsi.2025.102585","url":null,"abstract":"<div><div>Hardware watermarking helps detect various hardware security threats such as piracy, cloning, counterfeiting, and false claim of ownership of semiconductor intellectual property (IP) cores. However, a watermark cannot be uniquely associated with the vendor's identity unless it is created using an individual's unique features. Further, ideally, a watermarking approach should not incur design overhead after incorporating the security features. Therefore, this paper proposes ‘<em>EASY- a zero-cost high level synthesis (HLS) based hardware watermarking scheme based on voice image features</em>’ which not only uses unique features of an individual's voice sample but also offers seamless verification. The proposed verification process is independent of the potential variations in the biometric features values as it regenerates the feature values using a pre-stored voice image for verification. The proposed watermarking is also aware of the interconnect minimization during the embedding process and incurs zero design overhead. The results reveal that the strength of watermark achieved for the proposed approach is on an average 87 % and is considerably higher than the related works. Further, an average reduction in interconnect requirement for the registers sharing is achieved to be around 24.5 %. The proposed work offers the higher security and zero design cost overhead in contrast to the related works.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102585"},"PeriodicalIF":2.5,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-10-17DOI: 10.1016/j.vlsi.2025.102584
Xiaosong Wang, Qisheng Zhang, Yu Zhang
This paper proposes a frequency compensation scheme – high-pass feed-forward simple Miller compensation (SMCHPF), based on the output-capacitorless low dropout regulator (OCL-LDO) structure. Adding a high-pass feed-forward path to the LDO extends the bandwidth of the Miller loop, allowing the OCL-LDO to maintain loop stability with smaller output currents under no-load conditions. Additionally, it enhances the transient performance of the OCL-LDO, improving the slew rate of the power transistor gate. Furthermore, high-performance adaptive bias amplifiers, dynamic buffers, and non-linear current mirrors are used in the OCL-LDO to enhance performance. This designed SMCHPF-LDO was fabricated in TSMC 65 nm process, and the core area is . The actual operating voltage range is 2.7V-3.6V, with an output voltage of 0.61V–3.1V and a minimum voltage drop of 80 mV. The SMCHPF-LDO can drive a maximum load current of 50 mA and a load capacitance of 100 pF with a quiescent current consumption of 68 A and a maximum current efficiency of 99.86%. The test results show that the overshoot is 99.5 mV and the undershoot is 316 mV when the load current is switched between 0 mA and 50 mA within 180 ns under a 100pF load capacitor. In addition, the SMCHPF-LDO achieves a line regulation of 5.6mV/V and a load regulation of 0.304 mV/mA, allowing for the power supply rejection over the frequency range of 0–25 MHz.
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