This work presents challenges and solutions of global interconnect in Network-on-Chip (NoC) based System-on-Chips (SoCs) for congestion-free communication between different quantum accelerators in quantum computing systems. To address these problems, we have proposed two novel topologies in two-dimensional (2-D) and four topologies in three-dimensional (3-D). These topologies are based on two different architectural connection methods. The first two are the hybrid connection of the ring-of-mesh, with partial-diagonal-link (HMRPD) in 2-D and 3-D, and the other two are the hybrid connection of the ring-of-torus, with partial-diagonal-link (HTRPD) in 2-D and 3-D. Initially, the parametric analysis performed for both 2-D topologies and result shows that the interconnect has less diameter and average distance, which leads to reduce latency. It requires a small node degree, which makes it more accessible to design a network. It has a high bisection bandwidth, which helps in achieving low communication cost and high throughput. The scalability is higher than that of another existing interconnect. Further, we have examined the throughput, packet latency, and energy consumption of the interconnect for performance comparison of topologies under synthetic traffic patterns. We found that the proposed technique improves performance, optimizes communication cost, and energy consumption. Next, the 2-D HMRPD and 2-D HTRPD extended to 3-D symmetric network architectures by appending two additional ports in 2-D router architectures, namely up port and down port, and connecting these ports by Through Silicon Via (TSV), and routing of packets performed by a quasi-minimal routing technique. The result shows that these 3-D HMRPD and HTRPD have better performance than the 2-D HMRPD, 2-D HTRPD, and existing topologies. Unfortunately, these 3-D topologies result in extra energy consumption issues. Therefore, to solve this issue, heterogeneous layout of 2-D and 3-D router integration techniques applied in 3-D topologies for reducing number of TSV. Furthermore, we have presented two 3-D HTRPD topologies with TSV optimized and compared them with a full TSV-connected 3-D HTRPD. We found that 1P-3DR-HTRPD topology has the lowest gate count, area, dynamic, and static power consumption in comparison to fully connected 3-D HTRPD topology. This work has been designed by modifying network system simulator and also implemented in the Xc7z020clg484-1 ZYNQ FPGA device for validation. Furthermore, we have also examined that these 2-D topologies are more area-efficient and require a maximum crossbar size of 6x6 and have a high frequency of 2.29 GHz and 2.22 GHz for 2-D HMRPD and 2-D HTRPD, respectively, in comparison to other diagonal link topologies.
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