Integration-The Vlsi Journal最新文献_第6页

Routability–wirelength co-guided cell inflation with explainable multi-task learning for global placement optimization 可达性-无线协同引导细胞膨胀与可解释的多任务学习，用于全局布局优化

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-12-01 DOI: 10.1016/j.vlsi.2025.102624

Yan Xing, Zicheng Deng, Shuting Cai, Weijun Li, Xiaoming Xiong

Existing routability-driven global placers typically employed an iterative routability optimization process and performed cell inflation based only on lookahead congestion maps during each run. However, this incremental application of congestion estimation and mitigation resulted in placement solutions that deviate from optimal wirelength, thus compromising the optimization objective of balancing wirelength minimization and routability optimization. To simultaneously improve routability and reduce wirelength, this paper proposes a novel routability–wirelength co-guided cell inflation approach for global placement optimization. It employs a multi-task learning-based feature selection method, MTL-FS, to identify the optimal feature subset and train the corresponding routability–wirelength co-learning model, RWNet. During the iterative optimization process, both routability and wirelength are predicted using RWNet, and their correlation is interpreted by DeepSHAP to produce three impact maps. Subsequently, routability–wirelength co-guided cell inflation (RWCI) is performed based on an adjusted congestion map, which is derived from the predicted congestion map and the three impact maps. The experimental results on ISPD2011 and DAC2012 benchmark designs demonstrate that, compared to DERAMPlace and RoutePlacer (which represent non-machine learning-based and machine learning-based routability-driven placers, respectively), the proposed approach achieves both better optimization quality, specifically improved routability and reduced wirelength, and a decreased time cost. Moreover, the extension experiment shows our method consistently outperforms DREAMPlace (even when it uses 2D feature maps as proxies) in effectiveness while maintaining comparable efficiency. The Generalization experiment further confirms this superiority and comparable runtime, particularly in highly congested scenarios.

现有的可达性驱动的全局放置器通常采用迭代的可达性优化过程，并且在每次运行期间仅基于前瞻拥塞图执行单元膨胀。然而，这种对拥塞估计和缓解的增量应用导致放置解决方案偏离最佳无线长度，从而损害了平衡无线长度最小化和可达性优化的优化目标。为了同时提高可达性和减少无线长度，本文提出了一种新的可达性-无线长度协同引导的蜂窝膨胀方法，用于全局布局优化。它采用基于多任务学习的特征选择方法MTL-FS来识别最优特征子集，并训练相应的路由-无线共同学习模型RWNet。在迭代优化过程中，使用RWNet预测可达性和无线长度，并通过DeepSHAP解释它们的相关性，生成三个影响图。随后，基于调整后的拥塞图（由预测的拥塞图和三个影响图导出）执行可达性-无线共同引导蜂窝膨胀（RWCI）。在ISPD2011和DAC2012基准设计上的实验结果表明，与DERAMPlace和RoutePlacer（分别代表非机器学习和基于机器学习的可达性驱动的放料器）相比，所提出的方法实现了更好的优化质量，特别是提高了可达性和缩短了无线长度，并且降低了时间成本。此外，扩展实验表明，我们的方法在保持相当效率的同时，在有效性上始终优于DREAMPlace（即使它使用2D特征映射作为代理）。泛化实验进一步证实了这种优越性和可比较的运行时间，特别是在高度拥塞的场景下。

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引用次数: 0

Optimizing detailed-routability for 3D global routing through dynamic resource model and routability-aware cost scheme 通过动态资源模型和可达性感知成本方案优化三维全局路由的详细可达性

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-29 DOI: 10.1016/j.vlsi.2025.102616

Juntao Jian, Yan Xing, Shuting Cai, Weijun Li, Xiaoming Xiong

Detailed-routability optimization methods for three-dimensional global routing typically employ a two-stage process involving initial routing and multi-level maze routing (iterative rip-up and reroute, or RRR iterations). Within the coarse-grained maze route planning of RRR iterations, the resource model and cost scheme are paramount for optimization quality. However, current advancements in these areas often overlook the dynamic nature of routing resources throughout RRR iterations and fail to consider routability features beyond congestion. To mitigate these limitations, this paper introduces a novel detailed-routability optimization approach that integrates a dynamic resource model and a routability-aware cost scheme. The proposed dynamic resource model accounts for routing resources’ sensitivity to both spatial information and the progression of RRR iterations. Moreover, the routability-aware cost scheme, derived from coarse-grained routability features, is designed to optimize fine-grained routability. Experimental results validate that our approach surpasses baseline detailed-routability-driven global routers, exhibiting superior optimization performance by concurrently enhancing routability and overall quality scores (a weighted summation of wirelength and routability metrics), alongside achieving significant runtime reduction.

三维全局路由的详细可达性优化方法通常采用两阶段过程，包括初始路由和多级迷宫路由（迭代撕破和重新路由，或RRR迭代）。在RRR迭代的粗粒度迷宫路径规划中，资源模型和成本方案对优化质量至关重要。然而，目前这些领域的进展往往忽略了路由资源在RRR迭代过程中的动态特性，并且没有考虑到除了拥塞之外的可达性特征。为了减轻这些限制，本文引入了一种新的详细可达性优化方法，该方法集成了动态资源模型和可达性感知成本方案。提出的动态资源模型考虑了路由资源对空间信息的敏感性和RRR迭代进程的敏感性。此外，基于粗粒度可达性特征的可达性感知成本方案旨在优化细粒度可达性。实验结果证实，我们的方法超越了基准的详细可达性驱动的全局路由器，通过同时增强可达性和整体质量分数（无线长度和可达性指标的加权总和），表现出卓越的优化性能，同时显著减少了运行时间。

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引用次数: 0

Design insights for implementing a PRNG with fractional Lorenz system on ESP32 and FPGA 在ESP32和FPGA上实现带有分数洛伦兹系统的PRNG的设计见解

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-29 DOI: 10.1016/j.vlsi.2025.102622

Luis Gerardo de la Fraga , Esteban Tlelo-Cuautle

A Pseudo Random Number Generator (PRNG) produces a sequence whose randomness is evaluated by statistical tests like NIST and TestU01. The random sequences are deterministic and reproducible when using the same seed value. In this manner, and for cryptographic applications, the key size of a PRNG must be increased to resist brute force attacks. Henceforth, a fractional-order chaotic system, like the Lorenz one, is suitable to be used to design a PRNG, which implementation can be performed by using embedded devices such as the low-cost ESP32 (32-bit LX6 microprocessor) and field-programmable gate array (FPGA). To increase the throughput, the fractional Lorenz system is integrated with an approximated two steps Runge–Kutta method. An analysis in performed to find the domain of attraction for each state variable, and to verify that the PRNG produces non-correlated sequences. The hardware implementation is detailed by establishing the number of bits (or keys) required for the PRNG to guarantee its suitability for cryptographic applications. Finally, the hardware design of a PRNG using the fractional Lorenz system provides a throughput of 4.99 Mbits/s in the ESP32 platform, and 112.96 Mbits/s in the FPGA.

伪随机数生成器（PRNG）生成一个序列，其随机性由NIST和TestU01等统计测试评估。当使用相同的种子值时，随机序列具有确定性和可重复性。以这种方式，对于加密应用程序，必须增加PRNG的密钥大小以抵抗暴力攻击。因此，分数阶混沌系统，如洛伦兹系统，适合用于设计PRNG，其实现可以使用嵌入式器件，如低成本的ESP32（32位LX6微处理器）和现场可编程门阵列（FPGA）来实现。为了提高通量，将分数阶洛伦兹系统与近似两步龙格-库塔方法相结合。进行了分析，以找到每个状态变量的吸引域，并验证PRNG产生非相关序列。通过建立PRNG所需的比特（或密钥）数量来确保其适合加密应用程序，详细介绍了硬件实现。最后，采用分数阶洛伦兹系统的PRNG硬件设计在ESP32平台上的吞吐量为4.99 Mbits/s，在FPGA上的吞吐量为112.96 Mbits/s。

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引用次数: 0

Error expectation-driven design and energy optimization of approximate multipliers 误差预期驱动的近似乘法器设计与能量优化

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-28 DOI: 10.1016/j.vlsi.2025.102620

Yiqi Zhou , Yanghui Wu , Daying Sun , Shan Shen , Xiong Cheng , Li Li

Multipliers dominate energy consumption in digital signal processing (DSP) systems, while approximate multipliers offer accuracy-efficiency trade-offs, many existing designs suffer from suboptimal energy efficiency. This paper presents an error compensation algorithm that minimizes the global error expectation (EE). By analyzing the error distribution across approximate compressor columns, the algorithm determines optimal compensation positions to reduce EE while maintaining low hardware overhead. Based on this approach, two high energy efficiency approximate multipliers (HEAMs) are proposed: HEAM_M1, optimized for high accuracy, and HEAM_M2, which incorporates a newly designed 4-1 approximate compressor for ultra-low power applications. Compared to an exact multiplier, HEAM_M1 and HEAM_M2 achieve power-delay product (PDP) reductions of 32% and 54%, respectively. Moreover, compared to prior approximate multipliers with similar PDP levels, HEAM_M1 reduces NMED and MRED by 80% and 83%, while HEAM_M2 achieves reductions of 70% and 86%, respectively. Application-level evaluations on image processing and neural network tasks further demonstrate the effectiveness and robustness of the proposed designs.

在数字信号处理（DSP）系统中，乘法器主导着能源消耗，而近似乘法器提供了精度和效率的权衡，许多现有的设计都遭受着次优能源效率的困扰。提出了一种最小化全局误差期望（EE）的误差补偿算法。通过分析近似压缩机列之间的误差分布，该算法确定最佳补偿位置，以减少EE，同时保持较低的硬件开销。基于这种方法，提出了两种高能效近似乘法器（HEAMs）：针对高精度进行优化的HEAM_M1和包含新设计的用于超低功耗应用的4-1近似压缩机的HEAM_M2。与精确乘法器相比，HEAM_M1和HEAM_M2分别实现了32%和54%的功率延迟积（PDP）降低。此外，与先前具有相似PDP水平的近似乘数相比，HEAM_M1将NMED和MRED分别降低了80%和83%，而HEAM_M2分别降低了70%和86%。对图像处理和神经网络任务的应用级评估进一步证明了所提出设计的有效性和鲁棒性。

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引用次数: 0

NeSTAR: Hardware Trojans and its mitigation strategy in NoC routers NeSTAR: NoC路由器中的硬件木马及其缓解策略

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-26 DOI: 10.1016/j.vlsi.2025.102603

Josna Philomina , Rekha K. James , Shirshendu Das , Palash Das , Daleesha M Viswanathan

As Network-on-Chip (NoC) designs become essential in Tiled Chip Multicore Processor (TCMP) systems, it is increasingly important to protect NoC router communication from disruptions caused by hardware Trojans (HT). TCMPs often use intellectual property (IP) blocks from multiple vendors to design their NoC. This opens the door for untrusted vendors to compromise system security by inserting HTs into these IPs, which can alter the normal operation of NoC routers. These HTs are especially dangerous because they can remain undetected during the chip verification and testing stages. This paper explores how multiple HTs placed in the Route Computation Unit (RCU) of NoC routers can interfere with routing decisions, affect packet delivery, and harm overall system performance. We analyze the effects of these HTs using both synthetic traffic and real-world benchmarks, measuring their impact on latency, throughput and processor instructions per cycle (IPC). To address these issues, we introduce a solution called Neighbor-Supported Trojan-Aware Routing (NeSTAR). NeSTAR uses cooperation among neighboring routers to make routing decisions, helping the network to continue to function even when some RCUs are compromised. Our experimental results show that NeSTAR can reduce latency by 46%, improve throughput by 262%, lower packet deflected latency by 69%, and improve IPC by 37%, compared to the NoC affected by HT.

随着片上网络（NoC）设计在平铺片多核处理器（TCMP）系统中变得越来越重要，保护NoC路由器通信免受硬件木马（HT）造成的中断变得越来越重要。tcm通常使用来自多个供应商的知识产权（IP）块来设计他们的NoC。这为不受信任的供应商打开了一扇门，通过在这些ip中插入ht来破坏系统安全，这可能会改变NoC路由器的正常运行。这些高温超导尤其危险，因为它们可能在芯片验证和测试阶段未被发现。本文探讨了放置在NoC路由器的路由计算单元（RCU）中的多个ht如何干扰路由决策，影响数据包传递，并损害整体系统性能。我们使用合成流量和实际基准来分析这些ht的影响，测量它们对延迟、吞吐量和每周期处理器指令（IPC）的影响。为了解决这些问题，我们引入了一种称为邻居支持的木马感知路由（NeSTAR）的解决方案。NeSTAR使用相邻路由器之间的合作来做出路由决策，即使某些rcu受到损害，也可以帮助网络继续运行。我们的实验结果表明，与受HT影响的NoC相比，NeSTAR可以减少46%的延迟，提高262%的吞吐量，降低69%的数据包偏转延迟，提高37%的IPC。

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引用次数: 0

Enhanced fault detection in digital VLSI circuits using convolutional autoencoders 利用卷积自编码器增强数字VLSI电路的故障检测

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-25 DOI: 10.1016/j.vlsi.2025.102608

Chandrasekhar Savalam , Sanjay Medisetti , Prasanti Korapati

As Very Large-Scale Integration (VLSI) technology advances, the demand for reliable and scalable pre-silicon fault detection (FD) techniques continues to grow. Conventional diagnostic methods often face limitations in identifying subtle stuck-at faults within complex and high-dimensional test data. This study proposes a deep learning-based fault detection framework that integrates unsupervised and supervised learning to enhance fault identification and classification in combinational circuits. A Convolutional Autoencoder (CAE) is employed to extract spatial and structural features from circuit test patterns, effectively reducing dimensionality while preserving fault-related information. The encoded features are then classified using a Random Forest model for precise fault localization. The proposed framework is validated on ISCAS’85 benchmark circuits of different sizes and complexities, achieving fault detection accuracies ranging from 93 % to 100 %. Notably, when compared to existing models such as SSAE, VAE, and CEAE, which recorded accuracies between 83 % to 98 %, the proposed CAE-Random Forest framework consistently outperformed them across all benchmarks. Furthermore, the model exhibited stable convergence, low reconstruction error, and efficient memory usage of about 380–403 MB, ensuring reliable and scalable performance. Overall, these results demonstrate that the framework offers a robust, high-accuracy, and resource-efficient solution for automatic fault detection in digital VLSI circuits. It can also be effectively extended to more complex architectures for improved diagnostic reliability.

随着超大规模集成电路（VLSI）技术的进步，对可靠和可扩展的预硅故障检测（FD）技术的需求不断增长。传统的诊断方法在识别复杂和高维测试数据中的细微卡滞故障时往往面临局限性。本文提出了一种基于深度学习的故障检测框架，该框架将无监督学习和有监督学习相结合，以增强组合电路的故障识别和分类能力。采用卷积自编码器（CAE）从电路测试图中提取空间和结构特征，有效地降低了维数，同时保留了故障相关信息。然后使用随机森林模型对编码特征进行分类，以实现精确的故障定位。该框架在不同尺寸和复杂程度的ISCAS’85基准电路上进行了验证，实现了93% ~ 100%的故障检测准确率。值得注意的是，与现有的模型（如SSAE、VAE和CEAE）相比，所提出的cae -随机森林框架在所有基准测试中始终优于它们，这些模型记录的准确率在83%到98%之间。此外，该模型收敛稳定，重构误差低，内存利用率约为380-403 MB，具有可靠的可扩展性。总体而言，这些结果表明，该框架为数字VLSI电路中的自动故障检测提供了鲁棒、高精度和资源高效的解决方案。它还可以有效地扩展到更复杂的体系结构，以提高诊断可靠性。

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引用次数: 0

A progressive self-training semi-supervised model to enhance discontinuous change detection 一种渐进式自训练半监督模型，增强不连续变化检测

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-25 DOI: 10.1016/j.vlsi.2025.102609

Yamane Soma , Sakai Yuwa , Riaz-ul-haque Mian

Wafer-level performance has garnered significant attention within the industry. In this study, to achieve accurate modeling in a multisite testing environment, we explore the potential of incorporating Semi-Supervised Progressive Self-Training techniques into Gaussian process regression. Our experimental results, based on industrial production test data, show that the proposed progressive self-training Semi-Supervised Model outperforms two state-of-the-art methods: The Hierarchical Gaussian Process Regression (HGP) model and the Active Learning-Based Gaussian Process Regression (AHGP) model. Specifically, the proposed method achieved 29% and 80% less errors compared to the HGP model and cluster-based (Two Step) method respectively with the similar training data. Furthermore, it reduced testing costs by 50% while maintaining accuracy levels comparable to state-of-the-art active learning (AHGP) based models in a multi-site testing environment.

晶圆级性能在业界引起了极大的关注。在本研究中，为了在多站点测试环境中实现精确建模，我们探索了将半监督渐进式自我训练技术纳入高斯过程回归的潜力。基于工业生产测试数据的实验结果表明，所提出的渐进式自训练半监督模型优于两种最先进的方法：层次高斯过程回归（HGP）模型和基于主动学习的高斯过程回归（AHGP）模型。具体而言，在相似的训练数据下，与HGP模型和基于聚类（Two Step）的方法相比，该方法的误差分别降低了29%和80%。此外，它降低了50%的测试成本，同时在多站点测试环境中保持了与最先进的主动学习（AHGP）模型相当的精度水平。

引用次数: 0

EE DC-DB PFAL: A novel two-phase adiabatic logic family for low-power 14 nm FinFET-Based hybrid full adders EE DC-DB PFAL：一种新型的两相绝热逻辑系列，用于低功耗14nm基于finfet的混合全加法器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-24 DOI: 10.1016/j.vlsi.2025.102605

Sukhreet Kaur, Rita Mahajan, Deepak Bagai

This paper presents a novel hybrid 1-bit full adder design integrating 14 nm FinFET technology with a two-phase adiabatic logic family—Energy-Efficient Diode-Connected, DC-Biased Positive Feedback Adiabatic Logic (EE DC-DB PFAL)—and Modified Gate Diffusion Input (MGDI) logic. The proposed design achieves an average power consumption of 4.36 nW, a power-delay product of 1.26 aJ, and a transistor count of only 15, demonstrating significant energy efficiency and performance improvements compared to existing benchmark adder architectures. Transistor-level analysis, including Gm/Id considerations, validates optimized device sizing and energy-efficient switching. Layout and post-layout simulations confirm compact design and practical feasibility. The design demonstrates robustness under process, voltage, and temperature (PVT) variations, ensuring reliable operation across a wide range of operating conditions. Scalability across technology nodes from 7 nm to 20nm is demonstrated, and the methodology can be extended to multi-bit arithmetic units and full-scale ALUs. The proposed adder is particularly suitable for IoT edge nodes, wearable and biomedical devices, and portable communication processors.

本文提出了一种新型的混合1位全加法器设计，集成了14nm FinFET技术和两相绝热逻辑系列——节能二极管连接、直流偏置正反馈绝热逻辑（EE DC-DB PFAL）和改进的门扩散输入（MGDI）逻辑。该设计的平均功耗为4.36 nW，功率延迟积为1.26 aJ，晶体管数量仅为15，与现有基准加法器架构相比，显示出显著的能效和性能改进。晶体管级分析，包括Gm/Id考虑，验证了优化的器件尺寸和节能开关。布局和布局后仿真验证了紧凑的设计和实际的可行性。该设计在工艺、电压和温度（PVT）变化下具有稳健性，确保在各种操作条件下可靠运行。演示了从7纳米到20纳米的技术节点的可扩展性，并且该方法可以扩展到多位算术单元和全尺寸alu。该加法器特别适用于物联网边缘节点、可穿戴和生物医学设备以及便携式通信处理器。

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引用次数: 0

Higher-order filters based on the Mittag-Leffler function 基于Mittag-Leffler函数的高阶滤波器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-24 DOI: 10.1016/j.vlsi.2025.102607

Ahmed S. Elwakil , Brent J. Maundy , Anis Allagui , Costas Psychalinos

In this work, we show how higher-order low-pass, high-pass, band-pass or band-stop filter functions can be systematically obtained using the Mittag-Leffler (ML) function as a basic building block. In particular, by multiplying (i.e. cascading) two or more ML functions; each having the form of a two-parameter ML function

E_{α, β} (z)

(

0 \leq α, β \leq 1

) with its argument z being equal to

- s

or

- 1 /

s (

s

is the complex frequency; i.e.

s = j ω

), higher-order fractional filters can be obtained. We focus here on the cascade of two ML functions, which produces second-order transfer functions (as a special case) when

α = 0

and

β = 1

. We derive in closed form the impulse response and step-response of these filters and experimentally verify their behavior after approximating the ML function using a suitable integer-order approximation. It is worth mentioning that this class of filters does not employ the fractional-order Laplace operator

s^{\pm γ}

(

0 < γ \leq 1

), unlike classical fractional-order filters.

在这项工作中，我们展示了如何使用Mittag-Leffler （ML）函数作为基本构建块系统地获得高阶低通、高通、带通或带阻滤波器函数。特别是，通过乘法（即级联）两个或多个ML函数；各具有双参数ML函数Eα，β(z)（0≤α,β≤1）的形式，其参数z等于- s或- 1/s (s为复频率，即s=jω)，则可以得到高阶分数阶滤波器。我们在这里关注两个ML函数的级联，当α=0和β=1时，它产生二阶传递函数（作为特殊情况）。我们以封闭形式推导了这些滤波器的脉冲响应和阶跃响应，并在使用合适的整阶近似近似ML函数后实验验证了它们的行为。值得一提的是，这类滤波器不像经典的分数阶滤波器那样使用分数阶拉普拉斯算子s±γ (0<γ≤1)。

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引用次数: 0

A differential in-memory computing 12T SRAM macro with enhanced flexibility and reliability for XNOR-network 一个差分内存计算12T SRAM宏，增强了xnor网络的灵活性和可靠性

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-20 DOI: 10.1016/j.vlsi.2025.102604

Dekai Sun , Zhang Zhang , Wenyan Liu , Hongbin Yang , Yi Lu , Yonghong Zeng , Biao Zhang , Lianjie Lu

Implementing an artificial intelligence algorithm requires a lot of calculation, but the calculation process needs a lot of data migration, which consumes a lot of energy and time. In-memory computing is a promising paradigm to ease this limitation. XNOR-Network is an effective acceleration technique and has been widely applied in in-memory computing SRAM macro. Current in-memory computing SRAM macro for XNOR-Network has challenges in flexibility and reliability. To overcome these challenges, this paper proposes a differential in-memory computing 12T SRAM macro for XNOR-Network. The proposed SRAM macro eliminates the issue of memory information flipping that occurs during XNOR-and-accumulate operations. Moreover, it is capable of supporting XNOR-and-accumulate operations of varying sizes. Additionally, the XNOR-and-accumulate result can be read out quickly by the sensitive amplifier for its sign or read out by the Flash ADC for its multi-bit quantized value. The proposed architecture has an energy efficiency of 98.6TOPS/W and a recognition rate of 97.06% for MNIST data set.

实现人工智能算法需要大量的计算，但计算过程需要大量的数据迁移，消耗大量的能量和时间。内存计算是缓解这种限制的一个很有前途的范例。xnor网络是一种有效的加速技术，在内存中计算SRAM宏中得到了广泛的应用。当前用于xnor网络的内存计算SRAM宏在灵活性和可靠性方面面临挑战。为了克服这些挑战，本文提出了一种用于xnor网络的差分内存计算12T SRAM宏。所提出的SRAM宏消除了在xnor和累加操作期间发生的内存信息翻转问题。此外，它还能够支持不同大小的xnor和accumulate操作。此外，xnor和累加结果可以由敏感放大器快速读出其符号或由Flash ADC读出其多位量化值。该架构对MNIST数据集的能量效率为98.6TOPS/W，识别率为97.06%。

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引用次数: 0