Integration-The Vlsi Journal最新文献

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

In this research,we present a 64-point radix-$4^2$ pipelined Fast Fourier Transform(FFT) architecture which is area-efficient for an orthogonal frequency division multiplexing(OFDM) based IEEE 802.11a wireless Local area network(LAN) baseband. We adopt Multiple Delay Commutator(MDC) architecture for hardware implementation. The proposed 64-point FFT adopts a modified constant multiplier to compute complex multiplication in place of complex multipliers and to avoid read-only memory(ROM),which is used to store twiddle factor coefficients internally. The area of the design is reduced by using modified constant multiplier. The proposed radix-$4^2$ pipelined FFT architecture is synthesized using 45 nm CMOS technology with a supply voltage of 1.1 V. The proposed design occupies 15.31K total gates,dissipates 8.6 mW of power and the power delay product is 430$e^{-12}$.

Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.

This research paper proposes a novel robust high-performance power spectrum estimator, and bispactral power density analyzer that has outstanding capabilities in estimating noisy biomedical signal's power spectrum, and bispectrum. Biomedical signals usually are exposed to several sources of noises such as electrical noise from environmental noise from external sources, electrical equipment, and biological noise from the body. Therefore, accuracy and reliability are the most important feature of these systems in processing non-stationary biomedical signals. The proposed computationally-efficient architecture is based on a radix-8 memory-based 1024-point Blackman-Tuckey method power spectral density (PSD) estimator. The proposed nonparametric estimator uses a novel shared-resource CORDIC-Ⅱ unit to avoid multiplications in FFT computation, as well as filtering operations implemented in folded architectures. In order to merge two FFTs, the module uses bidirectional fractional delay filters to estimate half delay samples. By using modified safe-scaling, valid final output would be achieved, without any averaging operation. The proposed and competing designs are implemented on Artix-7 FPGA which is an ideal option for DSP applications. As final results demonstrate, the hardware has a remarkable capability in operating in short word-lengths which allows high-performance in low-power applications to compute the power spectrum and bicoherence of a vital signal.

Many human tracking methods by deep learning rely on powerful computing resources. For embedded platforms with limited resources, efficient use of resources is a priority. In this paper, we design an object detection and tracking system based on deep learning methods. We propose an efficient system with software and hardware design. We apply the framework of Vitis AI and its Deep Learning Processing Unit using a hardware/software co-design approach. This approach capitalizes on a higher-level acceleration design framework, where the convolutional models can be updated more flexibly and rapidly. This design approach not only provides a fast design flow but also has good performance in terms of throughput. We facilitate the design and accelerate the object detection model YOLO v3 to achieve higher throughput and energy efficiency. Our tracking method achieves a 1.27x improvement in processing speed with the addition of a single-object tracker. Our proposed human tracking methods can achieve better performance than the others in precision with the same test sequences.

Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by $1.1\times$ while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time.

Achieving matching constraints between various components is important in analog integrated circuit (IC) layout design, as it can reduce the impact of layout parasitics on the performance of IC. When automating analog integrated circuit layout design, identifying accurate matching constraints is an essential step before placement and routing. The matching relationship between devices strongly depends on circuit's topology and design expertise. This work focuses on differential circuits with various topologies and proposes a supervised learning framework that incorporates symmetry analysis. The heterogeneous multi-relationship graph representation is proposed to capture circuit's topology and extract matching constraints. Additionally, a symmetry analysis algorithm and filtering method based on matching levels are investigated to enhance the model's performance. The experimental results demonstrate that this work maintains a low false alarm rate and outperforms other matching constraint detection algorithms in terms of F₁ score and accuracy.

The effective monitoring of the grounding current of the core and clamp of the converter transformer can prevent partial overheating, gassing of oil, and other abnormal conditions caused by the grounding fault of the core and clamp, ensuring the safety and stability of the power system. At present, the main detection and diagnosis method is to use the clamp current meter to detect the effective value of the grounding current. However, due to the larger capacity, higher voltage level, more complex structure and electromagnetic field distribution of the converter transformer, there is no clear standard and detection diagnosis method. Firstly, this paper analyzes the causes of grounding current and related calculations. And the design of the monitoring system for the grounding current of the converter transformer core and clamp design of the hardware system for the grounding current of the converter transformer is studied and the design process of the main circuit is given. Secondly, aiming at the problem of amplitude measurement deviation and non-integer frequency of harmonic generated by the grounding current of the core and clamp, a harmonic current detection and analysis scheme based on four Blackman-harris algorithms and the specific design process are proposed. Third, a diagnostic method based on probabilistic neural network is proposed, and a software platform is built to display and diagnose the grounding current state according to it. Finally, a prototype was manufactured and experimental study was carried out to verify the correctness of the proposed scheme.

Adders are critical to the efficiency of arithmetic circuits in battery-powered electronic devices. This study demonstrates an 8-bit CLA (carry look-ahead adder) using single-phase ANT logic to increase the computation speed and reduce the power dissipation simultaneously. The single-phase ANT has no internal loop that optimizes the efficiency of the prior ANT. Utilizing a TSMC 40-nm technology, the proposed 8-bit CLA is fabricated. It attains the highest operating frequency of 3.2 GHz and the lowest normalized PDP (power delay product) by on-silicon measurement for 20 pF load.

Micro-LED technology offers numerous advantages, including high brightness, low power consumption, and superior color performance. However, driving micro LED displays requires complex control algorithms and high-speed data processing. To address these challenges, this paper presents the development of a real-time FPGA-based control system for a 68-inch 4K/60Hz micro-LED display. The objective of this project was to create a high-performance control system capable of driving the micro-LED display with precise color accuracy, supporting 10-bit color depth for enhanced color rendition. One crucial aspect of the system is color calibration, which ensures accurate color reproduction across the display, maintaining consistent and vibrant colors. By incorporating advanced color calibration techniques, the system achieves excellent color consistency and fidelity, providing a visually stunning viewing experience. Moreover, the system incorporates hot plug functionality, allowing for seamless reconnection of the display after Ethernet disconnection. This feature ensures uninterrupted operation and enhances user experience. In FPGA design, the proposed system demonstrates the feasibility and effectiveness of real-time control in driving micro-LED displays, offering improved color performance and reliable operation in various applications.