Integration-The Vlsi Journal最新文献_第6页

Review: Application and development of machine learning in semiconductor manufacturing for automated wafer map pattern recognition and classification 综述：机器学习在半导体制造中的应用与发展，用于自动化晶圆图模式识别与分类

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-11-07 DOI: 10.1016/j.vlsi.2025.102595

Wei Zhou, Guo-Xing Wang, Yongfu Li

The rapid development of the integrated circuit (IC) industry has continuously increased the complexity of IC manufacturing processes. Massive data analysis, exemplified by Wafer Map analysis, poses growing challenges for engineers and technicians in the field. With the ongoing advancement and maturation of machine learning in artificial intelligence, the application of machine learning algorithms for automated recognition and classification of wafer map patterns, known as Wafer Map Pattern Recognition and Classification, has emerged as a prominent research focus within the industry over the past decade. This paper conducts a systematic and comprehensive study, analyzing various machine learning algorithms applied to the problem of wafer map pattern recognition and classification. Starting from traditional machine learning techniques to neural networks and deep learning, the study identifies convolutional neural networks (CNNs) as one of the most effective approaches for addressing this problem currently. The research also highlights the continuous optimization of deep learning algorithms, focusing on improvements in architecture, depth, feature fusion, and the introduction of attention mechanisms to enhance the extraction of fine local features. Furthermore, the paper addresses issues related to data dependency, emphasizing innovations such as data augmentation, data generation, and semi-supervised learning models to mitigate the adverse effects of data scarcity and imbalance on deep learning training. These advancements aim to facilitate superior results for deep learning algorithms in solving the problem of wafer map pattern recognition and classification, thereby contributing to the field's ongoing progress.

集成电路产业的快速发展使集成电路制造工艺的复杂性不断增加。以Wafer Map分析为例的海量数据分析给该领域的工程师和技术人员带来了越来越大的挑战。随着人工智能中机器学习的不断发展和成熟，机器学习算法在晶圆图模式自动识别和分类中的应用，被称为晶圆图模式识别和分类，在过去十年中已经成为业界的一个突出的研究热点。本文进行了系统全面的研究，分析了应用于晶圆图模式识别与分类问题的各种机器学习算法。从传统的机器学习技术到神经网络和深度学习，本研究确定卷积神经网络（cnn）是目前解决这一问题最有效的方法之一。研究还强调了深度学习算法的不断优化，重点在架构、深度、特征融合等方面进行改进，并引入注意机制来增强对精细局部特征的提取。此外，本文还讨论了与数据依赖相关的问题，强调了数据增强、数据生成和半监督学习模型等创新，以减轻数据稀缺和不平衡对深度学习训练的不利影响。这些进步旨在促进深度学习算法在解决晶圆图模式识别和分类问题方面的卓越结果，从而促进该领域的持续发展。

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引用次数: 0

A progressive self-training semi-supervised model to enhance discontinuous change detection 一种渐进式自训练半监督模型，增强不连续变化检测

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-11-25 DOI: 10.1016/j.vlsi.2025.102609

Yamane Soma , Sakai Yuwa , Riaz-ul-haque Mian

Wafer-level performance has garnered significant attention within the industry. In this study, to achieve accurate modeling in a multisite testing environment, we explore the potential of incorporating Semi-Supervised Progressive Self-Training techniques into Gaussian process regression. Our experimental results, based on industrial production test data, show that the proposed progressive self-training Semi-Supervised Model outperforms two state-of-the-art methods: The Hierarchical Gaussian Process Regression (HGP) model and the Active Learning-Based Gaussian Process Regression (AHGP) model. Specifically, the proposed method achieved 29% and 80% less errors compared to the HGP model and cluster-based (Two Step) method respectively with the similar training data. Furthermore, it reduced testing costs by 50% while maintaining accuracy levels comparable to state-of-the-art active learning (AHGP) based models in a multi-site testing environment.

晶圆级性能在业界引起了极大的关注。在本研究中，为了在多站点测试环境中实现精确建模，我们探索了将半监督渐进式自我训练技术纳入高斯过程回归的潜力。基于工业生产测试数据的实验结果表明，所提出的渐进式自训练半监督模型优于两种最先进的方法：层次高斯过程回归（HGP）模型和基于主动学习的高斯过程回归（AHGP）模型。具体而言，在相似的训练数据下，与HGP模型和基于聚类（Two Step）的方法相比，该方法的误差分别降低了29%和80%。此外，它降低了50%的测试成本，同时在多站点测试环境中保持了与最先进的主动学习（AHGP）模型相当的精度水平。

引用次数: 0

Genetic algorithm-optimized fuzzy controller for the calibration of pipelined ADCs 基于遗传算法优化的模糊控制器对流水线adc的标定

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-29 DOI: 10.1016/j.vlsi.2025.102643

Luotian Wu, Honghui Deng, Jiashen Li, Muqi Li, Long Li, Yongsheng Yin

This paper proposes a genetic algorithm-optimized fuzzy controller for calibrating nonlinear errors in pipelined ADCs. Given the correspondence between the sub-ADC quantization codes and the errors in pipelined ADCs, this study employs a single-input single-output fuzzy controller to establish the mapping between the sub-ADC quantization codes and the errors. To fully utilize the fitting capabilities of the fuzzy controller, genetic algorithms are used to determine the optimal design parameters of the fuzzy controller. The developed single-input single-output fuzzy controller can fully achieve the fitting of nonlinear errors while maintaining a simple structure and low hardware implementation complexity. The optimal fuzzy controller is implemented on a Xilinx Kintex-7 FPGA and applied to calibrate a 14-bit 61 MS/s pipelined ADC. Experimental results demonstrate that after calibration with the optimized fuzzy controller, SNDR and SFDR are improved by 29.6 dB and 44.7 dB, respectively.

本文提出了一种遗传算法优化的模糊控制器，用于校正流水线adc中的非线性误差。考虑到流水线adc中子adc量化码与误差之间的对应关系，本研究采用单输入单输出模糊控制器建立子adc量化码与误差之间的映射关系。为了充分发挥模糊控制器的拟合能力，采用遗传算法确定模糊控制器的最优设计参数。所开发的单输入单输出模糊控制器在保持结构简单、硬件实现复杂度低的同时，能充分实现非线性误差的拟合。在Xilinx Kintex-7 FPGA上实现了最优模糊控制器，并应用于校准14位61 MS/s的流水线ADC。实验结果表明，经优化后的模糊控制器标定后，SNDR和SFDR分别提高了29.6 dB和44.7 dB。

引用次数: 0

Highly robust power efficient Full Adder and Full Subtractor CiM architecture using 10T SRAM cell 采用10T SRAM单元的高鲁棒高效全加法器和全减法器CiM架构

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-22 DOI: 10.1016/j.vlsi.2025.102639

Madan Mohan Sharma , Ananya Kabba , Kulbhushan Sharma , Pankaj Kumar

Von Neumann architectures suffer from data transfer bottlenecks which can be circumvented by performing computation directly inside memory arrays. This work presents a low-power 10T static random-access memory (SRAM) cell-based compute-in-memory (CiM) architecture designed with 18 nm FinFET technology in the Cadence Virtuoso tool, specifically implementing full adder (FA) and full subtractor (FS) operations. Compared to the 8T SRAM cell-based CiM architecture, the proposed architecture achieves 1.33x lower delay, 3.87x lower power, 5.82x better power-delay-product (PDP), and 8.8x better energy-delay-product (EDP) for performing FA operations. For FS operations, proposed 10T SRAM cell-based CiM architecture achieves 2.1x lower delay, 3.86x lower power, 8.3x better PDP, and 17.8x better EDP. The transistor count is reduced by 2.56x (126T–49T) for both FA and FS, minimizing area and design complexity. Monte Carlo simulations and process-temperature analyses further confirm, that the proposed architecture demonstrates greater robustness and stability under variations. The proposed architecture shows strong potential for use in complex neural networks.

冯·诺依曼架构受到数据传输瓶颈的困扰，这可以通过直接在存储器阵列内执行计算来规避。这项工作提出了一个低功耗的10T静态随机存取存储器（SRAM）基于单元的内存计算（CiM）架构，该架构采用Cadence Virtuoso工具中的18nm FinFET技术设计，具体实现了全加法器（FA）和全减法器（FS）操作。与基于8T SRAM单元的CiM架构相比，该架构在执行FA操作时延迟降低1.33倍，功耗降低3.87倍，功率延迟积（PDP）提高5.82倍，能量延迟积（EDP）提高8.8倍。对于FS操作，本文提出的基于10T SRAM单元的CiM架构实现了2.1倍的延迟降低，3.86倍的功耗降低，8.3倍的PDP提高，17.8倍的EDP提高。FA和FS的晶体管数量减少了2.56倍（126T-49T），最大限度地减少了面积和设计复杂性。蒙特卡罗模拟和过程温度分析进一步证实，所提出的体系结构在变化情况下具有更强的鲁棒性和稳定性。所提出的架构显示出在复杂神经网络中使用的强大潜力。

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引用次数: 0

Error expectation-driven design and energy optimization of approximate multipliers 误差预期驱动的近似乘法器设计与能量优化

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-11-28 DOI: 10.1016/j.vlsi.2025.102620

Yiqi Zhou , Yanghui Wu , Daying Sun , Shan Shen , Xiong Cheng , Li Li

Multipliers dominate energy consumption in digital signal processing (DSP) systems, while approximate multipliers offer accuracy-efficiency trade-offs, many existing designs suffer from suboptimal energy efficiency. This paper presents an error compensation algorithm that minimizes the global error expectation (EE). By analyzing the error distribution across approximate compressor columns, the algorithm determines optimal compensation positions to reduce EE while maintaining low hardware overhead. Based on this approach, two high energy efficiency approximate multipliers (HEAMs) are proposed: HEAM_M1, optimized for high accuracy, and HEAM_M2, which incorporates a newly designed 4-1 approximate compressor for ultra-low power applications. Compared to an exact multiplier, HEAM_M1 and HEAM_M2 achieve power-delay product (PDP) reductions of 32% and 54%, respectively. Moreover, compared to prior approximate multipliers with similar PDP levels, HEAM_M1 reduces NMED and MRED by 80% and 83%, while HEAM_M2 achieves reductions of 70% and 86%, respectively. Application-level evaluations on image processing and neural network tasks further demonstrate the effectiveness and robustness of the proposed designs.

在数字信号处理（DSP）系统中，乘法器主导着能源消耗，而近似乘法器提供了精度和效率的权衡，许多现有的设计都遭受着次优能源效率的困扰。提出了一种最小化全局误差期望（EE）的误差补偿算法。通过分析近似压缩机列之间的误差分布，该算法确定最佳补偿位置，以减少EE，同时保持较低的硬件开销。基于这种方法，提出了两种高能效近似乘法器（HEAMs）：针对高精度进行优化的HEAM_M1和包含新设计的用于超低功耗应用的4-1近似压缩机的HEAM_M2。与精确乘法器相比，HEAM_M1和HEAM_M2分别实现了32%和54%的功率延迟积（PDP）降低。此外，与先前具有相似PDP水平的近似乘数相比，HEAM_M1将NMED和MRED分别降低了80%和83%，而HEAM_M2分别降低了70%和86%。对图像处理和神经网络任务的应用级评估进一步证明了所提出设计的有效性和鲁棒性。

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引用次数: 0

A hybrid 16-bit Ripple Carry Adder with Doublet Transmission Gate-based Compressor for performance boost 混合16位纹波进位加法器与基于双态传输门的压缩器，用于性能提升

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-11-13 DOI: 10.1016/j.vlsi.2025.102594

Parthiv Bhau , Vijay Savani

This work introduces five novel 1-bit Transmission Gate Diffusion Input (TGDI)-based Hybrid Full Adders (HFAs), optimized for low power consumption and high-speed performance, outperforming recent architectures. Additionally, an innovative 16-bit Ripple Carry Adder (RCA) is developed, leveraging a Doublet Transmission Gate Adder-based Compressor Structure (DTGAC) to address driving strength challenges while achieving a low power-delay product and improved Figure of Merit (FoM). The proposed architectures are simulated using the Cadence Virtuoso tool with 18 nm Fin Field Effect Transistor (FinFET) technology and a nominal supply voltage of 0.8 V (±10%) at 27 °C. Post-layout simulations validate the real-world electrical behavior of the proposed circuits. Process corner and Monte Carlo analysis confirm the robustness of the designs. The results reveal a significant FoM improvement of 45.16%–59.3% for the proposed 1-bit TGDI-based HFAs compared to the 1-bit conventional mirror adder. Furthermore, the 16-bit RCA with DTGAC structures utilizing the proposed adders achieves a FoM enhancement of 19.94%–28.88% as compared to the DTGAC-based 16-bit RCA with a mirror adder. These advancements establish the proposed architectures as highly efficient and robust solutions for low-power, high-performance digital arithmetic circuits.

本研究介绍了五种新型的基于1位传输门扩散输入（TGDI）的混合全加法器（hfa），优化了低功耗和高速性能，优于最近的架构。此外，还开发了一种创新的16位纹波进位加法器（RCA），利用基于双态传输门加法器的压缩器结构（DTGAC）来解决驱动强度挑战，同时实现低功耗延迟产品和改进的性能图（FoM）。采用Cadence Virtuoso工具，采用18nm翅片场效应晶体管（FinFET）技术，在27°C下的标称电源电压为0.8 V（±10%）进行模拟。布局后仿真验证了所提出电路的真实电行为。过程角分析和蒙特卡罗分析证实了设计的鲁棒性。结果表明，与传统的1位镜像加法器相比，基于1位tgdi的HFAs的FoM显著提高了45.16%-59.3%。此外，与使用镜像加法器的基于DTGAC的16位RCA相比，使用所提加法器的具有DTGAC结构的16位RCA实现了19.94%-28.88%的FoM增强。这些进步使所提出的架构成为低功耗、高性能数字算术电路的高效、稳健的解决方案。

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引用次数: 0

Hardware efficient approximate activation functions for a Long-Short-Term Memory cell 长短期记忆单元的硬件高效近似激活函数

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-06 DOI: 10.1016/j.vlsi.2025.102627

R. Sindhu, V. Arunachalam

The activation functions (AF) such as

s i g m o i d (x)

and

\tanh (x)

are essential in a Long-Short Term Memory (LSTM) cell for time series classification using a Recurrent Neural Network (RNN). These AFs regulate the data flow effectively and optimize memory requirements in LSTM cells. Hardware realizations of these AFs are complex; consequently, approximation strategies must be adopted. The piece-wise linearization (PWL) method is appropriate for hardware implementations. A 7-segment PWL-based approximate

\tanh (x)

,

t (x_{8})

is proposed here. Employing a MATLAB-based error analysis, an optimum fixed-point data format (1-bit sign, 2-bit integer, 8-bit fraction) is chosen. The function

t (x_{8})

is implemented with parallel segment selection and two 10-bit adders using TSMC 65 nm technology libraries. This architecture uses 356.4 μm² area and consumes 230.7 μW at 1.67 GHz. Later, an approximate

s i g m o i d (x)

,

σ (x_{8})

is implemented using the

t (x_{8})

module with two shifters, a complement and an 11-bit adder. It uses a 462.4 μm² area and consumes 324.2 μW power at 1.25 GHz. An approximate LSTM cell with the proposed

t (x_{8})

and

σ (x_{8})

functions are modelled using Python 3.2 and tested with the Italian Parkinson's dataset. The approximate LSTM cell produces closer classification metrics with a maximum deviation of 0.21 % from the exact LSTM cell.

激活函数（AF）如sigmoid(x)和tanh(x)是使用递归神经网络（RNN）进行时间序列分类的长短期记忆（LSTM）单元中必不可少的。这些af有效地调节数据流并优化LSTM单元中的内存需求。这些af的硬件实现是复杂的；因此，必须采用近似策略。分段线性化（PWL）方法适用于硬件实现。这里提出了一个基于7段pwl的近似tanh(x), t（x8）。通过matlab误差分析，选择了最佳的定点数据格式（1位符号，2位整数，8位分数）。函数t（x8）是通过并行段选择和两个使用台积电65nm技术库的10位加法器实现的。该架构占用356.4 μm2的面积，1.67 GHz时功耗为230.7 μW。随后，使用t（x8）模块实现了一个近似的sigmoid(x), σ(x8)，其中包含两个移位器，一个补码和一个11位加法器。它占地462.4 μm2，在1.25 GHz时功耗为324.2 μW。使用Python 3.2对具有提议的t（x8）和σ(x8)函数的近似LSTM单元进行建模，并使用意大利帕金森病数据集进行测试。近似LSTM单元产生更接近的分类指标，与精确LSTM单元的最大偏差为0.21%。

{"title":"Hardware efficient approximate activation functions for a Long-Short-Term Memory cell","authors":"R. Sindhu, V. Arunachalam","doi":"10.1016/j.vlsi.2025.102627","DOIUrl":"10.1016/j.vlsi.2025.102627","url":null,"abstract":"<div><div>The activation functions (AF) such as <span><math><mrow><mi>s</mi><mi>i</mi><mi>g</mi><mi>m</mi><mi>o</mi><mi>i</mi><mi>d</mi><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span> and <span><math><mrow><mi>tanh</mi><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span> are essential in a Long-Short Term Memory (LSTM) cell for time series classification using a Recurrent Neural Network (RNN). These AFs regulate the data flow effectively and optimize memory requirements in LSTM cells. Hardware realizations of these AFs are complex; consequently, approximation strategies must be adopted. The piece-wise linearization (PWL) method is appropriate for hardware implementations. A 7-segment PWL-based approximate <span><math><mrow><mi>tanh</mi><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span>, <span><math><mrow><mi>t</mi><mrow><mo>(</mo><msub><mi>x</mi><mn>8</mn></msub><mo>)</mo></mrow></mrow></math></span> is proposed here. Employing a MATLAB-based error analysis, an optimum fixed-point data format (1-bit sign, 2-bit integer, 8-bit fraction) is chosen. The function <span><math><mrow><mi>t</mi><mrow><mo>(</mo><msub><mi>x</mi><mn>8</mn></msub><mo>)</mo></mrow></mrow></math></span> is implemented with parallel segment selection and two 10-bit adders using TSMC 65 nm technology libraries. This architecture uses 356.4 μm<sup>2</sup> area and consumes 230.7 μW at 1.67 GHz. Later, an approximate <span><math><mrow><mi>s</mi><mi>i</mi><mi>g</mi><mi>m</mi><mi>o</mi><mi>i</mi><mi>d</mi><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span>, <span><math><mrow><mi>σ</mi><mrow><mo>(</mo><msub><mi>x</mi><mn>8</mn></msub><mo>)</mo></mrow></mrow></math></span> is implemented using the <span><math><mrow><mi>t</mi><mrow><mo>(</mo><msub><mi>x</mi><mn>8</mn></msub><mo>)</mo></mrow></mrow></math></span> module with two shifters, a complement and an 11-bit adder. It uses a 462.4 μm<sup>2</sup> area and consumes 324.2 μW power at 1.25 GHz. An approximate LSTM cell with the proposed <span><math><mrow><mi>t</mi><mrow><mo>(</mo><msub><mi>x</mi><mn>8</mn></msub><mo>)</mo></mrow></mrow></math></span> and <span><math><mrow><mi>σ</mi><mrow><mo>(</mo><msub><mi>x</mi><mn>8</mn></msub><mo>)</mo></mrow></mrow></math></span> functions are modelled using Python 3.2 and tested with the Italian Parkinson's dataset. The approximate LSTM cell produces closer classification metrics with a maximum deviation of 0.21 % from the exact LSTM cell.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102627"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145737413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design insights for implementing a PRNG with fractional Lorenz system on ESP32 and FPGA 在ESP32和FPGA上实现带有分数洛伦兹系统的PRNG的设计见解

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-11-29 DOI: 10.1016/j.vlsi.2025.102622

Luis Gerardo de la Fraga , Esteban Tlelo-Cuautle

A Pseudo Random Number Generator (PRNG) produces a sequence whose randomness is evaluated by statistical tests like NIST and TestU01. The random sequences are deterministic and reproducible when using the same seed value. In this manner, and for cryptographic applications, the key size of a PRNG must be increased to resist brute force attacks. Henceforth, a fractional-order chaotic system, like the Lorenz one, is suitable to be used to design a PRNG, which implementation can be performed by using embedded devices such as the low-cost ESP32 (32-bit LX6 microprocessor) and field-programmable gate array (FPGA). To increase the throughput, the fractional Lorenz system is integrated with an approximated two steps Runge–Kutta method. An analysis in performed to find the domain of attraction for each state variable, and to verify that the PRNG produces non-correlated sequences. The hardware implementation is detailed by establishing the number of bits (or keys) required for the PRNG to guarantee its suitability for cryptographic applications. Finally, the hardware design of a PRNG using the fractional Lorenz system provides a throughput of 4.99 Mbits/s in the ESP32 platform, and 112.96 Mbits/s in the FPGA.

伪随机数生成器（PRNG）生成一个序列，其随机性由NIST和TestU01等统计测试评估。当使用相同的种子值时，随机序列具有确定性和可重复性。以这种方式，对于加密应用程序，必须增加PRNG的密钥大小以抵抗暴力攻击。因此，分数阶混沌系统，如洛伦兹系统，适合用于设计PRNG，其实现可以使用嵌入式器件，如低成本的ESP32（32位LX6微处理器）和现场可编程门阵列（FPGA）来实现。为了提高通量，将分数阶洛伦兹系统与近似两步龙格-库塔方法相结合。进行了分析，以找到每个状态变量的吸引域，并验证PRNG产生非相关序列。通过建立PRNG所需的比特（或密钥）数量来确保其适合加密应用程序，详细介绍了硬件实现。最后，采用分数阶洛伦兹系统的PRNG硬件设计在ESP32平台上的吞吐量为4.99 Mbits/s，在FPGA上的吞吐量为112.96 Mbits/s。

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引用次数: 0

Reinforcement learning-driven net order selection for efficient analog IC routing 基于强化学习的高效模拟IC路由网络选择

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-02 DOI: 10.1016/j.vlsi.2025.102623

Yong Zhang , Wen-Jie Li , Guo-Jing Ge , Jin-Qiao Wang , Bo-Wen Jia , Ning Xu

The A∗ algorithm is one of the most common analog integrated circuit (IC) routing techniques. As the number of nets increases, the routing order of this heuristic routing algorithm will affect the routing results immensely. Currently, artificial intelligence (AI) technologies are widely applied in IC physical design to accelerate layout design. In this paper, we propose a reinforcement model based on net order selection. We construct multi-channel images of routing data and extract features of the coordinates of routing pins through an attention mechanism. After training, the model outputs an optimized net order, which is then used to perform routing with a bidirectional A∗ algorithm, thereby improving both the speed and efficiency of the routing process. Experimental results on cases based on 130-nm and 180-nm processes show that the proposed method can achieve a 2.5 % reduction in wire length and a 3.7 % decrease in the number of vias compared to state-of-the-art methods for analog IC routing. In terms of computational efficiency, the bidirectional A∗ algorithm improves performance by 7.3 % over the unidirectional A∗ algorithm in decision-making scenarios and by 51.09 % in the path-planning process. Simulation results further demonstrate that, compared with manual and advanced automation methods, the overall performance of the layout achieved by our method aligns most closely with schematic performance.

A *算法是最常见的模拟集成电路（IC）路由技术之一。随着网络数量的增加，启发式路由算法的路由顺序将极大地影响路由结果。目前，人工智能（AI）技术被广泛应用于集成电路物理设计中，以加速版图设计。本文提出了一种基于网络顺序选择的强化模型。我们构建多通道路由数据图像，并通过注意机制提取路由引脚的坐标特征。经过训练后，该模型输出一个优化后的净顺序，然后使用双向a *算法执行路由，从而提高了路由过程的速度和效率。基于130纳米和180纳米工艺的实验结果表明，与最先进的模拟IC布线方法相比，所提出的方法可以减少2.5%的线长和3.7%的过孔数量。在计算效率方面，双向A∗算法在决策场景中的性能比单向A∗算法提高了7.3%，在路径规划过程中提高了51.09%。仿真结果进一步表明，与人工和先进的自动化方法相比，该方法实现的布局总体性能与原理图性能最接近。

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引用次数: 0

SARPAR: Systolic ARray Pallet-Integrated AcceleratoR for YOLO models on FPGA 基于FPGA的YOLO模型的收缩阵列托盘集成加速器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-16 DOI: 10.1016/j.vlsi.2025.102634

Sajad Eydivandi , Hakem Beitollahi

Efficient hardware acceleration is crucial for real-time object detection using YOLO models, particularly on FPGA-based platforms. This paper presents SARPAR, a high-performance, reconfigurable accelerator designed at the Register Transfer Level (RTL). Unlike previous works that rely on High-Level Synthesis (HLS), SARPAR fully optimizes FPGA resources by carefully managing dataflow, memory bandwidth, and computation parallelism. The architecture employs 16-bit fixed-point precision, a ping-pong buffering mechanism, and systolic computation for both normal and pointwise convolutions, significantly enhancing performance. Implemented on a Zynq UltraScale+ MPSoC, SARPAR operates at 300 MHz, achieving efficient feature map loading and processing while considering off-chip memory bandwidth. Our findings highlight a significant performance advantage over state-of-the-art YOLO accelerators, delivering a throughput of 1382 TOP/s while operating at a power consumption of 5.15 watts. Our approach achieves a 183.97% improvement in energy efficiency compared to existing YOLO accelerators developed on FPGA.

高效的硬件加速对于使用YOLO模型进行实时目标检测至关重要，特别是在基于fpga的平台上。本文介绍了一种高性能、可重构的寄存器传输级加速器SARPAR。与以前依赖于高级综合（HLS）的工作不同，SARPAR通过仔细管理数据流、内存带宽和计算并行性来充分优化FPGA资源。该架构采用16位定点精度、乒乓缓冲机制和常规卷积和点向卷积的收缩计算，显著提高了性能。SARPAR在Zynq UltraScale+ MPSoC上实现，工作频率为300 MHz，在考虑片外内存带宽的同时实现了高效的特征映射加载和处理。我们的研究结果突出了与最先进的YOLO加速器相比的显着性能优势，在5.15瓦的功耗下运行时提供1382 TOP/s的吞吐量。与现有FPGA上开发的YOLO加速器相比，我们的方法实现了183.97%的能效提升。

引用次数: 0