Integration-The Vlsi Journal最新文献

Since the concept of memristor was proposed, the construction of memristive hyperchaotic map has attracted wide attention. In this paper, a new 4D memristive hyperchaotic map is presented, investigating its characteristics such as multi$-$scroll attractors, coexisting attractors, offset boosting, and amplitude modulation. Regulated by variations in parameters, it exhibits extensive and continuous ranges of hyperchaotic behavior, overcoming the discontinuity issue in the chaotic range of traditional maps. Simulation results and numerical analyses demonstrate that it can generate diverse dynamic behaviors and possess superior chaotic properties. The National Institute of Standards and Technology (NIST) test reveals that the generated sequences display a high degree of randomness. A digital hardware platform based on microcomputer is established to verify the physical feasibility. Lastly, its successful application in the development of image encryption algorithm underscores the immense potential in the field of information security.

In this paper, we proposed a fully floating memristor emulator with long-term memory characteristics. The circuit comprises operational amplifiers and an analog switch. Switching between incremental and decremental modes is easily achieved by changing the polarity of the input signal. The key feature of the emulator is its long-term memory, made possible by the switch and voltage follower. The correctness of the derived formula is verified using Matlab, and the emulator's pinched hysteresis loop and non-volatility are assessed using LTspice. Additionally, an experimental platform was constructed for physical testing, with the physical results showing consistency with the simulations. Finally, the proposed emulator was applied to a simple read-write circuit, demonstrating its practical applicability.

In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a ‘digital fingerprint’ for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a ‘weak’ PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness.

An electronic circuit capable of performing the functions of all three memelements through simple configuration adjustments, known as a universal memelement emulator, addresses significant issues regarding the size and power consumption associated with integrated chips. This study aims to develop such a universal memelement emulator with configurable architecture requiring only few changes to switch into desired memelement emulator. The designed structure is based on only single active element known as the FTFNTA (Four Terminal Floating Nullor Transconductance Amplifier). The proposed circuit, in addition to a single FTFNTA, incorporates only four passive elements and three switches. Through the manipulation of these switches, the universal emulator can be configured to emulate three distinct memelements: flux-controlled memristor (FCMR), flux-controlled meminductor (FCMI), and charge-controlled memcapacitor (CCMC). The non-ideal analysis was conducted after considering the deviated parameters of the FTFNTA and associated parasitic elements and resultant behaviour is discussed. Simulation results conducted in the PSPICE environment validate the functionality of the realized memelements. Furthermore, verification of the concept is performed by implementing the FTFNTA-based circuit using commercially available ICs, specifically LM13700 and AD844, with the results discussed accordingly. The working of the realized memristor has also been verified by utilizing the proposed emulator (tuned as a memristor) in an associative learning circuit. Finally, the proposed emulator is validated experimentally using the physical ICs based breadboard implementation.

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

In this research,we present a 64-point radix-$4^2$ pipelined Fast Fourier Transform(FFT) architecture which is area-efficient for an orthogonal frequency division multiplexing(OFDM) based IEEE 802.11a wireless Local area network(LAN) baseband. We adopt Multiple Delay Commutator(MDC) architecture for hardware implementation. The proposed 64-point FFT adopts a modified constant multiplier to compute complex multiplication in place of complex multipliers and to avoid read-only memory(ROM),which is used to store twiddle factor coefficients internally. The area of the design is reduced by using modified constant multiplier. The proposed radix-$4^2$ pipelined FFT architecture is synthesized using 45 nm CMOS technology with a supply voltage of 1.1 V. The proposed design occupies 15.31K total gates,dissipates 8.6 mW of power and the power delay product is 430$e^{-12}$.

Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.

This research paper proposes a novel robust high-performance power spectrum estimator, and bispactral power density analyzer that has outstanding capabilities in estimating noisy biomedical signal's power spectrum, and bispectrum. Biomedical signals usually are exposed to several sources of noises such as electrical noise from environmental noise from external sources, electrical equipment, and biological noise from the body. Therefore, accuracy and reliability are the most important feature of these systems in processing non-stationary biomedical signals. The proposed computationally-efficient architecture is based on a radix-8 memory-based 1024-point Blackman-Tuckey method power spectral density (PSD) estimator. The proposed nonparametric estimator uses a novel shared-resource CORDIC-Ⅱ unit to avoid multiplications in FFT computation, as well as filtering operations implemented in folded architectures. In order to merge two FFTs, the module uses bidirectional fractional delay filters to estimate half delay samples. By using modified safe-scaling, valid final output would be achieved, without any averaging operation. The proposed and competing designs are implemented on Artix-7 FPGA which is an ideal option for DSP applications. As final results demonstrate, the hardware has a remarkable capability in operating in short word-lengths which allows high-performance in low-power applications to compute the power spectrum and bicoherence of a vital signal.

Many human tracking methods by deep learning rely on powerful computing resources. For embedded platforms with limited resources, efficient use of resources is a priority. In this paper, we design an object detection and tracking system based on deep learning methods. We propose an efficient system with software and hardware design. We apply the framework of Vitis AI and its Deep Learning Processing Unit using a hardware/software co-design approach. This approach capitalizes on a higher-level acceleration design framework, where the convolutional models can be updated more flexibly and rapidly. This design approach not only provides a fast design flow but also has good performance in terms of throughput. We facilitate the design and accelerate the object detection model YOLO v3 to achieve higher throughput and energy efficiency. Our tracking method achieves a 1.27x improvement in processing speed with the addition of a single-object tracker. Our proposed human tracking methods can achieve better performance than the others in precision with the same test sequences.

Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by $1.1\times$ while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time.