Pub Date : 2026-05-01Epub Date: 2026-01-29DOI: 10.1016/j.vlsi.2026.102671
Peng Wei , Yunhao Hu , Zhuomin Chai , Hongyu Zhao , Wei Liu
This paper presents MARS-Place, a novel multi-stage alignment-refined strategy for automated PCB placement and routing optimization. The proposed framework consists of three key stages: Initial Placement, Detailed Placement, and Fine-tuning, each designed to address specific challenges and enhance placement quality. In the Fine-tuning stage, a force-based alignment mechanism is introduced, leveraging both attractive and repulsive forces to improve pad alignment within nets, thereby reducing routing complexity and unnecessary bends. Furthermore, a classification-based initial placement and an adaptive exploration radius strategy are integrated to accelerate convergence while maintaining high solution quality. Experimental results on open-source benchmarks demonstrate that MARS-Place outperforms state-of-the-art PCB placement methods, achieving an average 5%–25% reduction in wirelength, 12%–36% reduction in via count, and 8%–23% reduction in the number of routing segments, leading to improved signal integrity and routing efficiency.
{"title":"MARS-Place: Multi-stage alignment-refined strategy for PCB placement and routing optimization","authors":"Peng Wei , Yunhao Hu , Zhuomin Chai , Hongyu Zhao , Wei Liu","doi":"10.1016/j.vlsi.2026.102671","DOIUrl":"10.1016/j.vlsi.2026.102671","url":null,"abstract":"<div><div>This paper presents MARS-Place, a novel multi-stage alignment-refined strategy for automated PCB placement and routing optimization. The proposed framework consists of three key stages: Initial Placement, Detailed Placement, and Fine-tuning, each designed to address specific challenges and enhance placement quality. In the Fine-tuning stage, a force-based alignment mechanism is introduced, leveraging both attractive and repulsive forces to improve pad alignment within nets, thereby reducing routing complexity and unnecessary bends. Furthermore, a classification-based initial placement and an adaptive exploration radius strategy are integrated to accelerate convergence while maintaining high solution quality. Experimental results on open-source benchmarks demonstrate that MARS-Place outperforms state-of-the-art PCB placement methods, achieving an average 5%–25% reduction in wirelength, 12%–36% reduction in via count, and 8%–23% reduction in the number of routing segments, leading to improved signal integrity and routing efficiency.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102671"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-02-07DOI: 10.1016/j.vlsi.2026.102679
Sujeet Kumar, Kailash Chandra Ray
The use of RISC-V-based soft processors in space technology is rapidly expanding, owing to their modular architecture, open instruction set, and flexible system integration capabilities. However, Single-Event Multiple Upsets (SEMUs) due to radiation effects pose critical reliability challenges, as faults in the instruction decoder will abort execution and cause system failures. Hence, the paper presents a new Full-Coverage Multi-Bit Fault-Tolerant Instruction Decoder (FCMFID) design that enhances the reliability of a pipeline RV32I processor core by providing protection to the full Instruction decoder, including IF/ID and ID/EX pipeline registers. The design employs nibble-level parity checking to correct single-bit faults within each nibble and mitigate multi-bit errors through selective nibble replacement. The proposed FCMFID architecture is implemented in Verilog HDL and prototyped on a Xilinx Artix-7 FPGA by employing Fault injection using the Xilinx Soft Error Mitigation (SEM) IP to validate its resilience at the silicon level. In comparison to an unprotected design, the results show that FCMFID improves fault tolerance by 99.36%. It also reduces power consumption by 30.05% and LUT overhead by 145.53% as compared to TMR and is suited for RISC-V-based soft processors in resource-constrained space applications.
{"title":"FCMFID: A Full Coverage Multi-bit Fault-Tolerant Instruction Decoder for RISC-V based softcore","authors":"Sujeet Kumar, Kailash Chandra Ray","doi":"10.1016/j.vlsi.2026.102679","DOIUrl":"10.1016/j.vlsi.2026.102679","url":null,"abstract":"<div><div>The use of RISC-V-based soft processors in space technology is rapidly expanding, owing to their modular architecture, open instruction set, and flexible system integration capabilities. However, Single-Event Multiple Upsets (SEMUs) due to radiation effects pose critical reliability challenges, as faults in the instruction decoder will abort execution and cause system failures. Hence, the paper presents a new Full-Coverage Multi-Bit Fault-Tolerant Instruction Decoder (FCMFID) design that enhances the reliability of a pipeline RV32I processor core by providing protection to the full Instruction decoder, including IF/ID and ID/EX pipeline registers. The design employs nibble-level parity checking to correct single-bit faults within each nibble and mitigate multi-bit errors through selective nibble replacement. The proposed FCMFID architecture is implemented in Verilog HDL and prototyped on a Xilinx Artix-7 FPGA by employing Fault injection using the Xilinx Soft Error Mitigation (SEM) IP to validate its resilience at the silicon level. In comparison to an unprotected design, the results show that FCMFID improves fault tolerance by 99.36%. It also reduces power consumption by 30.05% and LUT overhead by 145.53% as compared to TMR and is suited for RISC-V-based soft processors in resource-constrained space applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102679"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-02-07DOI: 10.1016/j.vlsi.2026.102680
Jinghe Wang , Zhiyuan Pan , Nengyuan Sun , Zhaoyi Niu , Wenrui Liu , Jiafeng Cheng , Kai Shi , Jianghong Li , Jiaqi Wang , Jiawei Zhang , Linhan Wang , Kangning Song , Yuzhu Wu , Weize Yu
In this paper, a high-performance application-specific integrated circuit (ASIC) design of CRYSTALS-Kyber is proposed for accelerating post-quantum cryptography (PQC) applications. Unlike a regular Barrett modular-reduction (BMR) that includes only a single modulus, two different moduli are utilized in the new BMR architecture for accelerating the number-theoretic transform (NTT) module within the Kyber algorithm. To protect against side-channel attacks (SCAs), the two moduli within the proposed BMR are randomized to introduce uncertainty in the power profile of the Kyber algorithm. In addition, in order to acquire the optimum power/area/performance/security trade-off values for the proposed CRYSTALS-Kyber, novel convex optimization models are established to investigate the impact of random modulus distributions on the overall ASIC design. As shown in the results, the proposed random modular-reduction (RMR)-based Kyber engine is capable of achieving a performance (an area of 1.63 mm) with a minimum measurement-to-disclosure (MTD) enhancement of 454.5x against 1st-order SCAs, under the synthesis of SMIC 55 nm process design kits (PDK).
{"title":"A random modular-reduction (RMR)-based ASIC design of CRYSTALS-Kyber engine against side-channel attacks","authors":"Jinghe Wang , Zhiyuan Pan , Nengyuan Sun , Zhaoyi Niu , Wenrui Liu , Jiafeng Cheng , Kai Shi , Jianghong Li , Jiaqi Wang , Jiawei Zhang , Linhan Wang , Kangning Song , Yuzhu Wu , Weize Yu","doi":"10.1016/j.vlsi.2026.102680","DOIUrl":"10.1016/j.vlsi.2026.102680","url":null,"abstract":"<div><div>In this paper, a high-performance application-specific integrated circuit (ASIC) design of CRYSTALS-Kyber is proposed for accelerating post-quantum cryptography (PQC) applications. Unlike a regular Barrett modular-reduction (BMR) that includes only a single modulus, two different moduli are utilized in the new BMR architecture for accelerating the number-theoretic transform (NTT) module within the Kyber algorithm. To protect against side-channel attacks (SCAs), the two moduli within the proposed BMR are randomized to introduce uncertainty in the power profile of the Kyber algorithm. In addition, in order to acquire the optimum power/area/performance/security trade-off values for the proposed CRYSTALS-Kyber, novel convex optimization models are established to investigate the impact of random modulus distributions on the overall ASIC design. As shown in the results, the proposed random modular-reduction (RMR)-based Kyber engine is capable of achieving a <span><math><mrow><mn>92</mn><mo>.</mo><mn>65</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> performance (an area of 1.63 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>) with a minimum measurement-to-disclosure (MTD) enhancement of 454.5x against 1st-order SCAs, under the synthesis of SMIC 55 nm process design kits (PDK).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102680"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-29DOI: 10.1016/j.vlsi.2026.102672
K.I. RaviKumar , K. Anusha , C. Kalal Vijayalaxmi , T. Kshitija , M. Ayesha Siddiqa Khanum
Very Large Scale Integration (VLSI) design has become a critical aspect of high-speed chip communications due to its simple, efficient register and data access, but these systems can be vulnerable to security attacks, leading to excessive traffic and slow performance. Therefore, the SRAM control unit uses a novel Armadillo Catboost Security Control (ACSC) design. First, an SRAM block was built with the controller's associated facilities. Then, the ACSC design was created using the Armadillo fitness traits, with the addition of CatBoost machine learning capabilities to mitigate threats. When many users are communicating within a large dataset, the ACSC protects the system from vulnerabilities. Key performance indicators are assessed and compared with existing systems, including processing time, secrecy score, memory usage, traffic rate, power consumption, delay, and bit error rate (BER). The developed model is validated using several metrics, and it achieves a power consumption of 2.98 mW, a memory usage of 7446.96 MB, a BER of 0.00276 %, a delay of 1.97 ns, a confidentiality score of 95 %, and a processing time of 59.21s. This model has superior performance, security, and operational performance compared to existing systems.
{"title":"Enhanced security for static random access memory with armadillo Catboost","authors":"K.I. RaviKumar , K. Anusha , C. Kalal Vijayalaxmi , T. Kshitija , M. Ayesha Siddiqa Khanum","doi":"10.1016/j.vlsi.2026.102672","DOIUrl":"10.1016/j.vlsi.2026.102672","url":null,"abstract":"<div><div>Very Large Scale Integration (VLSI) design has become a critical aspect of high-speed chip communications due to its simple, efficient register and data access, but these systems can be vulnerable to security attacks, leading to excessive traffic and slow performance. Therefore, the SRAM control unit uses a novel Armadillo Catboost Security Control (ACSC) design. First, an SRAM block was built with the controller's associated facilities. Then, the ACSC design was created using the Armadillo fitness traits, with the addition of CatBoost machine learning capabilities to mitigate threats. When many users are communicating within a large dataset, the ACSC protects the system from vulnerabilities. Key performance indicators are assessed and compared with existing systems, including processing time, secrecy score, memory usage, traffic rate, power consumption, delay, and bit error rate (BER). The developed model is validated using several metrics, and it achieves a power consumption of 2.98 mW, a memory usage of 7446.96 MB, a BER of 0.00276 %, a delay of 1.97 ns, a confidentiality score of 95 %, and a processing time of 59.21s. This model has superior performance, security, and operational performance compared to existing systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102672"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose two temperature-adaptive assist circuits aimed to ensure the stability of the Compute-In-Memory (CIM) system across a wide temperature range. Additionally, we propose an innovative quantization scheme to enhance the accuracy of quantization results. The two assist circuitry variants are designed to target the discharge transistors in bitcell operating in the saturation (7T) and subthreshold (8T) regions during Multiplication and Accumulation (MAC) operations, while the quantization scheme further compensates for temperature sensitivity and enhances resilience to process corner variations. Simulation results demonstrate that the maximum RBL voltage drift is reduced by at least 80% (up to 98%) across multiple process corners when employing the assist circuitry. After integrated with the quantization scheme, the quantization accuracy of maximum MAC values is improved by 7.6 for 8T CIM and 4.5 for 7T CIM, respectively.
{"title":"MTJ-back-gate SRAM CIM with replica quantization for temperature robust","authors":"Yongliang Zhou, Chengxing Dai, Yufei He, Xiulong Wu, Chunyu Peng","doi":"10.1016/j.vlsi.2026.102682","DOIUrl":"10.1016/j.vlsi.2026.102682","url":null,"abstract":"<div><div>In this paper, we propose two temperature-adaptive assist circuits aimed to ensure the stability of the Compute-In-Memory (CIM) system across a wide temperature range. Additionally, we propose an innovative quantization scheme to enhance the accuracy of quantization results. The two assist circuitry variants are designed to target the discharge transistors in bitcell operating in the saturation (7T) and subthreshold (8T) regions during Multiplication and Accumulation (MAC) operations, while the quantization scheme further compensates for temperature sensitivity and enhances resilience to process corner variations. Simulation results demonstrate that the maximum RBL voltage drift is reduced by at least 80% (up to 98%) across multiple process corners when employing the assist circuitry. After integrated with the quantization scheme, the quantization accuracy of maximum MAC values is improved by 7.6<span><math><mo>×</mo></math></span> for 8T CIM and 4.5<span><math><mo>×</mo></math></span> for 7T CIM, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102682"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-12DOI: 10.1016/j.vlsi.2026.102663
Yuanfa Ji , Haihui Zhang , Xiyan Sun , Furong Jiang , Qiang Fu
With the continuous increase in chip integration density and reliability requirements, test data volume has grown significantly. At the same time, limitations of automatic test equipment in terms of physical I/O channel count, memory capacity, and data transmission bandwidth have further raised test costs. To address these challenges, this paper proposes a test data compression method based on sliding-window encoding. This approach identifies repeated sequences in the data to be encoded and replaces them with shorter codewords, thereby achieving effective compression. Furthermore, a match length reuse mechanism is introduced, which considerably enhances both codeword utilization efficiency and compression performance. Additionally, this paper systematically analyzes the impact of encoding parameters on the compression ratio, optimizes the encoding scheme considering hardware overhead, and designs a corresponding decompression architecture. Experimental results show that the proposed method achieves an average compression ratio of 66.86% on ISCAS’89 benchmark circuits. This provides an innovative and practical solution for test data compression.
{"title":"A test data compression method based on sliding-window encoding and matching length reuse","authors":"Yuanfa Ji , Haihui Zhang , Xiyan Sun , Furong Jiang , Qiang Fu","doi":"10.1016/j.vlsi.2026.102663","DOIUrl":"10.1016/j.vlsi.2026.102663","url":null,"abstract":"<div><div>With the continuous increase in chip integration density and reliability requirements, test data volume has grown significantly. At the same time, limitations of automatic test equipment in terms of physical I/O channel count, memory capacity, and data transmission bandwidth have further raised test costs. To address these challenges, this paper proposes a test data compression method based on sliding-window encoding. This approach identifies repeated sequences in the data to be encoded and replaces them with shorter codewords, thereby achieving effective compression. Furthermore, a match length reuse mechanism is introduced, which considerably enhances both codeword utilization efficiency and compression performance. Additionally, this paper systematically analyzes the impact of encoding parameters on the compression ratio, optimizes the encoding scheme considering hardware overhead, and designs a corresponding decompression architecture. Experimental results show that the proposed method achieves an average compression ratio of 66.86% on ISCAS’89 benchmark circuits. This provides an innovative and practical solution for test data compression.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102663"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-06DOI: 10.1016/j.vlsi.2026.102653
Viet-Thanh Pham , Victor Kamdoum Tamba , Luigi Fortuna
Non-equilibrium oscillators are special because of their hidden attractors. This work introduces a non-equilibrium oscillator, which is implemented using a reduced number of resistors. Its implementation requires a diode instead of analog multipliers. Our oscillator is easily realized with common off-the-shelf components in the laboratory, making it suitable for educational purposes. Dynamics of the oscillator are investigated to present its special features. In addition, the usage of the oscillator for generating random signal is presented illustrating its possible application.
{"title":"Non-equilibrium oscillator with a diode: Dynamics and application","authors":"Viet-Thanh Pham , Victor Kamdoum Tamba , Luigi Fortuna","doi":"10.1016/j.vlsi.2026.102653","DOIUrl":"10.1016/j.vlsi.2026.102653","url":null,"abstract":"<div><div>Non-equilibrium oscillators are special because of their hidden attractors. This work introduces a non-equilibrium oscillator, which is implemented using a reduced number of resistors. Its implementation requires a diode instead of analog multipliers. Our oscillator is easily realized with common off-the-shelf components in the laboratory, making it suitable for educational purposes. Dynamics of the oscillator are investigated to present its special features. In addition, the usage of the oscillator for generating random signal is presented illustrating its possible application.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102653"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-02DOI: 10.1016/j.vlsi.2025.102644
Yongliang Zhou , Yingxue Sun , Beibei Zhang , Wangyong Si , Jingxue Zhong , Weizhe Tan , Chunyu Peng , Xiulong Wu
This article primarily investigates the temperature characteristics of magnetic tunnel junctions (MTJ) and exploits their tunnel magneto-resistance (TMR) effect to compensate for temperature-induced mismatches arising from CMOS temperature variations. In this work, the beta-multiplier reference and Kuijk bandgap reference are simulated on the 28 nm node. The proposed designs achieve improvements in temperature stability while maintaining low-voltage operation. Specifically, the circuit was redesigned based on a beta-multiplier voltage-reference topology in which MTJs replace resistors, with the explicit aim of strengthening the negative-feedback loop. As a result, stable operation is achieved at a minimum supply voltage of 0.6 V over the temperature range 0 °C to 110 °C. The reference voltage exhibits a line sensitivity of 0.57%/V, a temperature coefficient of 35.2 ppm/°C, and a nominal output of 441.6 mV. Drawing on MTJ-based compensation techniques, the modified Kuijk bandgap reference replaces the BJT-based temperature-compensation element with an MTJ device, yielding a reference voltage with a line sensitivity of 0.096%/V, a temperature coefficient of 11.8 ppm/°C, and a nominal output of 1.65 V. Beyond the electrical benefits, the use of MTJs enables vertical integration of the compensating elements, delivering substantial area savings — approximately 50% reduction for the beta-multiplier implementation and about 66.5% for the modified bandgap — thereby producing a more compact and competitive solution for high-performance precision voltage references.
{"title":"Low-temperature-drift voltage reference design using magnetic tunnel junctions","authors":"Yongliang Zhou , Yingxue Sun , Beibei Zhang , Wangyong Si , Jingxue Zhong , Weizhe Tan , Chunyu Peng , Xiulong Wu","doi":"10.1016/j.vlsi.2025.102644","DOIUrl":"10.1016/j.vlsi.2025.102644","url":null,"abstract":"<div><div>This article primarily investigates the temperature characteristics of magnetic tunnel junctions (MTJ) and exploits their tunnel magneto-resistance (TMR) effect to compensate for temperature-induced mismatches arising from CMOS temperature variations. In this work, the beta-multiplier reference and Kuijk bandgap reference are simulated on the 28 nm node. The proposed designs achieve improvements in temperature stability while maintaining low-voltage operation. Specifically, the circuit was redesigned based on a beta-multiplier voltage-reference topology in which MTJs replace resistors, with the explicit aim of strengthening the negative-feedback loop. As a result, stable operation is achieved at a minimum supply voltage of 0.6 V over the temperature range 0 °C to 110 °C. The reference voltage exhibits a line sensitivity of 0.57%/V, a temperature coefficient of 35.2 ppm/°C, and a nominal output of 441.6 mV. Drawing on MTJ-based compensation techniques, the modified Kuijk bandgap reference replaces the BJT-based temperature-compensation element with an MTJ device, yielding a reference voltage with a line sensitivity of 0.096%/V, a temperature coefficient of 11.8 ppm/°C, and a nominal output of 1.65 V. Beyond the electrical benefits, the use of MTJs enables vertical integration of the compensating elements, delivering substantial area savings — approximately 50% reduction for the beta-multiplier implementation and about 66.5% for the modified bandgap — thereby producing a more compact and competitive solution for high-performance precision voltage references.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102644"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-09DOI: 10.1016/j.vlsi.2026.102661
Aydin Tarik Zengin
This paper introduces a high-precision, FPGA-based analog signal generator that fundamentally departs from conventional, template-based approaches by mathematically synthesizing each analog pulse in real time. Unlike systems relying on pre-recorded or pre-defined waveform memories, the proposed architecture dynamically computes every sample of double-exponential pulses on-the-fly within reconfigurable FPGA logic. Leveraging the AMD Xilinx ZYNQ 7010 SoC, the system ensures that every pulse is uniquely tailored on demand, with full control over rise time, decay time, amplitude, and pile-up effects. This real-time, parameter-driven signal generation enables the accurate emulation of complex detector signals, including overlapping events and user-defined spectral distributions, while guaranteeing deterministic timing and minimal processor overhead.
Experimental results demonstrate that the platform can precisely reproduce the analog characteristics and statistical features of diverse scintillation detector responses, outperforming commercial solutions limited to simple exponential or static waveform outputs. The modular, runtime-reconfigurable design supports dual-channel, high-fidelity operation and can be extended to broader application domains, including medical signal emulation and telecommunication waveform synthesis. By eliminating dependence on static pulse templates, this work establishes a new standard for flexibility, realism, and accuracy in embedded hardware testing and detector development.
{"title":"A method for mathematically synthesizing double-exponential signal generation on-the-fly on FPGA and its evaluation","authors":"Aydin Tarik Zengin","doi":"10.1016/j.vlsi.2026.102661","DOIUrl":"10.1016/j.vlsi.2026.102661","url":null,"abstract":"<div><div>This paper introduces a high-precision, FPGA-based analog signal generator that fundamentally departs from conventional, template-based approaches by mathematically synthesizing each analog pulse in real time. Unlike systems relying on pre-recorded or pre-defined waveform memories, the proposed architecture dynamically computes every sample of double-exponential pulses on-the-fly within reconfigurable FPGA logic. Leveraging the AMD Xilinx ZYNQ 7010 SoC, the system ensures that every pulse is uniquely tailored on demand, with full control over rise time, decay time, amplitude, and pile-up effects. This real-time, parameter-driven signal generation enables the accurate emulation of complex detector signals, including overlapping events and user-defined spectral distributions, while guaranteeing deterministic timing and minimal processor overhead.</div><div>Experimental results demonstrate that the platform can precisely reproduce the analog characteristics and statistical features of diverse scintillation detector responses, outperforming commercial solutions limited to simple exponential or static waveform outputs. The modular, runtime-reconfigurable design supports dual-channel, high-fidelity operation and can be extended to broader application domains, including medical signal emulation and telecommunication waveform synthesis. By eliminating dependence on static pulse templates, this work establishes a new standard for flexibility, realism, and accuracy in embedded hardware testing and detector development.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102661"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-03DOI: 10.1016/j.vlsi.2025.102640
Jinlin Chen , Huaguo Liang , Yingchun Lu , Liang Yao
With the rise of the internet and electronic devices, the security of network information has garnered increasing attention. True Random Number Generators (TRNGs) play an increasingly important role in information security. TRNG entropy sources based on Ring Oscillator (RO) have attracted significant interest due to their simple circuit design and ease of implementation on FPGAs. However, most existing works suffer from high hardware overhead. A novel ultra-lightweight TRNG based on multi-mode switching of RO-like rings is proposed in this work, which can be automatically placed and routed on the Xilinx Artix-7 FPGA, using only 10 LUTs and 2 D flip-flops. The randomness of the entropy source is analyzed through a mathematical model, proving that the output sequence is an unordered random bit string under any circumstances. The output sequence of the TRNG successfully passed various tests, including autocorrelation tests, NIST SP800-22, NIST SP800-90B, AIS-31, and TESTU01, with favorable results.
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