Integration-The Vlsi Journal最新文献

The paper presents an approach to increase the performance in terms of input and output resistance of a low voltage flipped voltage follower (FVF) based current mirror. The proposed technique consists of substituting the main output transistor with a network of transistors in a feedback arrangement, designed to improve the output resistance. Furthermore, a low saturation onset transistor approach is used to improve the performance. Such an approach also helped in reducing the input resistance of the current mirror, which ranges in ohms. A wide current range of up to 1 mA is achieved at a minimal current transfer error of 0.38 %. This feedback mechanism-based current mirror exhibits an output resistance of 29.61 GΩ, an input resistance of 30.45 Ω, and a bandwidth of 1.464 GHz. The proposed current mirror runs on ±0.5 V supply voltage. The robustness of the proposed circuit is evaluated through process corner analysis, temperature mismatch assessment, and Monte-Carlo simulations. The performance characteristics of the proposed current mirror have been validated and simulated using Cadence Virtuoso and Spectre simulations on 0.18 μm UMC technology. The validation process included both pre-layout and post-layout simulation results.

A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB-OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC $0.18\mu m$ process. The simulated results demonstrate that the proposed LPFBR-OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB-OTA under the condition that LCMFB resistors are increased by a factor of 10.

An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.

As chip designs grow in complexity, the optical proximity correction (OPC) process becomes increasingly time-consuming. As a result, pattern search technology is becoming a foundation stone of many tasks for manufacturing, such as lithography simulation, hotspot detection, mask optimization, and so on. The most difficult challenge of pattern search is to locate clips by specific patterns within the layout accurately and efficiently. In this paper, we present a generalized pattern search method capable in diverse scenarios, including patterns with hollow shapes, shifting edges, and multi-layer situations. Experimental results show that our method outperforms commercial tools in pattern locating accuracy and handling search problems involving complex patterns which is not directly support by commercial tools yet.

In this paper, the circuit simulation is achieved by the established Hindmarsh-Rose (HR) neuron model and the system is applied in projection synchronization. The chaotic behaviors of the neural network model are analyzed using bifurcation diagrams, Lyapunov exponents spectra, phase diagrams and time series diagrams. The dynamics analysis of the neuron model shows a variety of firing behaviors and extreme multistability behavior. The model is then simulated through circuit multisim to demonstrate the possibility in a physical sense. Finally, synchronization is induced to the memristive neural system through projection control, and the experimental results show that the model embodies a good synchronization effect in the process of projection synchronization, which helps to improve the security of signal transmission and the confidentiality of the system, and lays the foundation for the secure communication afterwards.