Integration-The Vlsi Journal最新文献

In recent years, the application of deep learning (DL) models has sparked considerable interest in timing prediction within the place-and-route (P&R) flow of IC chip design. Specifically, at the pre-route stage, an accurate prediction of post-route timing is challenging due to the lack of sufficient physical information. However, achieving precise timing prediction significantly accelerates the design closure process, saving considerable time and effort. In this work, we propose pre-route timing prediction and optimization framework with graph neural network (GNN) models combined with convolution neural network (CNN). Our framework is divided into two main stages, each of which is further subdivided into smaller steps. Precisely, our GNN-driven arc delay/slew prediction model is divided into two levels: in level-1, it predicts net resistance (net R) and net capacitance (net C) using GNN while the arc length is predicted using CNN. These predictions are hierarchically passed on to level-2 where delay/slew is estimated with our GNN based prediction model. The timing optimization model utilizes the precise delay/slew predictions obtained from the GNN-driven prediction model to accurately set the path margin during the timing optimization stage. This approach effectively reduces unnecessary turn-around iterations in the commercial EDA tools. Experimental results show that by using our proposed framework in P&R, we are able to improve the pre-route prediction accuracy by 42%/36% on average on arc delay/slew, and improve timing metrics in terms of WNS, TNS, and the number of timing violation paths by 77%, 77%, and 64%, which are an increase of 32%/35% on arc delay/slew and 30%, 20% and 31% on timing optimization compared with the existing DL prediction model.

In global routing, congestion and running time are the key factors that affect the quality of the solution. With the rapid growth of integrated chip scale, striking a balance between running time and congestion has become a bottleneck in improving design quality. In this paper, we propose a highly efficient and effective global router to address this challenge. We first propose an efficient R-tree-based compatible routing region partitioning algorithm for collecting routable regions, which offers robust support for ideal parallel routing scheduling. Then, taking into account the effect of the barrel effect on congestion evaluation and the detrimental impact of loops, a congestion-driven initial parallel routing scheme is proposed to enhance routability in the triaxial pattern routing structure. After that, we develop an accurate congestion estimation model and an optimized path-searching scheme, which are instrumental in effectively managing smaller congestion gradient variations and guiding efficient congestion reduction. We evaluate the performance of our algorithm on the ISPD 2018 and ISPD 2019 contest benchmark suites and compare it with the state-of-the-art work. Experimental results show that our proposed algorithm significantly reduces 71% overflows, improving 65% running time, and the total wirelength is even smaller.

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.

In this paper, a fully integrated memristive Chua’s chaotic circuit based on the voltage-controlled oscillator is proposed. The memristor replaces the nonlinear diode, and the VCO (voltage-controlled oscillator) replaces the LC oscillator, eliminating the need for diodes, resistors, capacitors, and other complex circuit structures. The proposed chaotic circuit occupies a small chip area, only 0.0045 ${\mathrm{mm}}^2$, and achieves low power consumption of 2.8267 $\mathrm{mW}$. The chaotic circuit is fabricated using the SMIC 180 nm CMOS process. The simulation results demonstrate that the VCO circuit can generate a frequency output ranging from 358 MHz to 1.1 GHz by varying Vc from 0 V to 2.8 V, with a power supply of 3.3 V. The value range of the Lyapunov index is 1.015 $\sim$1.03. The circuit offers advantages such as a stable power supply, low power consumption, and a small chip area.

In this paper, a fast hardware accelerator for defogging based on image fusion is proposed. This method overcomes the problem of model based defogging algorithms being unable to estimate atmospheric light in dark scenes, as well as the poor performance of learning based defogging algorithms at night. Through hardware implementation and optimization, while reducing system resources, it can meet the demand for real-time defogging. The entire algorithm consists of difference guided filtering, grayscale linear stretching, and image fusion. The difference oriented filtering algorithm can enhance edges by obtaining image information of bright and dark channels, and has better effects on night lighting. Gray-scale linear stretching can restore the overall brightness and edge information of the image, compensating for some halos and noise caused by difference guided filtering. Numerous experiments have shown that the proposed hardware accelerator for defogging performs best at night. It can also be used effectively during the day. In addition, it has the fastest processing speed, which can process the images with the size of 1920*1080 for 34.5fps in real time.

FPGAs, characterized by their low power consumption and swift response, are ideally suited for parallel computations associated with object detection tasks, making them a popular choice for target detection and neural network acceleration. However, contemporary FPGA designs often come with high costs and resource demands, which limit their adoption in resource-constrained embedded and edge devices. This study presents a novel design that addresses these limitations by emphasizing cost-effectiveness, energy efficiency, and rapid performance, particularly for single-shot multi-box detectors. The design employs an Xilinx ZYNQ7020-based main control chip and leverages parallel computing models for convolution layers and feature extraction. It enhances efficiency by proposing parallel feature extraction at the network architecture level and integrates convolution activation and pooling in a single, hardware-optimized operation for convolution kernel computations. The design employs alternating memory reuse for feature layer inputs and outputs to optimize memory management, thereby reducing read/write delays and transmission times. Implemented on a PYNQ-Z2 development board and tested using Jupyter Notebook, the SSD algorithm demonstrates a 789.4 GOPS inference performance with 16-bit fixed-point quantization at a 200MHz clock frequency, achieving an average accuracy of 77.84% and an inference time of 81.4621 ms, while consuming 1.595 watts of power. This innovative design significantly boosts energy efficiency by up to 2590%, outperforming contemporary methods.

Since the concept of memristor was proposed, the construction of memristive hyperchaotic map has attracted wide attention. In this paper, a new 4D memristive hyperchaotic map is presented, investigating its characteristics such as multi$-$scroll attractors, coexisting attractors, offset boosting, and amplitude modulation. Regulated by variations in parameters, it exhibits extensive and continuous ranges of hyperchaotic behavior, overcoming the discontinuity issue in the chaotic range of traditional maps. Simulation results and numerical analyses demonstrate that it can generate diverse dynamic behaviors and possess superior chaotic properties. The National Institute of Standards and Technology (NIST) test reveals that the generated sequences display a high degree of randomness. A digital hardware platform based on microcomputer is established to verify the physical feasibility. Lastly, its successful application in the development of image encryption algorithm underscores the immense potential in the field of information security.

In this paper, we proposed a fully floating memristor emulator with long-term memory characteristics. The circuit comprises operational amplifiers and an analog switch. Switching between incremental and decremental modes is easily achieved by changing the polarity of the input signal. The key feature of the emulator is its long-term memory, made possible by the switch and voltage follower. The correctness of the derived formula is verified using Matlab, and the emulator's pinched hysteresis loop and non-volatility are assessed using LTspice. Additionally, an experimental platform was constructed for physical testing, with the physical results showing consistency with the simulations. Finally, the proposed emulator was applied to a simple read-write circuit, demonstrating its practical applicability.

In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a ‘digital fingerprint’ for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a ‘weak’ PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness.

An electronic circuit capable of performing the functions of all three memelements through simple configuration adjustments, known as a universal memelement emulator, addresses significant issues regarding the size and power consumption associated with integrated chips. This study aims to develop such a universal memelement emulator with configurable architecture requiring only few changes to switch into desired memelement emulator. The designed structure is based on only single active element known as the FTFNTA (Four Terminal Floating Nullor Transconductance Amplifier). The proposed circuit, in addition to a single FTFNTA, incorporates only four passive elements and three switches. Through the manipulation of these switches, the universal emulator can be configured to emulate three distinct memelements: flux-controlled memristor (FCMR), flux-controlled meminductor (FCMI), and charge-controlled memcapacitor (CCMC). The non-ideal analysis was conducted after considering the deviated parameters of the FTFNTA and associated parasitic elements and resultant behaviour is discussed. Simulation results conducted in the PSPICE environment validate the functionality of the realized memelements. Furthermore, verification of the concept is performed by implementing the FTFNTA-based circuit using commercially available ICs, specifically LM13700 and AD844, with the results discussed accordingly. The working of the realized memristor has also been verified by utilizing the proposed emulator (tuned as a memristor) in an associative learning circuit. Finally, the proposed emulator is validated experimentally using the physical ICs based breadboard implementation.