Integration-The Vlsi Journal最新文献

英文中文

Improved adaptive sliding mode control for non-ideal single-inductor dual-output boost converter

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-16 DOI: 10.1016/j.vlsi.2024.102335

Lin Yang , Jiarong Wu , Hailong Ma

Single-inductor dual-output (SIDO) boost converters have been applied in portable electronic devices, but the cross-regulation severely deteriorates its dynamic performance. Meanwhile, parasitic parameters have a significant impact on the cross-regulation. To suppress the cross-regulation and improve the performance of a non-ideal SIDO boost converter, an improved adaptive sliding mode control strategy is proposed in this paper. Considering the parasitic resistor of the inductor, capacitors and MOSFETs, a nonlinear mathematical model of the non-ideal SIDO boost converter is established. Based on the differential geometry theory, a set of output functions that meet the requirements of exact feedback linearization is constructed to linearize the model. An improved adaptive reaching law is proposed to reduce the sliding mode chattering. Combining adaptive technology, improved adaptive sliding mode controllers are designed. The stability and robustness of the control system are verified based on Lyapunov theory. Compared with the existing control method, simulation and experimental results show that the proposed control strategy provides a rapider response, lower cross-regulation, and better performance.

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引用次数: 0

High-performance CORDIC-based approximate MAC architectures for FPGA platforms

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-16 DOI: 10.1016/j.vlsi.2024.102338

Burhan Khurshid

CORDIC is a versatile algorithm frequently used in different signal-processing operations. While using CORDIC-based computations in evaluating trigonometric and transcendental functions is quite prevalent, the resource overhead associated with its implementation does not justify its use in evaluating linear functions like multiplication and addition. However, with the emergence of approximate computing as an attractive paradigm for error-resilient applications, the algorithm can be used to design approximate linear computational units that completely justify the accuracy-performance trade-offs. In this paper, we model the CORDIC-based computations to emulate the multiply-accumulate operation, albeit with some loss of accuracy. We specifically present two incremental CORDIC-based multiply-accumulate architectures with an attempt to improve the accuracy-performance trade-offs with each increment. A detailed Pareto analysis for 8 and 16-bit unsigned and signed multiply-accumulate structures is conducted to determine the optimum number of computing stages and the associated bit-precision of the intermediate results. Accuracy and performance analysis using 6th and 7th generation FPGAs reveals a substantial improvement over state-of-the-art designs. The proposed architectures are also tested using three image processing applications, and the output results are promising.

{"title":"High-performance CORDIC-based approximate MAC architectures for FPGA platforms","authors":"Burhan Khurshid","doi":"10.1016/j.vlsi.2024.102338","DOIUrl":"10.1016/j.vlsi.2024.102338","url":null,"abstract":"<div><div>CORDIC is a versatile algorithm frequently used in different signal-processing operations. While using CORDIC-based computations in evaluating trigonometric and transcendental functions is quite prevalent, the resource overhead associated with its implementation does not justify its use in evaluating linear functions like multiplication and addition. However, with the emergence of approximate computing as an attractive paradigm for error-resilient applications, the algorithm can be used to design approximate linear computational units that completely justify the accuracy-performance trade-offs. In this paper, we model the CORDIC-based computations to emulate the multiply-accumulate operation, albeit with some loss of accuracy. We specifically present two incremental CORDIC-based multiply-accumulate architectures with an attempt to improve the accuracy-performance trade-offs with each increment. A detailed Pareto analysis for 8 and 16-bit unsigned and signed multiply-accumulate structures is conducted to determine the optimum number of computing stages and the associated bit-precision of the intermediate results. Accuracy and performance analysis using 6th and 7th generation FPGAs reveals a substantial improvement over state-of-the-art designs. The proposed architectures are also tested using three image processing applications, and the output results are promising.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102338"},"PeriodicalIF":2.2,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Localisation of malicious nets in integrated circuits using unsupervised methodologies

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-16 DOI: 10.1016/j.vlsi.2024.102312

Tapobrata Dhar, Chandan Giri, Surajit Kumar Roy

A novel golden-model free unsupervised static analysis method is proposed for detecting Hardware Trojan Horse (HTH) nets in integrated circuits (IC). Established and newly introduced gate-level HTH features are extracted and separate feature subsets are obtained pertaining to natures of combinational and sequential HTHs. Local outlier analysis is used to identify the nets that exhibit behaviours pertaining to specific HTH types. Heuristic localisation process through neighbourhood analysis is used to identify malicious nets within the gate-level netlist of the host IC. The proposed localisation technique detect HTH nets with consistent high accuracy and high average true positive rate (TPR).

引用次数: 0

ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-14 DOI: 10.1016/j.vlsi.2024.102315

Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi

Surrogate model-based design space exploration (DSE) is the mainstream method to search for optimal microarchitecture designs. However, building accurate models for accelerator-rich systems within limited samples is challenging due to their high dimensionality. Additionally, these models often fall into local optima or have difficulty converging. To address these issues, we propose a DSE flow based on active learning, called ARS-Flow. This method features particle-swarm-optimized Gaussian process regression modeling (PSOGPR), a multiobjective genetic algorithm with self-adaptive hyperparameter control (SAMOGA), and a Pareto-region-oriented stochastic resampling method (PRSRS). Using the gem5-SALAM system for evaluation, the proposed method can build more accurate models and find better microarchitecture designs with acceptable runtime costs.

引用次数: 0

CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-13 DOI: 10.1016/j.vlsi.2024.102333

Salih Yalcin , Hamdi Burak Usul , Gulay Yalcin

Traveling Salesman Problem (TSP) is one of the significant problems in computer science which tries to find the shortest path for a salesman who needs to visit a set of cities and it is involved in many computing problems such as networks, genome analysis, logistics etc. Using parallel executing paradigms, especially GPUs, is appealing in order to reduce the problem solving time of TSP. One of the main issues in GPUs is to have limited GPU memory which would not be enough for the entire data. Therefore, transferring data from the host device would reduce the performance in execution time. In this study, we applied three data compression methodologies to represent cities in the TSP such as (1) Using Greatest Common Divisor (2) Shift Cities to the Origin (3) Splitting Surface to Grids. Therefore, we include more cities in GPU memory and reduce the number of data transfers from the host device. We implement our methodology in Iterated Local Search (ILS) algorithm with 2-opt and The Lin–Kernighan–Helsgaun (LKH) Algorithm. We show that our implementation presents more than 25% performance improvement for both algorithms.

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引用次数: 0

Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102320

Christoph Hazott, Florian Stögmüller, Daniel Große

Embedded graphics libraries are part of the Firmware (FW) of embedded systems and provide complex functionalities optimized for specific hardware. After unit testing of embedded graphics libraries, integration testing is a significant challenge, in particular since the hardware is needed to obtain the output image as well as the inherent difficulty in defining the reference result. In this paper, we present a novel approach focusing on integration testing of embedded graphic libraries. We leverage Virtual Prototypes (VPs) and integrate them with Metamorphic Testing (MT). Metamorphic Testing (MT) is a software testing technique that uncovers faults or issues in a system by exploring how its outputs change under predefined input transformations, without relying on explicit oracles or predetermined results. In combination with virtualizing the displays in VPs, we even eliminate the need for physical hardware. This allows us to develop a Metamorphic Testing (MT) framework automating the verification process. In our evaluation, we demonstrate the effectiveness of our Metamorphic Testing (MT) framework. On an extended RISC-V Virtual Prototype (VP) for the GD32VF103VBT6 platform, we found 15 distinct bugs for the widely used TFT_eSPI embedded graphics library, confirming the strength our approach. We finish the evaluation of our Metamorphic Testing (MT) approach by discussing the achieved structural coverage for function, line and branch coverage.

{"title":"Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries","authors":"Christoph Hazott, Florian Stögmüller, Daniel Große","doi":"10.1016/j.vlsi.2024.102320","DOIUrl":"10.1016/j.vlsi.2024.102320","url":null,"abstract":"<div><div>Embedded graphics libraries are part of the <em>Firmware</em> (FW) of embedded systems and provide complex functionalities optimized for specific hardware. After unit testing of embedded graphics libraries, integration testing is a significant challenge, in particular since the hardware is needed to obtain the output image as well as the inherent difficulty in defining the reference result. In this paper, we present a novel approach focusing on integration testing of embedded graphic libraries. We leverage <em>Virtual Prototypes</em> (VPs) and integrate them with <em>Metamorphic Testing</em> (MT). <em>Metamorphic Testing</em> (MT) is a software testing technique that uncovers faults or issues in a system by exploring how its outputs change under predefined input transformations, without relying on explicit oracles or predetermined results. In combination with virtualizing the displays in VPs, we even eliminate the need for physical hardware. This allows us to develop a <em>Metamorphic Testing</em> (MT) framework automating the verification process. In our evaluation, we demonstrate the effectiveness of our <em>Metamorphic Testing</em> (MT) framework. On an extended RISC-V <em>Virtual Prototype</em> (VP) for the GD32VF103VBT6 platform, we found 15 distinct bugs for the widely used TFT_eSPI embedded graphics library, confirming the strength our approach. We finish the evaluation of our <em>Metamorphic Testing</em> (MT) approach by discussing the achieved structural coverage for function, line and branch coverage.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102320"},"PeriodicalIF":2.2,"publicationDate":"2024-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102310

Sameera Shaik , S.M. Srinivasavarma Vegesna , Noor Mahammad S.K.

Intrusion Detection System (IDS) is a type of packet filtering that ensures network security by analyzing the packets flowing through the network and detecting any malicious pattern(s) present in them. In signature-based NIDS, pattern matching is the critical step as it determines the system’s performance. The throughput of the system, inherently, relies on the delay required to match an input pattern. Hardware-based high-speed pattern matching algorithms are popularly used to speed up the pattern matching process and improve the system’s performance. Ternary Content Addressable Memory (TCAM) is one such memory in which the input pattern is simultaneously launched on all the match lines. Since all the match lines and search lines are activated at a given instance, the power consumed per search is extremely high. To address this issue, this paper proposes an approach in which the match is carried out with an n-bit prefix of the input pattern that enables a smaller TCAM unit, which contains the patterns having this prefix. A significant improvement in energy is observed since a single TCAM segment is enabled for a single search. The results are compared with existing solutions, and energy improvement of 96.1% is observed with worst case and best case throughput of

17 G b p s

and

148 G b p s

, respectively.

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引用次数: 0

The art of temporal decoupling

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102314

Niko Zurstraßen , Ruben Brandhofer , José Cubero-Cascante , Nils Bosbach , Lukas Jünger , Rainer Leupers

Virtual Platforms (VPs) and Full-System Simulators (FSSs) are essential tools in modern Multiprocessor System on A Chip (MPSoC) development. Over the past two decades, the speed of these simulations has not kept pace with the increasing complexity of the systems being simulated, highlighting the need for faster simulation techniques. One widely used approach is Temporal Decoupling (TD), which allows parts of the simulation to run unsynchronized with the rest of the system for a period called the quantum. While a larger quantum improves simulation performance by reducing the number of synchronization and context switches, it also raises the risk of causality errors, leading to inaccuracies. Consequently, users of TD simulations may struggle to find the optimal quantum that balances accuracy and performance. In practice, the quantum is often chosen based on empirical knowledge, which, though sometimes effective, lacks a solid theoretical basis. This work addresses this gap by offering analytical estimations and deeper insights into the effects of TD. We also validate the proposed models using TD simulations in SystemC and gem5.

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引用次数: 0

An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuit

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-09 DOI: 10.1016/j.vlsi.2024.102319

Tengfei Yuan , Pengjun Wang , Yuejun Zhang , Ziyu Zhou

—Physical unclonable function (PUF) as an emerging hardware security primitive has caused extensive research by scholars. PUF extracts unclonable fingerprint information from intrinsic changes in the circuit during operation. However, conventional PUFs usually adopt the dedicated circuit structure to generate random, non-clonable responses, which require additional hardware resource overhead. This article proposes a software PUF (SPUF) based on the video encoding circuit in response to the above issues. SPUF causes abnormal operation of the encoding circuit by applying an overclocking clock. A response key with circuit characteristics is generated by exploiting the response to timing path dependence. Primarily, the video coding circuit, which is part of the open-source H265 IP Core, is taken as the PUF circuit carrier. Secondly, after analyzing the timing path of the encoding circuit, an overclocking signal is selected according to the timing path to put the circuit in abnormal operating mode. Then, unclonable random data is generated while completing video encoding and compression. Next, the response data is obfuscated by gray encoding and XOR operation to improve the responses' reliability further. Finally, a both-way encrypted lightweight authentication protocol is constructed. Encrypting the video stream with SPUF responses and random numbers enables bi-directional encrypted transmission between the device and the server. The test results show that the proposed SPUF passes the NIST test with a uniqueness of 48.87 %. The autocorrelation coefficient is 0.0204 at 95 % confidence, showing good randomness and uniqueness.

{"title":"An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuit","authors":"Tengfei Yuan , Pengjun Wang , Yuejun Zhang , Ziyu Zhou","doi":"10.1016/j.vlsi.2024.102319","DOIUrl":"10.1016/j.vlsi.2024.102319","url":null,"abstract":"<div><div>—Physical unclonable function (PUF) as an emerging hardware security primitive has caused extensive research by scholars. PUF extracts unclonable fingerprint information from intrinsic changes in the circuit during operation. However, conventional PUFs usually adopt the dedicated circuit structure to generate random, non-clonable responses, which require additional hardware resource overhead. This article proposes a software PUF (SPUF) based on the video encoding circuit in response to the above issues. SPUF causes abnormal operation of the encoding circuit by applying an overclocking clock. A response key with circuit characteristics is generated by exploiting the response to timing path dependence. Primarily, the video coding circuit, which is part of the open-source H265 IP Core, is taken as the PUF circuit carrier. Secondly, after analyzing the timing path of the encoding circuit, an overclocking signal is selected according to the timing path to put the circuit in abnormal operating mode. Then, unclonable random data is generated while completing video encoding and compression. Next, the response data is obfuscated by gray encoding and XOR operation to improve the responses' reliability further. Finally, a both-way encrypted lightweight authentication protocol is constructed. Encrypting the video stream with SPUF responses and random numbers enables bi-directional encrypted transmission between the device and the server. The test results show that the proposed SPUF passes the NIST test with a uniqueness of 48.87 %. The autocorrelation coefficient is 0.0204 at 95 % confidence, showing good randomness and uniqueness.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102319"},"PeriodicalIF":2.2,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nested chopper instrument amplifier with noise modulation for physiological signal sensing

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-12-07 DOI: 10.1016/j.vlsi.2024.102332

Bo Liu, Dong Zhang, Tianyu Liu, Kai Li, Jinchan Wang, Jun Wang

This article presents a novel CMOS nested chopper instrumentation amplifier (NCIA) suitable for physiological signal (such as EEG, ECG and EMG) acquisition systems. By incorporating a DC offset suppression module and impedance boosting loop, the implemented instrumentation amplifier achieves high input impedance and low DC offset voltage. The usage of novel nested chopping technology with noise shifting in the filtering circuit effectively eliminates low-frequency noise, which makes it well-suited for analog front-end (AFE) sensing systems for precision extraction of weak physiological signals. The proposed NCIA circuit is implemented based on 180 nm/1.8 V standard BCD technology. Under 1.8V power supply voltage, the power consumption of the overall amplifier circuit is 4.17 μW, the total input reference noise is 771.365 nV_rms, and the total circuit layout area is 5.47 × 10⁻² mm².

引用次数: 0

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