Pub Date : 2025-11-01DOI: 10.1016/j.vlsi.2025.102586
Ayush Dahiya, Poornima Mittal, Rajesh Rohilla
The SRAM cell structure in itself offers huge performance improvements in the memory array. An eight transistor SRAM cell (8TP) is presented with high- PMOS transistors used together with nominal- NMOS transistors. The 8TP cell offers a process variation resistant structure which offers a good balance between stability, delay, write margin, leakage and power consumption over other cell structures over a wide range of supply voltages for 0.6 V to 1.2 V. A number of 2000-point Monte Carlo simulations were performed for highlighting the impact of process, voltage and temperature variations on the cell architecture. The 8TP cell has a write-1/write-0 margin (WM) of 0.4091 V/ 0.4092 V at supply of 0.8 V. The stability of the cell is shown by its static noise margin (SNM) which shows a 6 deviation for a temperature range of to 100°C. The cell offers excellent read and write performance compared to various other SRAM cells. The 8TP cell also demonstrates low leakage and power consumption compared among other 8T cells. The 8TP cell exhibits a good balance between speed and stability while having a competitive area footprint as well as half-select resilience which makes it a good choice for low-power applications.
{"title":"A low-power half-select free 8T SRAM cell with process-induced variation resistance for voltage scaling at 32 nm technology node","authors":"Ayush Dahiya, Poornima Mittal, Rajesh Rohilla","doi":"10.1016/j.vlsi.2025.102586","DOIUrl":"10.1016/j.vlsi.2025.102586","url":null,"abstract":"<div><div>The SRAM cell structure in itself offers huge performance improvements in the memory array. An eight transistor SRAM cell (8TP) is presented with high-<span><math><msub><mrow><mi>V</mi></mrow><mrow><mtext>T</mtext></mrow></msub></math></span> PMOS transistors used together with nominal-<span><math><msub><mrow><mi>V</mi></mrow><mrow><mtext>T</mtext></mrow></msub></math></span> NMOS transistors. The 8TP cell offers a process variation resistant structure which offers a good balance between stability, delay, write margin, leakage and power consumption over other cell structures over a wide range of supply voltages for 0.6 V to 1.2 V. A number of 2000-point Monte Carlo simulations were performed for highlighting the impact of process, voltage and temperature variations on the cell architecture. The 8TP cell has a write-1/write-0 margin (WM) of 0.4091 V/ 0.4092 V at supply of 0.8 V. The stability of the cell is shown by its static noise margin (SNM) which shows a 6<span><math><mi>σ</mi></math></span> deviation for a temperature range of <span><math><mrow><mo>−</mo><mn>25</mn><mo>°</mo><mtext>C</mtext></mrow></math></span> to 100°C. The cell offers excellent read and write performance compared to various other SRAM cells. The 8TP cell also demonstrates low leakage and power consumption compared among other 8T cells. The 8TP cell exhibits a good balance between speed and stability while having a competitive area footprint as well as half-select resilience which makes it a good choice for low-power applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102586"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145519609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1016/j.vlsi.2025.102592
Xiumin Xu , Liang Yao
On-chip multi-ported shared memory, functioning as a global buffer in AI accelerators, plays a vital role in enabling high-throughput data reuse and minimizing memory latency. However, as the number of ports increases, traditional architectures face rapidly escalating interconnect complexity, timing closure issues, and significant hardware overhead. To overcome these challenges, we propose X-RAM, a novel multi-ported memory architecture that integrates an x-type low-fan-out network with a merge-split interface scheduling strategy. This approach significantly enhances routability and scalability while maintaining low logic cost and predictable port arbitration. X-RAM is designed to support concurrent multi-port access with high bandwidth efficiency, making it well-suited for compute-intensive AI operations such as matrix multiplication and multi-dimensional convolution. We validate X-RAM by integrating it into a reconfigurable AI accelerator prototype and conducting continuous random matrix multiplication tests. Implementations on FPGA and 28 nm CMOS demonstrate robust performance, including 1 GHz operating frequency and compact area utilization (9.4 mm2). Experimental results confirm that X-RAM delivers efficient memory access, high bandwidth (up to 153.6 Gbps), and system-level scalability, offering a practical solution to the memory bottleneck in modern AI systems.
{"title":"X-RAM: a novel and efficient multi-ported memory for AI accelerator","authors":"Xiumin Xu , Liang Yao","doi":"10.1016/j.vlsi.2025.102592","DOIUrl":"10.1016/j.vlsi.2025.102592","url":null,"abstract":"<div><div>On-chip multi-ported shared memory, functioning as a global buffer in AI accelerators, plays a vital role in enabling high-throughput data reuse and minimizing memory latency. However, as the number of ports increases, traditional architectures face rapidly escalating interconnect complexity, timing closure issues, and significant hardware overhead. To overcome these challenges, we propose X-RAM, a novel multi-ported memory architecture that integrates an x-type low-fan-out network with a merge-split interface scheduling strategy. This approach significantly enhances routability and scalability while maintaining low logic cost and predictable port arbitration. X-RAM is designed to support concurrent multi-port access with high bandwidth efficiency, making it well-suited for compute-intensive AI operations such as matrix multiplication and multi-dimensional convolution. We validate X-RAM by integrating it into a reconfigurable AI accelerator prototype and conducting continuous random matrix multiplication tests. Implementations on FPGA and 28 nm CMOS demonstrate robust performance, including 1 GHz operating frequency and compact area utilization (9.4 mm<sup>2</sup>). Experimental results confirm that X-RAM delivers efficient memory access, high bandwidth (up to 153.6 Gbps), and system-level scalability, offering a practical solution to the memory bottleneck in modern AI systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102592"},"PeriodicalIF":2.5,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145519611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-28DOI: 10.1016/j.vlsi.2025.102591
Oumayma Bel Haj Salah , Seifeddine Messaoud , Mohamed Ali Hajjaji , Mohamed Atri , Noureddine Liouane
The deployment of deep neural networks on embedded systems remains a challenging task due to stringent constraints in computational resources, memory bandwidth, and energy efficiency. In this work, we present QYOLOv10, a quantization-aware acceleration framework designed to enable efficient object detection using low-precision variants of the YOLOv10 model—namely nano (n), small (s), and medium (m). The proposed method integrates advanced post-training quantization techniques for weights, activations, and inputs, with adaptive precision strategies aligned to hardware-specific constraints. These optimizations strike a favorable trade-off between computational efficiency and detection accuracy. To demonstrate real-world viability, we deploy QYOLOv10 on the Xilinx Kria KV260 platform using a customized Deep Processing Unit (DPU) overlay synthesized in Vivado and executed via the Vitis AI runtime. Experimental results show that QYOLOv10 achieves up to 4.8 improvement in inference speed, over 40% memory footprint reduction, and maintains accuracy within 1.2% of the original full-precision models. Inference latency is reduced to below 25 ms per image, enabling robust real-time performance. These results highlight the suitability of QYOLOv10 for edge-centric applications such as autonomous navigation, intelligent surveillance, and IoT-based visual analytics. By addressing the practical challenges of deep model deployment under resource-constrained conditions, this work contributes a scalable and hardware-aware solution for embedded object detection systems.
{"title":"Low-latency QYOLOv10-based FPGA implementation for real-time object detection","authors":"Oumayma Bel Haj Salah , Seifeddine Messaoud , Mohamed Ali Hajjaji , Mohamed Atri , Noureddine Liouane","doi":"10.1016/j.vlsi.2025.102591","DOIUrl":"10.1016/j.vlsi.2025.102591","url":null,"abstract":"<div><div>The deployment of deep neural networks on embedded systems remains a challenging task due to stringent constraints in computational resources, memory bandwidth, and energy efficiency. In this work, we present QYOLOv10, a quantization-aware acceleration framework designed to enable efficient object detection using low-precision variants of the YOLOv10 model—namely nano (n), small (s), and medium (m). The proposed method integrates advanced post-training quantization techniques for weights, activations, and inputs, with adaptive precision strategies aligned to hardware-specific constraints. These optimizations strike a favorable trade-off between computational efficiency and detection accuracy. To demonstrate real-world viability, we deploy QYOLOv10 on the Xilinx Kria KV260 platform using a customized Deep Processing Unit (DPU) overlay synthesized in Vivado and executed via the Vitis AI runtime. Experimental results show that QYOLOv10 achieves up to 4.8<span><math><mo>×</mo></math></span> improvement in inference speed, over 40% memory footprint reduction, and maintains accuracy within 1.2% of the original full-precision models. Inference latency is reduced to below 25 ms per image, enabling robust real-time performance. These results highlight the suitability of QYOLOv10 for edge-centric applications such as autonomous navigation, intelligent surveillance, and IoT-based visual analytics. By addressing the practical challenges of deep model deployment under resource-constrained conditions, this work contributes a scalable and hardware-aware solution for embedded object detection systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102591"},"PeriodicalIF":2.5,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145416390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1016/j.vlsi.2025.102590
Zilong Liang, Xinbo Zhang, Mark Vousden, David B. Thomas, Graeme M. Bragg
Modern digital neuromorphic system design increasingly demands parallel architectures capable of scaling Spiking Neural Network (SNN) simulations to levels of complexity comparable to the human brain. As a result, developing SNN models that can efficiently leverage such architectures has emerged as a critical research challenge. This work presents a novel Synfire Ring SNN model specifically designed for event-driven, parallel neuromorphic platforms to explore the capacity of neurons and synapses, addressing key limitations related to communication latency and resource inefficiency observed in previous implementations. The proposed model employs uniform neuron pools, thus simplifying network topology while improving scalability and ensuring more predictable performance. Experimental validation in a single POETS box, comprising six DE5-Net FPGAs, demonstrates real-time operation that involves 509,648 neurons and 509,648,000 synapses. Comparative analysis with quantitative simulations of SpiNNaker, evaluated under a fixed wallclock simulation window, highlights the suitability of the proposed Synfire Ring topology for the event-driven parallel architecture. Furthermore, an analytical scalability model, grounded in the experimental data, forecasts near-linear scaling up to 4.1 million neurons and 4.1 billion synapses on the full 48-FPGA POETS system.
现代数字神经形态系统设计越来越需要能够将峰值神经网络（SNN）模拟扩展到与人脑相当的复杂水平的并行架构。因此，开发能够有效利用此类架构的SNN模型已成为一项关键的研究挑战。这项工作提出了一个新的Synfire Ring SNN模型，专门为事件驱动的并行神经形态平台设计，用于探索神经元和突触的容量，解决了先前实现中观察到的与通信延迟和资源低效相关的关键限制。该模型采用统一的神经元池，从而简化了网络拓扑结构，同时提高了可扩展性，并确保了更可预测的性能。在包含6个DE5-Net fpga的单个poet盒中进行实验验证，演示了涉及509,648个神经元和509,648,000个突触的实时操作。与SpiNNaker的定量仿真进行对比分析，在固定的挂钟模拟窗口下进行评估，强调了所提出的Synfire Ring拓扑对于事件驱动并行架构的适用性。此外，基于实验数据的分析可扩展性模型预测，在完整的48 fpga poet系统上，可近线性扩展到410万个神经元和41亿个突触。
{"title":"Quantitative simulations of Spiking Neural Networks on an event-driven FPGA cluster","authors":"Zilong Liang, Xinbo Zhang, Mark Vousden, David B. Thomas, Graeme M. Bragg","doi":"10.1016/j.vlsi.2025.102590","DOIUrl":"10.1016/j.vlsi.2025.102590","url":null,"abstract":"<div><div>Modern digital neuromorphic system design increasingly demands parallel architectures capable of scaling Spiking Neural Network (SNN) simulations to levels of complexity comparable to the human brain. As a result, developing SNN models that can efficiently leverage such architectures has emerged as a critical research challenge. This work presents a novel Synfire Ring SNN model specifically designed for event-driven, parallel neuromorphic platforms to explore the capacity of neurons and synapses, addressing key limitations related to communication latency and resource inefficiency observed in previous implementations. The proposed model employs uniform neuron pools, thus simplifying network topology while improving scalability and ensuring more predictable performance. Experimental validation in a single POETS box, comprising six DE5-Net FPGAs, demonstrates real-time operation that involves 509,648 neurons and 509,648,000 synapses. Comparative analysis with quantitative simulations of SpiNNaker, evaluated under a fixed wallclock simulation window, highlights the suitability of the proposed Synfire Ring topology for the event-driven parallel architecture. Furthermore, an analytical scalability model, grounded in the experimental data, forecasts near-linear scaling up to 4.1 million neurons and 4.1 billion synapses on the full 48-FPGA POETS system.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102590"},"PeriodicalIF":2.5,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145416389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-24DOI: 10.1016/j.vlsi.2025.102589
Jiho Jung, Ickjin Kwon
This paper presents a novel output capacitor-less low-dropout (OCL-LDO) regulator optimized for ultra-low-power Internet of Things (IoT) applications powered by ambient RF energy harvesting. To simultaneously achieve fast transient response and minimal power consumption, the proposed design employs a dual-pass-transistor architecture with adaptive biasing, dynamically scaling the bias current with load variations. This enables a minimum quiescent current of 100 nA while maintaining loop stability across a wide operating range. An auxiliary pass transistor further enhances dynamic behavior by supplying an additional current path during rapid load transitions without increasing static power. In addition, a dynamic current generator (DCG) delivers instantaneous current in response to output voltage deviations, effectively accelerating undershoot recovery and suppressing overshoot. Post-layout simulation results in a 180 nm CMOS process demonstrate a 41% reduction in undershoot, a 12% reduction in overshoot, and up to a 99.7% improvement in settling time compared with conventional OCL-LDOs. The regulator achieves a stable 1 V output with a dropout voltage of 0.2 V over a 0–10 mA load range and requires only a fully integrated 10 pF capacitor, eliminating external components. These innovations enable complete on-chip integration, making the proposed OCL-LDO a compelling solution for miniaturized RF energy harvesting-based IoT systems demanding ultra-low power and robust transient performance.
{"title":"Output capacitor-less LDO regulator with dual-pass adaptive biasing and dynamic current generation for ultra-low-power IoT","authors":"Jiho Jung, Ickjin Kwon","doi":"10.1016/j.vlsi.2025.102589","DOIUrl":"10.1016/j.vlsi.2025.102589","url":null,"abstract":"<div><div>This paper presents a novel output capacitor-less low-dropout (OCL-LDO) regulator optimized for ultra-low-power Internet of Things (IoT) applications powered by ambient RF energy harvesting. To simultaneously achieve fast transient response and minimal power consumption, the proposed design employs a dual-pass-transistor architecture with adaptive biasing, dynamically scaling the bias current with load variations. This enables a minimum quiescent current of 100 nA while maintaining loop stability across a wide operating range. An auxiliary pass transistor further enhances dynamic behavior by supplying an additional current path during rapid load transitions without increasing static power. In addition, a dynamic current generator (DCG) delivers instantaneous current in response to output voltage deviations, effectively accelerating undershoot recovery and suppressing overshoot. Post-layout simulation results in a 180 nm CMOS process demonstrate a 41% reduction in undershoot, a 12% reduction in overshoot, and up to a 99.7% improvement in settling time compared with conventional OCL-LDOs. The regulator achieves a stable 1 V output with a dropout voltage of 0.2 V over a 0–10 mA load range and requires only a fully integrated 10 pF capacitor, eliminating external components. These innovations enable complete on-chip integration, making the proposed OCL-LDO a compelling solution for miniaturized RF energy harvesting-based IoT systems demanding ultra-low power and robust transient performance.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102589"},"PeriodicalIF":2.5,"publicationDate":"2025-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1016/j.vlsi.2025.102588
Neha Maheshwari , Ambika Prasad Shah , Santosh Kumar Vishvakarma
In this paper, we explore an SRAM-based ring oscillator design based on gate logic. The gating logic not only ensures stable operation but also provides flexibility in managing the activation and deactivation of the oscillator, thus reducing power consumption during idle periods. The proposed Gated Logic-based SRAM cell consumes 1.17 and 1.02 lower read and write power respectively than conventional 6T SRAM. A detailed analysis validates this proposed SRAM cell can be a good candidate for implementing the memory-based RO with less number of memory cell utilization. The frequency in the schematic is 1.24 that of the post-layout and frequency variation with temperature and aging to ensure the reliability of the proposed ring oscillator. Further proposed GL-SRAM-RO consumes less power and area utilization than the previous design. The simulation results show bidirectional behavior, making it a suitable candidate for security and power efficiency requirements and integration into resource-constrained environments and embedded systems.
{"title":"Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators","authors":"Neha Maheshwari , Ambika Prasad Shah , Santosh Kumar Vishvakarma","doi":"10.1016/j.vlsi.2025.102588","DOIUrl":"10.1016/j.vlsi.2025.102588","url":null,"abstract":"<div><div>In this paper, we explore an SRAM-based ring oscillator design based on gate logic. The gating logic not only ensures stable operation but also provides flexibility in managing the activation and deactivation of the oscillator, thus reducing power consumption during idle periods. The proposed Gated Logic-based SRAM cell consumes 1.17<span><math><mo>×</mo></math></span> and 1.02<span><math><mo>×</mo></math></span> lower read and write power respectively than conventional 6T SRAM. A detailed analysis validates this proposed SRAM cell can be a good candidate for implementing the memory-based RO with less number of memory cell utilization. The frequency in the schematic is 1.24<span><math><mo>×</mo></math></span> that of the post-layout and frequency variation with temperature and aging to ensure the reliability of the proposed ring oscillator. Further proposed GL-SRAM-RO consumes less power and area utilization than the previous design. The simulation results show bidirectional behavior, making it a suitable candidate for security and power efficiency requirements and integration into resource-constrained environments and embedded systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102588"},"PeriodicalIF":2.5,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1016/j.vlsi.2025.102587
AbdolRasool Ghasemi , Hamed Aminzadeh
The need for battery-operated high-precision transceivers is pushing toward the use of high-order on-chip filters with maximum linearity and power efficiency. This paper presents a highly-linear Gm−C biquad filter, implemented to meet advanced wireless applications. A systematic approach is proposed to minimize the linearity requirements of the open-loop transconductors in biquad sections, reducing the differential voltage swing at the transconductors’ input with no area or power overhead. A fourth-order filter is implemented using the proposed biquad sections in a 0.18-μm CMOS technology. Post-layout simulation results demonstrate a −3 dB cut-off frequency of 600-kHz, a peak in-band total harmonic distortion (THD) improvement of 62.5 dB, and a peak 3rd-order intercept point (IIP3) enhancement of 15.3 dB at low frequencies. The proposed filter consumes 380-μW of power, achieving an input-referred noise (IRN) of 175-μV under an active area of 0.03-mm2. In return, the design introduces a modest 10.7 dB degradation in power-supply rejection (PSR) at low frequencies, which becomes negligible near the cut-off frequency. Comparative results indicate a favorable trade-off between linearity and common-mode (CM) rejection, making it suitable for certain wireless applications such as Bluetooth transceivers.
{"title":"A modified Tow-Thomas Gm−C filter with enhanced linearity","authors":"AbdolRasool Ghasemi , Hamed Aminzadeh","doi":"10.1016/j.vlsi.2025.102587","DOIUrl":"10.1016/j.vlsi.2025.102587","url":null,"abstract":"<div><div>The need for battery-operated high-precision transceivers is pushing toward the use of high-order on-chip filters with maximum linearity and power efficiency. This paper presents a highly-linear <em>G</em><sub><em>m</em></sub><em>−C</em> biquad filter, implemented to meet advanced wireless applications. A systematic approach is proposed to minimize the linearity requirements of the open-loop transconductors in biquad sections, reducing the differential voltage swing at the transconductors’ input with no area or power overhead. A fourth-order filter is implemented using the proposed biquad sections in a 0.18-μm CMOS technology. Post-layout simulation results demonstrate a −3 dB cut-off frequency of 600-kHz, a peak in-band total harmonic distortion (THD) improvement of 62.5 dB, and a peak 3rd-order intercept point (IIP3) enhancement of 15.3 dB at low frequencies. The proposed filter consumes 380-μW of power, achieving an input-referred noise (IRN) of 175-μV under an active area of 0.03-mm<sup>2</sup>. In return, the design introduces a modest 10.7 dB degradation in power-supply rejection (PSR) at low frequencies, which becomes negligible near the cut-off frequency. Comparative results indicate a favorable trade-off between linearity and common-mode (CM) rejection, making it suitable for certain wireless applications such as Bluetooth transceivers.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102587"},"PeriodicalIF":2.5,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-21DOI: 10.1016/j.vlsi.2025.102562
Esteban Tlelo-Cuautle , Eric Campos-Cantón , Jesús Manuel Muñoz-Pacheco , Guillermo Huerta-Cuellar
The Meeting for the Dissemination and Research in the Study of Complex Systems and their Applications (EDIESCA) 2024, was held in Aguascalientes, Mexico, during October 28–30, and successfully gathered 112 research articles from international researchers and students. The authors were from more than 30 national and international institutions. The program featured plenary lectures, oral presentations, and poster sessions covering a broad spectrum of topics, including nonlinear dynamics, chaos, synchronization, control, and applications across engineering, physics, and life sciences. One of the most significant outcomes of the meeting was the publication of 18 peer-reviewed papers in a special issue of Integration the VLSI Journal, highlighting both the scientific quality and international impact of EDIESCA. Beyond the dissemination of research results, the meeting fostered valuable collaborations among institutions, promoting long-term partnerships among scientists from diverse backgrounds. With over a decade of history, EDIESCA has proven to be a vital platform for advancing dynamical systems research and strengthening global scientific cooperation.
{"title":"Editorial: 5th meeting for the dissemination and research in the study of complex systems and their applications","authors":"Esteban Tlelo-Cuautle , Eric Campos-Cantón , Jesús Manuel Muñoz-Pacheco , Guillermo Huerta-Cuellar","doi":"10.1016/j.vlsi.2025.102562","DOIUrl":"10.1016/j.vlsi.2025.102562","url":null,"abstract":"<div><div>The Meeting for the Dissemination and Research in the Study of Complex Systems and their Applications (EDIESCA) 2024, was held in Aguascalientes, Mexico, during October 28–30, and successfully gathered 112 research articles from international researchers and students. The authors were from more than 30 national and international institutions. The program featured plenary lectures, oral presentations, and poster sessions covering a broad spectrum of topics, including nonlinear dynamics, chaos, synchronization, control, and applications across engineering, physics, and life sciences. One of the most significant outcomes of the meeting was the publication of 18 peer-reviewed papers in a special issue of Integration the VLSI Journal, highlighting both the scientific quality and international impact of EDIESCA. Beyond the dissemination of research results, the meeting fostered valuable collaborations among institutions, promoting long-term partnerships among scientists from diverse backgrounds. With over a decade of history, EDIESCA has proven to be a vital platform for advancing dynamical systems research and strengthening global scientific cooperation.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102562"},"PeriodicalIF":2.5,"publicationDate":"2025-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145617845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-20DOI: 10.1016/j.vlsi.2025.102585
Mahendra Rathor
Hardware watermarking helps detect various hardware security threats such as piracy, cloning, counterfeiting, and false claim of ownership of semiconductor intellectual property (IP) cores. However, a watermark cannot be uniquely associated with the vendor's identity unless it is created using an individual's unique features. Further, ideally, a watermarking approach should not incur design overhead after incorporating the security features. Therefore, this paper proposes ‘EASY- a zero-cost high level synthesis (HLS) based hardware watermarking scheme based on voice image features’ which not only uses unique features of an individual's voice sample but also offers seamless verification. The proposed verification process is independent of the potential variations in the biometric features values as it regenerates the feature values using a pre-stored voice image for verification. The proposed watermarking is also aware of the interconnect minimization during the embedding process and incurs zero design overhead. The results reveal that the strength of watermark achieved for the proposed approach is on an average 87 % and is considerably higher than the related works. Further, an average reduction in interconnect requirement for the registers sharing is achieved to be around 24.5 %. The proposed work offers the higher security and zero design cost overhead in contrast to the related works.
{"title":"EASY: Exploring zero-cost watermarking using voice image features for hardware security","authors":"Mahendra Rathor","doi":"10.1016/j.vlsi.2025.102585","DOIUrl":"10.1016/j.vlsi.2025.102585","url":null,"abstract":"<div><div>Hardware watermarking helps detect various hardware security threats such as piracy, cloning, counterfeiting, and false claim of ownership of semiconductor intellectual property (IP) cores. However, a watermark cannot be uniquely associated with the vendor's identity unless it is created using an individual's unique features. Further, ideally, a watermarking approach should not incur design overhead after incorporating the security features. Therefore, this paper proposes ‘<em>EASY- a zero-cost high level synthesis (HLS) based hardware watermarking scheme based on voice image features</em>’ which not only uses unique features of an individual's voice sample but also offers seamless verification. The proposed verification process is independent of the potential variations in the biometric features values as it regenerates the feature values using a pre-stored voice image for verification. The proposed watermarking is also aware of the interconnect minimization during the embedding process and incurs zero design overhead. The results reveal that the strength of watermark achieved for the proposed approach is on an average 87 % and is considerably higher than the related works. Further, an average reduction in interconnect requirement for the registers sharing is achieved to be around 24.5 %. The proposed work offers the higher security and zero design cost overhead in contrast to the related works.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102585"},"PeriodicalIF":2.5,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1016/j.vlsi.2025.102584
Xiaosong Wang, Qisheng Zhang, Yu Zhang
This paper proposes a frequency compensation scheme – high-pass feed-forward simple Miller compensation (SMCHPF), based on the output-capacitorless low dropout regulator (OCL-LDO) structure. Adding a high-pass feed-forward path to the LDO extends the bandwidth of the Miller loop, allowing the OCL-LDO to maintain loop stability with smaller output currents under no-load conditions. Additionally, it enhances the transient performance of the OCL-LDO, improving the slew rate of the power transistor gate. Furthermore, high-performance adaptive bias amplifiers, dynamic buffers, and non-linear current mirrors are used in the OCL-LDO to enhance performance. This designed SMCHPF-LDO was fabricated in TSMC 65 nm process, and the core area is . The actual operating voltage range is 2.7V-3.6V, with an output voltage of 0.61V–3.1V and a minimum voltage drop of 80 mV. The SMCHPF-LDO can drive a maximum load current of 50 mA and a load capacitance of 100 pF with a quiescent current consumption of 68 A and a maximum current efficiency of 99.86%. The test results show that the overshoot is 99.5 mV and the undershoot is 316 mV when the load current is switched between 0 mA and 50 mA within 180 ns under a 100pF load capacitor. In addition, the SMCHPF-LDO achieves a line regulation of 5.6mV/V and a load regulation of 0.304 mV/mA, allowing for the power supply rejection over the frequency range of 0–25 MHz.
{"title":"Design of an output-capacitorless low-dropout regulator with high-pass feed-forward compensation","authors":"Xiaosong Wang, Qisheng Zhang, Yu Zhang","doi":"10.1016/j.vlsi.2025.102584","DOIUrl":"10.1016/j.vlsi.2025.102584","url":null,"abstract":"<div><div>This paper proposes a frequency compensation scheme – high-pass feed-forward simple Miller compensation (SMCHPF), based on the output-capacitorless low dropout regulator (OCL-LDO) structure. Adding a high-pass feed-forward path to the LDO extends the bandwidth of the Miller loop, allowing the OCL-LDO to maintain loop stability with smaller output currents under no-load conditions. Additionally, it enhances the transient performance of the OCL-LDO, improving the slew rate of the power transistor gate. Furthermore, high-performance adaptive bias amplifiers, dynamic buffers, and non-linear current mirrors are used in the OCL-LDO to enhance performance. This designed SMCHPF-LDO was fabricated in TSMC 65 nm process, and the core area is <span><math><mrow><mn>170</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> <span><math><mo>∗</mo></math></span> <span><math><mrow><mn>100</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span>. The actual operating voltage range is 2.7V-3.6V, with an output voltage of 0.61V–3.1V and a minimum voltage drop of 80 mV. The SMCHPF-LDO can drive a maximum load current of 50 mA and a load capacitance of 100 pF with a quiescent current consumption of 68 <span><math><mi>μ</mi></math></span>A and a maximum current efficiency of 99.86%. The test results show that the overshoot is 99.5 mV and the undershoot is 316 mV when the load current is switched between 0 mA and 50 mA within 180 ns under a 100pF load capacitor. In addition, the SMCHPF-LDO achieves a line regulation of 5.6mV/V and a load regulation of 0.304 mV/mA, allowing for the power supply rejection over the frequency range of 0–25 MHz.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102584"},"PeriodicalIF":2.5,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145416388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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