Integration-The Vlsi Journal最新文献_第7页

Advanced fault diagnosis in analog and digital VLSI circuits utilizing multi-anchor space-aware temporal convolutional neural network for efficient circuit reliability assessment 利用多锚点空间感知时间卷积神经网络对模拟和数字VLSI电路进行高级故障诊断，以实现有效的电路可靠性评估

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-11 DOI: 10.1016/j.vlsi.2025.102631

Divya Arivalagan , O. Vignesh , S.S. Abinayaa , V.S. Nishok

Fault diagnosis in analog and digital Very Large Scale Integration (VLSI) circuits is essential for ensuring reliable operation and performance. These circuits are increasingly complex due to miniaturization and high integration levels. Advanced circuits are susceptible to various faults including transient, permanent and intermittent types. Detecting and accurately diagnosing these faults remains major challenge due to signal complexity and noise. Therefore, this research proposes a novel model of Advanced Fault Diagnosis in Analog and Digital VLSI Circuits utilizing Optimized Multi-Anchor Space-Aware Temporal Convolutional Neural Network for Efficient Circuit Reliability Assessment (FDAD-VLSI- MSTCNN). The objective is to accurately detect and locate faults in analog and digital VLSI circuits to ensure reliable circuit performance. It aims to enhance circuit functionality by enabling optimal recovery of faulty designs. The proposed process begins with collecting input signals with frequency responses. The collected input signal is given to pre-processing using Robust Maximum Correntropy Kalman Filter (RMCKF) to remove noise. The Multidimensional Empirical Mode Decomposition (MEMD) is applied to decompose complex, non-stationary, nonlinear signals into simpler intrinsic mode functions (IMFs). These components undergo feature extraction using the Lifted Euler Characteristic Transform (LECT) extract mean, Standard Deviation (SD), kurtosis, skewness, Relative Entropy (RE), and minimum and maximum values features. Then, the extracted feature is given to Multi-Anchor Space-Aware Temporal Convolutional Neural Network (MSTCNN)to identify the fault locations for diagnosing fault in analog and digital VLSI circuits. The Divine Religions Algorithm (DRA) to recover the faulty circuit and restore normal circuit operation. Then the proposed FDAD-VLSI-MSTCNN is examined using performance metrics like Accuracy, Precision, Recall, F1-Score, Specificity, Receiver Operating Characteristic Curve (ROC), Computational Time and Execution Time. The proposed FDAD-VLSI-MSTCNN method provides 99.42 % higher accuracy, 98.34 % higher precision and 98.88 % higher recall while compared with existing methods like Soft fault detection in analog circuits using voltage feature extraction and supervised learning (SFDAC-VFE-SL), an investigation of extreme learning machine-based fault diagnosis to identify faulty components in analog circuits (FD-IFCAC-ELM) and detecting and classifying parametric faults in analog circuits using optimized attention neural networks (DCPF-AC-ANN) respectively.

模拟和数字超大规模集成电路（VLSI）的故障诊断是保证其可靠运行和性能的关键。由于小型化和高集成度，这些电路越来越复杂。高级电路易受各种故障的影响，包括瞬态、永久和间歇类型。由于信号的复杂性和噪声，检测和准确诊断这些故障仍然是一个重大挑战。因此，本研究提出了一种基于优化多锚点空间感知时序卷积神经网络（FDAD-VLSI- MSTCNN）的模拟和数字VLSI电路高级故障诊断新模型。目标是准确地检测和定位模拟和数字VLSI电路中的故障，以确保可靠的电路性能。它旨在通过实现故障设计的最佳恢复来增强电路功能。所提出的过程从收集具有频率响应的输入信号开始。采集到的输入信号通过鲁棒最大相关卡尔曼滤波（RMCKF）进行预处理，去除噪声。多维经验模态分解（MEMD）用于将复杂、非平稳、非线性信号分解为更简单的内禀模态函数（IMFs）。使用提升欧拉特征变换（LECT）提取平均值、标准差（SD）、峰度、偏度、相对熵（RE）以及最小值和最大值特征，对这些成分进行特征提取。然后，将提取的特征输入到多锚点空间感知时序卷积神经网络（MSTCNN）中进行故障定位，用于模拟和数字VLSI电路的故障诊断。通过DRA （Divine Religions Algorithm）算法恢复故障电路，使电路恢复正常运行。然后，使用准确度、精密度、召回率、f1评分、特异性、接受者工作特征曲线（ROC）、计算时间和执行时间等性能指标来检查所提出的FDAD-VLSI-MSTCNN。与现有的基于电压特征提取和监督学习（SFDAC-VFE-SL）的模拟电路软故障检测方法相比，本文提出的fdd - vlsi - mstcnn方法的准确率提高了99.42%，精密度提高了98.34%，召回率提高了98.88%。研究了基于极限学习机的模拟电路故障诊断方法（FD-IFCAC-ELM）和基于优化注意神经网络（DCPF-AC-ANN）的模拟电路参数故障检测与分类方法。

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引用次数: 0

EE DC-DB PFAL: A novel two-phase adiabatic logic family for low-power 14 nm FinFET-Based hybrid full adders EE DC-DB PFAL：一种新型的两相绝热逻辑系列，用于低功耗14nm基于finfet的混合全加法器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-11-24 DOI: 10.1016/j.vlsi.2025.102605

Sukhreet Kaur, Rita Mahajan, Deepak Bagai

This paper presents a novel hybrid 1-bit full adder design integrating 14 nm FinFET technology with a two-phase adiabatic logic family—Energy-Efficient Diode-Connected, DC-Biased Positive Feedback Adiabatic Logic (EE DC-DB PFAL)—and Modified Gate Diffusion Input (MGDI) logic. The proposed design achieves an average power consumption of 4.36 nW, a power-delay product of 1.26 aJ, and a transistor count of only 15, demonstrating significant energy efficiency and performance improvements compared to existing benchmark adder architectures. Transistor-level analysis, including Gm/Id considerations, validates optimized device sizing and energy-efficient switching. Layout and post-layout simulations confirm compact design and practical feasibility. The design demonstrates robustness under process, voltage, and temperature (PVT) variations, ensuring reliable operation across a wide range of operating conditions. Scalability across technology nodes from 7 nm to 20nm is demonstrated, and the methodology can be extended to multi-bit arithmetic units and full-scale ALUs. The proposed adder is particularly suitable for IoT edge nodes, wearable and biomedical devices, and portable communication processors.

本文提出了一种新型的混合1位全加法器设计，集成了14nm FinFET技术和两相绝热逻辑系列——节能二极管连接、直流偏置正反馈绝热逻辑（EE DC-DB PFAL）和改进的门扩散输入（MGDI）逻辑。该设计的平均功耗为4.36 nW，功率延迟积为1.26 aJ，晶体管数量仅为15，与现有基准加法器架构相比，显示出显著的能效和性能改进。晶体管级分析，包括Gm/Id考虑，验证了优化的器件尺寸和节能开关。布局和布局后仿真验证了紧凑的设计和实际的可行性。该设计在工艺、电压和温度（PVT）变化下具有稳健性，确保在各种操作条件下可靠运行。演示了从7纳米到20纳米的技术节点的可扩展性，并且该方法可以扩展到多位算术单元和全尺寸alu。该加法器特别适用于物联网边缘节点、可穿戴和生物医学设备以及便携式通信处理器。

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引用次数: 0

Design of CMOS current-mode multi-operand addition circuit based on carry stack 基于进位堆栈的CMOS电流型多操作数加法电路设计

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-12 DOI: 10.1016/j.vlsi.2025.102630

Maoqun Yao, Xiaole Zhang

This paper proposes a design method for current-mode multi-operand addition circuits. The approach temporarily stacks carry signals — which would typically be computed in subsequent stages — within the current stage, and employs a bit-by-bit modulus operation to calculate the remainder for each digit. The integer quotient is then propagated to higher digits, while the final result is composed of the remainders from all digits. Circuits designed using this method feature a shortened critical path in current-mode multi-operand addition and exhibit low hardware cost. In SPICE simulations, the proposed circuit achieved approximately 35% lower average power consumption compared to full-adders from relevant literature, along with higher operating speed and fewer transistors. Since inter-stage carry outputs can exceed the representation range of the current digit, current-mode signals between stages are allowed to surpass conventional logic limits, making it possible to further reduce cost by increasing internal logical values. A 15-operand summation circuit designed with this method demonstrated correct logical functionality, achieving a 52% reduction in transistor count and a 33% shortening of the critical path.

提出了一种电流型多操作数加法电路的设计方法。这种方法在当前阶段临时叠加信号（通常在后续阶段进行计算），并采用逐位模数运算来计算每个数字的余数。然后将整商传播到更高的数字，而最终结果由所有数字的余数组成。采用该方法设计的电路具有缩短电流模式多操作数加法的关键路径和低硬件成本的特点。在SPICE模拟中，与相关文献中的全加法器相比，所提出的电路的平均功耗降低了约35%，同时具有更高的工作速度和更少的晶体管。由于级间进位输出可以超过当前数字的表示范围，因此允许级间的电流模式信号超过常规逻辑限制，从而可以通过增加内部逻辑值来进一步降低成本。用这种方法设计的15个操作数求和电路显示出正确的逻辑功能，晶体管数量减少52%，关键路径缩短33%。

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引用次数: 0

First-order universal filters with two CCII+s and a grounded capacitor: Theory and experimental validation 具有两个CCII+s和一个接地电容的一阶通用滤波器：理论和实验验证

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-25 DOI: 10.1016/j.vlsi.2025.102642

Mehmet Dogan , Erkan Yuce , Shahram Minaei

In this study, two first-order voltage-mode universal filters based on the plus-type second-generation current conveyors (CCII+s) are proposed. Each filter employs two CCII+s, a grounded capacitor, and three resistors. Each filter exhibits the feature of universality, i.e., they realize low-pass filter, high-pass filter, and all-pass filter (APF) responses. Additionally, the APF responses offer electronically tunable gain through grounded resistors, eliminating the need for extra amplifier stages. Total harmonic distortion variations of the APFs are low. Dynamic ranges of the proposed filters are wide. However, they require a passive element matching condition and include two floating resistors. As application examples, two quadrature oscillators are presented. Extensive SPICE simulations are conducted using 180 nm TSMC technology parameters. Experimental validations are also carried out using commercially available AD844 active devices.

本文提出了两种基于加式二代电流传送带（CCII+s）的一阶电压型通用滤波器。每个滤波器采用两个CCII+s，一个接地电容和三个电阻。每个滤波器都具有通用性，即实现低通滤波器、高通滤波器和全通滤波器（APF）响应。此外，APF响应通过接地电阻提供电子可调谐增益，从而消除了额外放大器级的需要。apf的总谐波失真变化很小。所提出的滤波器的动态范围很广。然而，它们需要一个无源元件匹配条件，并包括两个浮动电阻。作为应用实例，给出了两个正交振荡器。采用180nm台积电技术参数进行了广泛的SPICE模拟。实验验证也使用市售AD844有源器件进行。

引用次数: 0

Achieving superior segmented CAM efficiency with pre-charge free local search based hybrid matcher for high speed applications 实现卓越的分段凸轮效率与预收费免费本地搜索为基础的混合匹配器高速应用

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-06 DOI: 10.1016/j.vlsi.2025.102621

Shyamosree Goswami , Adwait Wakankar , Partha Bhattacharyya , Anup Dandapat

This high-speed, power-efficient content addressable memory (CAM) uses parallel lookups to match quickly without sacrificing power consumption. It introduces three key contributions: i. Pre-charge free operation, which improves search speed and reduces power requirements by eliminating node charging time, ii. A Hybrid Match Line (HML) structure that strategically balances power and delay, combining the high-speed attributes of NOR with the low-power attributes of NAND, and iii. Local searching technique ascertain further improvement in search time. Performance indicators improve greatly when these methods are seamlessly integrated. Utilizing 45 nm CMOS technology, the design supports diverse process voltages, temperatures, and frequencies for a 64x32 memory array. Monte Carlo simulations verify design stability. The proposed architecture outperforms the leading benchmark in speed and power-delay-product (PDP) by 54.6% and 76.02%, respectively. This novel design can do repeated data searches at frequencies up to 2 GHz after a single write operation, enabling quicker and more energy-efficient data processing that could revolutionize consumer electronics. This development could revolutionize consumer electronics by improving efficiency and speed in high-performance computing, mobile devices, and IoT applications.

这种高速、节能的内容可寻址内存（CAM）使用并行查找来快速匹配，而不会牺牲功耗。它引入了三个关键贡献：1 .预充电自由操作，通过消除节点充电时间，提高搜索速度并降低功耗要求；混合匹配线（HML）结构，战略性地平衡了功率和延迟，结合了NOR的高速属性和NAND的低功耗属性；局部搜索技术进一步提高了搜索时间。当这些方法无缝集成时，性能指标将大大提高。该设计采用45纳米CMOS技术，支持64x32存储器阵列的各种工艺电压、温度和频率。蒙特卡罗仿真验证了设计的稳定性。该架构在速度和功率延迟积（PDP）方面分别优于领先基准54.6%和76.02%。这种新颖的设计可以在单次写入操作后以高达2 GHz的频率进行重复数据搜索，从而实现更快、更节能的数据处理，这可能会给消费电子产品带来革命性的变化。这一发展可以通过提高高性能计算、移动设备和物联网应用的效率和速度来彻底改变消费电子产品。

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引用次数: 0

Routability–wirelength co-guided cell inflation with explainable multi-task learning for global placement optimization 可达性-无线协同引导细胞膨胀与可解释的多任务学习，用于全局布局优化

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-12-01 DOI: 10.1016/j.vlsi.2025.102624

Yan Xing, Zicheng Deng, Shuting Cai, Weijun Li, Xiaoming Xiong

Existing routability-driven global placers typically employed an iterative routability optimization process and performed cell inflation based only on lookahead congestion maps during each run. However, this incremental application of congestion estimation and mitigation resulted in placement solutions that deviate from optimal wirelength, thus compromising the optimization objective of balancing wirelength minimization and routability optimization. To simultaneously improve routability and reduce wirelength, this paper proposes a novel routability–wirelength co-guided cell inflation approach for global placement optimization. It employs a multi-task learning-based feature selection method, MTL-FS, to identify the optimal feature subset and train the corresponding routability–wirelength co-learning model, RWNet. During the iterative optimization process, both routability and wirelength are predicted using RWNet, and their correlation is interpreted by DeepSHAP to produce three impact maps. Subsequently, routability–wirelength co-guided cell inflation (RWCI) is performed based on an adjusted congestion map, which is derived from the predicted congestion map and the three impact maps. The experimental results on ISPD2011 and DAC2012 benchmark designs demonstrate that, compared to DERAMPlace and RoutePlacer (which represent non-machine learning-based and machine learning-based routability-driven placers, respectively), the proposed approach achieves both better optimization quality, specifically improved routability and reduced wirelength, and a decreased time cost. Moreover, the extension experiment shows our method consistently outperforms DREAMPlace (even when it uses 2D feature maps as proxies) in effectiveness while maintaining comparable efficiency. The Generalization experiment further confirms this superiority and comparable runtime, particularly in highly congested scenarios.

现有的可达性驱动的全局放置器通常采用迭代的可达性优化过程，并且在每次运行期间仅基于前瞻拥塞图执行单元膨胀。然而，这种对拥塞估计和缓解的增量应用导致放置解决方案偏离最佳无线长度，从而损害了平衡无线长度最小化和可达性优化的优化目标。为了同时提高可达性和减少无线长度，本文提出了一种新的可达性-无线长度协同引导的蜂窝膨胀方法，用于全局布局优化。它采用基于多任务学习的特征选择方法MTL-FS来识别最优特征子集，并训练相应的路由-无线共同学习模型RWNet。在迭代优化过程中，使用RWNet预测可达性和无线长度，并通过DeepSHAP解释它们的相关性，生成三个影响图。随后，基于调整后的拥塞图（由预测的拥塞图和三个影响图导出）执行可达性-无线共同引导蜂窝膨胀（RWCI）。在ISPD2011和DAC2012基准设计上的实验结果表明，与DERAMPlace和RoutePlacer（分别代表非机器学习和基于机器学习的可达性驱动的放料器）相比，所提出的方法实现了更好的优化质量，特别是提高了可达性和缩短了无线长度，并且降低了时间成本。此外，扩展实验表明，我们的方法在保持相当效率的同时，在有效性上始终优于DREAMPlace（即使它使用2D特征映射作为代理）。泛化实验进一步证实了这种优越性和可比较的运行时间，特别是在高度拥塞的场景下。

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引用次数: 0

Higher-order filters based on the Mittag-Leffler function 基于Mittag-Leffler函数的高阶滤波器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-03-01 Epub Date: 2025-11-24 DOI: 10.1016/j.vlsi.2025.102607

Ahmed S. Elwakil , Brent J. Maundy , Anis Allagui , Costas Psychalinos

In this work, we show how higher-order low-pass, high-pass, band-pass or band-stop filter functions can be systematically obtained using the Mittag-Leffler (ML) function as a basic building block. In particular, by multiplying (i.e. cascading) two or more ML functions; each having the form of a two-parameter ML function

E_{α, β} (z)

(

0 \leq α, β \leq 1

) with its argument z being equal to

- s

or

- 1 /

s (

s

is the complex frequency; i.e.

s = j ω

), higher-order fractional filters can be obtained. We focus here on the cascade of two ML functions, which produces second-order transfer functions (as a special case) when

α = 0

and

β = 1

. We derive in closed form the impulse response and step-response of these filters and experimentally verify their behavior after approximating the ML function using a suitable integer-order approximation. It is worth mentioning that this class of filters does not employ the fractional-order Laplace operator

s^{\pm γ}

(

0 < γ \leq 1

), unlike classical fractional-order filters.

在这项工作中，我们展示了如何使用Mittag-Leffler （ML）函数作为基本构建块系统地获得高阶低通、高通、带通或带阻滤波器函数。特别是，通过乘法（即级联）两个或多个ML函数；各具有双参数ML函数Eα，β(z)（0≤α,β≤1）的形式，其参数z等于- s或- 1/s (s为复频率，即s=jω)，则可以得到高阶分数阶滤波器。我们在这里关注两个ML函数的级联，当α=0和β=1时，它产生二阶传递函数（作为特殊情况）。我们以封闭形式推导了这些滤波器的脉冲响应和阶跃响应，并在使用合适的整阶近似近似ML函数后实验验证了它们的行为。值得一提的是，这类滤波器不像经典的分数阶滤波器那样使用分数阶拉普拉斯算子s±γ (0<γ≤1)。

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引用次数: 0

MICSim: A modular pre-circuit simulator for mixed-signal compute-in-memory accelerators in CNNs and transformers MICSim：用于cnn和变压器中混合信号内存计算加速器的模块化预电路模拟器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-01 Epub Date: 2025-09-18 DOI: 10.1016/j.vlsi.2025.102543

Cong Wang, Zeming Chen, Shanshi Huang

This work introduces MICSim, an open-source, pre-circuit simulator designed to assist circuit designers to evaluate early-stage chip-level software performance and hardware overhead of mixed-signal compute-in-memory(CIM) accelerators. MICSim features a modular design, allowing easy multi-level co-design and design space exploration. Modularized from the state-of-the-art CIM simulator NeuroSim, MICSim provides a highly configurable simulation framework supporting multiple quantization algorithms, diverse circuit architecture designs, and different memory devices. This modular approach allows MICSim to be effectively extended to accommodate new designs.

MICSim natively enables evaluating accelerators’ software and hardware performance for convolutional neural networks (CNNs) and Transformers in Python, leveraging the popular PyTorch and Hugging Face Transformers frameworks. MICSim can be easily combined with optimization strategies to perform design space exploration and can be used for evaluating chip-level Transformers CIM accelerators, making it highly adaptable to different networks. Also, MICSim can achieve

9 \times \sim 32 \times

speedup of NeuroSim through a statistic-based average mode proposed by this work, without significant error across various networks. MICSim is available as an open-source tool on GitHub (https:// github.com/ MICSim-official/MICSim_V1.0.git).

这项工作介绍了MICSim，一个开源的预电路模拟器，旨在帮助电路设计人员评估混合信号内存计算（CIM）加速器的早期芯片级软件性能和硬件开销。MICSim采用模块化设计，可轻松实现多级协同设计和设计空间探索。从最先进的CIM模拟器NeuroSim模块化，MICSim提供了一个高度可配置的仿真框架，支持多种量化算法，多种电路架构设计和不同的存储设备。这种模块化方法允许MICSim有效地扩展以适应新的设计。MICSim原生地可以评估卷积神经网络（cnn）和Python中的transformer的加速器的软件和硬件性能，利用流行的PyTorch和hugs Face transformer框架。MICSim可以很容易地与优化策略相结合，进行设计空间探索，并可用于评估芯片级变压器CIM加速器，使其高度适应不同的网络。此外，通过本研究提出的基于统计的平均模式，MICSim可以实现神经sim的9倍~ 32倍的加速，并且在各种网络之间没有明显的误差。MICSim是GitHub上的开源工具（https:// github.com/ MICSim-official/MICSim_V1.0.git）。

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引用次数: 0

A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units 综合分析亚10nm CNFET技术对64位并行前缀加法器和32位矩阵乘法单元的影响

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-01 Epub Date: 2025-10-14 DOI: 10.1016/j.vlsi.2025.102583

Chenlin Shi , Tongxin Yang , Ryota Shioya , Hayato Yamaki , Hiroki Honda , Shinobu Miwa

In this paper, we provide the first thorough analysis of LSI circuits implemented using sub 10-nm carbon nanotube field effect transistors (CNFETs). Unlike many previous studies in which researchers performed the analysis of CNFET circuits at the SPICE level, we focus on netlists placed and routed using the state-of-the-art CNFET cell libraries. This approach enables us to analyze a more complex and wider range of CNFET circuits (i.e., various architectures that have the same functionality) than researchers in previous studies, while considering various effects of the circuits’ physical layout. Our experimental results demonstrate that, under comparable technology nodes, circuits implemented with CNFET technology can achieve superior performance compared to state-of-the-art 3-nm FinFET technology, exhibiting an energy-delay product (EDP) improvement of up to over 23

\times

for 64-bit Parallel Prefix Adders (PPAs) and up to over 18

\times

for 32-bit Matrix Multiply Units (MMUs). In addition, our analysis shows that the impact of both local and global wires on delay and energy consumption is more substantial in CNFET circuits than in FinFET circuits, and wire savings, which could lead to an EDP improvement of up to 49% in large-scale CNFET circuits, are therefore crucial for the optimization of the EDP of CNFET circuits, even with considering process variations. This study opens up a new opportunity to develop a wire-aware design for CNFET circuits.

在本文中，我们首次对使用亚10nm碳纳米管场效应晶体管（cnfet）实现的LSI电路进行了全面分析。与许多先前研究人员在SPICE级别对CNFET电路进行分析的研究不同，我们专注于使用最先进的CNFET细胞库放置和路由的网络列表。这种方法使我们能够分析比以前研究人员更复杂和更广泛的CNFET电路（即具有相同功能的各种架构），同时考虑电路物理布局的各种影响。我们的实验结果表明，在可比较的技术节点下，与最先进的3纳米FinFET技术相比，采用CNFET技术实现的电路可以实现卓越的性能，对于64位并行前缀加法器（PPAs），能量延迟积（EDP）提高了23倍以上，对于32位矩阵乘单元（mmu），能量延迟积（EDP）提高了18倍以上。此外，我们的分析表明，在CNFET电路中，局部和全局导线对延迟和能耗的影响比在FinFET电路中更大，并且在大规模CNFET电路中，节省导线可能导致EDP提高高达49%，因此对于优化CNFET电路的EDP至关重要，即使考虑到工艺变化。这项研究为CNFET电路的线感设计开辟了一个新的机会。

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引用次数: 0

A PSRR enhanced capacitorless LDO with gate capacitance cancellation technique 采用门电容对消技术的PSRR增强无电容LDO

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2026-01-01 Epub Date: 2025-10-01 DOI: 10.1016/j.vlsi.2025.102573

Hang Shu , Pengfei Liao , Yong Tao , Wensuo Chen

—Switching power supplies, characterized by significant power noise, can degrade the performance of display driver ICs, especially with switching frequencies ranging from hundreds of kilohertz to several megahertz. To minimize this power noise, low-dropout (LDO) regulators with high power supply rejection ratio (PSRR) are essential. This paper introduces a capacitorless LDO regulator that integrates a gate capacitance cancellation (GCC) technique for enhanced PSRR and a class-AB operational amplifier for improved transient response. Post-layout simulation results in 180-nm CMOS technology confirm the effectiveness of the proposed design. With an input voltage of 1.5 V, the LDO exhibits a settling time of only 0.15 μs under an undershoot voltage of 122.8 mV and 0.24 μs under an overshoot voltage of 92.8 mV. The proposed CL-LDO achieves a PSRR of −75.3 dB at 398 kHz, with a total on-chip capacitance as low as 8.8 pF. This design offers superior noise suppression and transient response, making it well-suited for applications requiring stable and clean power supply in noise-sensitive environments.

-开关电源的特点是显著的功率噪声，可以降低显示驱动ic的性能，特别是开关频率范围从数百千赫兹到几兆赫兹。为了尽量减少这种功率噪声，具有高电源抑制比（PSRR）的低差（LDO）稳压器是必不可少的。本文介绍了一种无电容LDO稳压器，该稳压器集成了用于增强PSRR的门电容抵消（GCC）技术和用于改善瞬态响应的ab类运算放大器。在180nm CMOS技术下的布局后仿真结果证实了所提设计的有效性。当输入电压为1.5 V时，LDO在122.8 mV欠调电压下的沉降时间仅为0.15 μs，在92.8 mV过调电压下的沉降时间仅为0.24 μs。所提出的CL-LDO在398 kHz时的PSRR为- 75.3 dB，片上总电容低至8.8 pF。该设计具有出色的噪声抑制和瞬态响应，非常适合在噪声敏感环境中需要稳定清洁电源的应用。

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引用次数: 0