Integration-The Vlsi Journal最新文献

A multi-segment nonlinear memristor model with controllable parameters is simplified significantly reducing circuit costs without compromising circuit performance. Different quantities of simplified memristor models are introduced into an improved Shimizu and Morioka (S-M) system, which constitute the one-directional memristive multiscroll chaotic attractor (1D-MMSCA) and the two-directional memristive multiscroll chaotic attractor (2D-MMSCA). Dynamical analysis is conducted from equilibrium points, Lyapunov exponents and bifurcation diagrams, Poincaré map, 0–1 tests, complexity, coexisting attractors, and National Institute of Standards and Technology (NIST) test. The Lyapunov exponents and bifurcation diagrams revealed that 1D-MMSCA exhibit rich dynamical behaviors, including fixed points, periodic orbits, transient quasi-periodic cycles, limit cycles, and period-doubling bifurcations. The 2D-MMSCA demonstrates simultaneous homogeneous and heterogeneous multi-stability and extreme multi-stability. Furthermore, an analog circuit is designed and simulated, and the results verify the circuit realizability and correctness of the MMSCAs. By utilizing an improved Euler algorithm and STM32 microcontroller, the implementation of MMSCAs are achieved, enhancing their applicability in the embedded systems domain. Finally, the drive-response synchronization constructed based on 1D-MMSCA exhibits a wide adjustable synchronization time, ranging from 49.3 s to 0.18 s. This significantly expands the application scope of the system. Additionally, a chaotic analog encrypted communication system has been developed using this synchronization framework. These advancements substantially enhance both the efficiency and practicality of the synchronization system.

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing the sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage ($V_{DDMIN}$). In this work, we first propose a model that describes a specific relationship between read current and leakage noise in a given column. Based on the model, Ultra8T SRAM is designed to aggressively reduce $V_{DDMIN}$ by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256 × 64 array in 28 nm CMOS technology. Post-simulation results show successful read operation at 0.25 V with 1.11 $\mu$s read delay, and the minimum energy required is 1.69 pJ at 0.4 V

In an era dominated by technology, the imperative for robust personal authentication in electronic information systems becomes increasingly evident. A secure and dependable solution to address this need is biometric authentication. Due to their intrinsic features of being universal, unique, and fraud-resistant, finger vein-based recognition systems have gained importance. Veins provide an efficient barrier against misleading methods since they are buried under the skin and undetectable to human sight. While many researchers focus on advanced technology for finger-vein-based authentication systems, existing research has often overlooked significant challenges, such as short datasets, high computational complexity, and a lack of efficient and lightweight feature descriptors. This paper proposes a unique method for automated Finger Vein Recognition (FVR) based on a fusion model known as “CNN-ViT” for FVR. Transfer learning-based Convolutional Neural Network (CNN) models, such as Inception-V3 and ResNet-50, compute the correlation of adjacent pixels to process texture-based features. Furthermore, shape-based features are processed using the vision transformer (ViT) model to determine the relationship between distant pixels. The combination of these three models enables the learning of textural features based on forms, contributing to more effective finger vein identification. In addition to our databases, we utilize two benchmark databases, FV-USM and SDUMLA-HMT, to validate our experiments. Our proposed approach achieves outstanding accuracy values of 99.95 %, 98.9 %, and 97.78 % on both the benchmark and our datasets. When compared to previous methods, the proposed Deep Learning (DL) model outperforms state-of-the-art models, demonstrating higher recognition rates and accuracy. To prototype the proposed FVR system, a Zynq XCZU4EV UltraScale + Multiprocessor System-On-Chip (MPSoC) was employed. The proposed model exhibits high throughput and competitive power efficiency, making it an excellent choice for scenarios where computing performance is critical, albeit utilizing more power and resources. This was established through a comprehensive examination of FPGA resource utilization and performance metrics.

This paper presents the development and evaluation of a 128 × 128 Readout Integrated Circuit (ROIC) prototype, engineered for Short-Wave Infrared (SWIR) imaging at a specific target wavelength of 2.6 μm. Employing silicon-level verification, this work undertook an exhaustive analysis of the ROIC's performance, identifying key areas for enhancement to improve SWIR imaging systems. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) Focal Plane Arrays (FPAs), facilitating high-resolution imaging. The prototype consumes 42.25 mW of power and achieves a frame rate of 390 frames per second. The fabricated chip show that the random noise level is 72.65 μVrms and Pixel-FPN is 21 LSBrms. This investigation lays a critical groundwork for future SWIR imaging advancements, providing valuable insights and methodologies to boost imaging performance in various applications.

This paper presents circuit for $2\times \text{VDD}$ signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for $2\times \text{VDD}$ signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.

A temperature self-adaptive ultra-high-resistance pseudo-resistor (PR) circuit is proposed for a wide range of biomedical applications. It acts as a relatively constant resistor over a wide temperature range (−40 °C–85 °C) due to its potential to compensate for the impact of the temperature-induced current. Hence, the performance of many biomedical analog intellectual property (IP) circuits can be effectively improved with temperature variations. The proposed circuit consists of a gate-voltage-controlled pseudo-resistor and a proportional-to- absolute-temperature (PTAT) circuit. Besides, its analysis and proof of concept with the self-adaptive scheme are presented. The circuit is designed in standard 0.18 μm CMOS technology and occupies a silicon area of 18.5 × 43.7 μm². It consumes 12 nW with a single power supply of 1.8 V. The post-layout simulation results demonstrate that the proposed pseudo-resistor could adequately improve the temperature-induced resistance variation by up to 18X while consuming ultra-low power and providing relatively high-temperature independence compared to the prior art.

In recent years, microfluidic biochips have been widely applied in various fields of human society. The optimization design of system-architecture based on continuous-flow microfluidic biochips has been widely studied. However, most previous work was based on the traditional chip architecture with dedicated storage, which not only limits the performance of biochips but also increases their manufacturing costs. In order to improve the execution efficiency and reduce the manufacturing cost, a distributed channel-storage architecture can be used to temporarily cache intermediate fluids in idle flow channels. Under this architecture, careful consideration of the volume management of the fluid to be cached is a prerequisite for ensuring the reliability of bioassay results. However, the existing work has not considered the volume management of the fluid to be cached in detail. This may cause the volume of the fluid to not match the capacity of the storage channel, which can contaminate other fluids and lead to incorrect bioassay results or increase the manufacturing cost of biochips due to long storage channels. In this paper, we propose a physical design method for microfluidic biochips that considers the actual volume of fluid while utilizing distributed channel storage. We address this problem by taking a placement and routing co-design strategy throughout the iterative process of the simulated annealing algorithm. Experimental results under multiple benchmarks show that the proposed method can effectively reduce the completion time of bioassays, minimize the flow path length, and decrease the number of intersections.

A mixed-logic design scheme utilizing pass-transistor logic (PTL) and dual-value logic (DVL) in combination with static CMOS logic for decoders in SRAMs is proposed. By using of the mixed-logic circuit, new n-Transistor (T) NAND/AND structures were provided for decoders, while achieving fewer transistors, faster speed, lower power dissipation as compared to traditional circuits, and having full-swing capability and good noise immunity. Experiments were conducted using TSMC 28 nm process for mixed-logic decoders, and the results show the superiority in terms of propagation delay and power dissipation, compared to the conventional corresponding circuits. A mixed-logic 2-4 decoder exhibits 36 % reduction in propagation delay and 10 % improvement in power dissipation; A mixed-logic 3-8 decoder exhibits 27 % reduction in propagation delay and 5.5 % improvement in power dissipation; While, A mixed-logic 4-16 decoder exhibits 30 % reduction in propagation delay and 5 % improvement in power dissipation; As well, A mixed-logic 5-32 decoder exhibits 34 % reduction in propagation delay and 6.3 % improvement in power dissipation.

This paper introduces the development and validation of a 64-channel readout integrated circuit (ROIC) prototype, specifically engineered for short-wave infrared (SWIR) line scan sensors. The design of the prototype undergoes various evaluation through comprehensive silicon-level testing, ensuring its robust performance across a variety of operational modes. Key features such as capacitive transimpedance amplifier (CTIA) gain control and sensitivity control are examined, demonstrating the prototype's ability to handle different input currents and capacitance values with precision. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) pixels, facilitating high-resolution imaging. The prototype consumes 26.55 mW with A 3.3 V power supply. The fabricated chip show that the total random noise (RN) level is 128 μV_rms and column fixed pattern noise (FPN) is 0.16 mV_rms

This research paper introduces a memory architecture that handles standard memory storage operations and enables in-memory computations, surpassing the capabilities of conventional SRAM bit-cells. The proposed architecture in this work effectively eliminates read-disturb issues and facilitates bit-wise operations like NAND, NOR, and XNOR, all without requiring intricate analog peripheral circuits. The suggested bit-cell architecture offers enhanced throughput compared to existing In-Memory Computing (IMC) bit-cell architectures, making it a more suitable design for IMC applications. Parallelism offers enhanced throughput due to the unique bit-cell architecture, which allows all the bit-wise operations to be achieved simultaneously in a single cycle. The validity of the suggested architecture has been confirmed through Monte-Carlo variation analysis, utilizing UMC 28 nm PDK transistor models to ensure its robustness. Furthermore, architecture is benchmarked using the CIFAR-10 dataset, which entails assessing its performance across various machine learning models via the NeuroSim Simulator. The proposed architecture offers a substantial increase of up to 40 % in throughput (TOPS/W) compared to the existing architectures. Utilizing accurate Monte-Carlo simulations with 1000 samples, the stability of the proposed 10T bit-cell is validated at worst-case PVT corners, up to 6σ variations.