Integration-The Vlsi Journal最新文献

英文中文

Lightweight high-throughput true random number generator based on state switchable ring oscillator 基于状态可切换环形振荡器的轻量级高吞吐量真随机数发生器

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-11-09 DOI: 10.1016/j.vlsi.2024.102305

Shehui Wu, Huaguo Liang, Siyu Wang, Hao Lv, Maoxiang Yi, Yingchun Lu

True random number generators (TRNGs) perform an extremely critical role in cryptographic algorithms and security protocols, scientific simulation, industrial testing, privacy protection, and numerous other domains. Nevertheless, modern TRNGs have difficulty striking a reasonable balance between high throughput and low hardware consumption. In this paper, a novel lightweight high-throughput TRNG based on state switchable ring oscillators (SSROs) is proposed. Under the effect of flip-flops that are prone to entering the metastable region, the SSROs randomly switch between oscillatory and buffer states to create jitter and metastability. A feedback strategy is adopted to effectively eliminate the fixed point in the circuit, which further enhances the randomness of the structure. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs, with support for automatic routing. It achieves a throughput of up to 400 Mbps while consuming only 16 LUTs and 13 DFFs, showing extremely high resource utilization efficiency. Experimental results show that the output random sequence passes the NIST SP800-22 test, the NIST SP800-90B test, and the AIS-31 test without any post-processing, exhibiting strong robustness against voltage and temperature variations as well as frequency injection attacks.

真随机数发生器（TRNG）在加密算法和安全协议、科学模拟、工业测试、隐私保护等众多领域发挥着极其重要的作用。然而，现代 TRNG 难以在高吞吐量和低硬件消耗之间取得合理平衡。本文提出了一种基于状态可切换环形振荡器（SSRO）的新型轻量级高吞吐量 TRNG。在容易进入可变区的触发器的作用下，SSRO 在振荡态和缓冲态之间随机切换，从而产生抖动和可变性。采用反馈策略可有效消除电路中的固定点，从而进一步增强结构的随机性。所提出的 TRNG 在 Xilinx Artix-7 和 Kintex-7 FPGA 上实现，并支持自动路由。它实现了高达 400 Mbps 的吞吐量，同时仅消耗 16 个 LUT 和 13 个 DFF，显示出极高的资源利用效率。实验结果表明，输出随机序列无需任何后处理即可通过 NIST SP800-22 测试、NIST SP800-90B 测试和 AIS-31 测试，对电压和温度变化以及频率注入攻击具有很强的鲁棒性。

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引用次数: 0

A low noise instrument amplifier in 40 nm CMOS with positive feedback loop and DC servo loop for neural signal acquisition 40 nm CMOS 低噪声仪器放大器，带用于神经信号采集的正反馈回路和直流伺服回路

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-11-06 DOI: 10.1016/j.vlsi.2024.102304

Shuoshuo Zhu, Bin Wang, Xiaokun Lin, Lu Liu, Xiao Qu, Weitao Yang

This paper presents a low-noise instrument amplifier (LNA) for neural signal acquisition. The proposed LNA consists of two operational transconductance amplifiers (OTA), feedback loops, a positive feedback loop (PFL), a DC servo loop (DSL) and the internal chopper switch located between the capacitive feedback loop and op-amp. The LNA employs the capacitively coupled amplifier with the internal chopper to obtain the rail to rail electrode dc offset (EDO) rejection ability and eliminate the flicker noise of OTA. The PFL is designed to improve the input impedance of the circuit, and the DSL is introduced to suppress the residual offset introduced by the chopper switch. Realized in a 40 nm CMOS technology with 0.69 × 0.1 mm², the LNA draws 7.4 μA from a supply voltage of 2.5Vand exhibits 1.69 μVrms input-referred noise (IRN) over 1–200 Hz for low frequency and low amplitude neural signals. Besides, the simulation results show that the LNA achieves 87.12 dB common-mode rejection ratio (CMRR), 87.64 dB power-supply rejection ratio (PSRR) and 2.75 GΩ input impedance at 50 Hz.

本文介绍了一种用于神经信号采集的低噪声仪器放大器（LNA）。拟议的 LNA 由两个运算跨导放大器 (OTA)、反馈环路、正反馈环路 (PFL)、直流伺服环路 (DSL) 以及位于电容反馈环路和运算放大器之间的内部斩波开关组成。LNA 采用带内部斩波器的电容耦合放大器，以获得轨至轨电极直流偏移 (EDO) 抑制能力，并消除 OTA 的闪烁噪声。PFL 的设计旨在改善电路的输入阻抗，而 DSL 的引入则是为了抑制斩波器开关引入的残余偏移。该 LNA 采用 0.69 × 0.1 mm2 的 40 nm CMOS 技术实现，电源电压为 2.5 V，电流为 7.4 μA，在 1-200 Hz 频率范围内，对于低频、低振幅神经信号的输入参考噪声（IRN）为 1.69 μVrms。此外，仿真结果表明，该 LNA 在 50 Hz 时实现了 87.12 dB 的共模抑制比 (CMRR)、87.64 dB 的电源抑制比 (PSRR) 和 2.75 GΩ 的输入阻抗。

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引用次数: 0

An enhanced key expansion module based on 2D hyper chaotic map and Galois field 基于二维超混沌图和加洛瓦场的增强型密钥扩展模块

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-11-05 DOI: 10.1016/j.vlsi.2024.102302

Yafei Cao, Hongjun Liu

Key expansion is an essential component in block cryptography, which serves the round function. By analyzing key expansion module of AES, it is found that the round-keys are highly correlated, and current round-key can be derived from its previous or the next round-key. To address these weaknesses, first, a 2D exponential chaotic map (2D-ECM) that exhibits ergodicity and superior randomness was constructed. Then, the Lyapunov exponents (LEs) were calculated based on the singular value decomposition (SVD) method. In addition, TestU01 test results showed that the sequences generated by 2D-ECM have better randomness. Further, an enhanced key expansion module was designed utilizing 2D-ECM and primitive polynomial over GF(2ⁿ), which has irreversibility and parallelism, and the round-keys are independent of each other. Simulation results and performance analysis demonstrated the effectiveness of the proposed enhanced key expansion module.

密钥扩展是块密码学的重要组成部分，它具有轮询功能。通过分析 AES 的密钥扩展模块，可以发现轮密钥具有高度相关性，当前轮密钥可以从其上一轮或下一轮密钥中推导出来。针对这些弱点，首先构建了一种具有遍历性和超强随机性的二维指数混沌图（2D-ECM）。然后，根据奇异值分解（SVD）方法计算了李亚普诺夫指数（LE）。此外，TestU01 测试结果表明，2D-ECM 生成的序列具有更好的随机性。此外，利用 2D-ECM 和 GF(2n)上的基元多项式设计了一个增强型密钥扩展模块，该模块具有不可逆性和并行性，且圆密钥相互独立。仿真结果和性能分析表明了所提出的增强型密钥扩展模块的有效性。

引用次数: 0

Simple memristive chaotic systems with complex dynamics 具有复杂动力学的简单记忆混沌系统

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-11-05 DOI: 10.1016/j.vlsi.2024.102301

You Lü , Qiang Lai , Jianning Huang

The exploration of memristive chaotic systems (MCSs) has been a prominent area of research due to the inherent richness of their dynamical characteristics. The objective of this paper is to propose two chaotic systems, derived from a common basic system, which also exhibit distinct characteristics such as coexisting attractors and robustness of chaos while maintaining the common attributes of multi-parameter amplitude modulation and large-scale offset boosting. The evolution process of MCSs' dynamical behavior with changes to parameters and initial values is described in detail through the analysis of bifurcation diagrams, Lyapunov exponents (LEs), and phase projections. Furthermore, the findings of the numerical simulations are validated by circuit implementations, thereby providing additional confirmation of the existence of the two memristive chaotic systems constructed and their potential for practical applications.

由于记忆混沌系统（MCS）固有的丰富动态特性，对其进行探索一直是一个突出的研究领域。本文旨在提出两个混沌系统，它们源自一个共同的基本系统，在保持多参数振幅调制和大规模偏移增强等共同属性的同时，还表现出共存吸引子和混沌鲁棒性等显著特点。通过分析分岔图、李亚普诺夫指数（LE）和相位投影，详细描述了 MCS 随参数和初始值变化的动力学行为演变过程。此外，数值模拟的结果通过电路实现得到了验证，从而进一步证实了所构建的两个记忆混沌系统的存在及其实际应用的潜力。

引用次数: 0

Model and system robustness in distributed CNN inference at the edge 边缘分布式 CNN 推断中的模型和系统鲁棒性

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-10-20 DOI: 10.1016/j.vlsi.2024.102299

Xiaotian Guo , Quan Jiang , Andy D. Pimentel , Todor Stefanov

Prevalent large CNN models pose a significant challenge in terms of computing resources for resource-constrained devices at the Edge. Distributing the computations and coefficients over multiple edge devices collaboratively has been well studied but these works generally do not consider the presence of device failures (e.g., due to temporary connectivity issues, overload, discharged battery of edge devices). Such unpredictable failures can compromise the reliability of edge devices, inhibiting the proper execution of distributed CNN inference. In this paper, we present a novel partitioning method, called RobustDiCE, for robust distribution and inference of CNN models over multiple edge devices. Our method can tolerate intermittent and permanent device failures in a distributed system at the Edge, offering a tunable trade-off between robustness (i.e., retaining model accuracy after failures) and resource utilization. We verify the system’s robustness by validating the overall end-to-end latency under failures. We evaluate RobustDiCE using the ImageNet-1K dataset on several representative CNN models under various device failure scenarios and compare it with several state-of-the-art partitioning methods as well as an optimal robustness approach (i.e., full neuron replication). In addition, we demonstrate RobustDiCE’s advantages in terms of memory usage and energy consumption per device, and system throughput for various system setups with different device counts.

对于资源有限的边缘设备来说，普遍的大型 CNN 模型对计算资源构成了巨大挑战。在多个边缘设备上协同分配计算和系数的问题已经得到了很好的研究，但这些工作通常没有考虑设备故障的存在（例如，由于临时连接问题、过载、边缘设备电池放电）。这种不可预知的故障会损害边缘设备的可靠性，阻碍分布式 CNN 推断的正常执行。在本文中，我们提出了一种名为 RobustDiCE 的新型分区方法，用于在多个边缘设备上对 CNN 模型进行稳健的分布和推理。我们的方法可以容忍边缘分布式系统中的间歇性和永久性设备故障，在鲁棒性（即故障后保持模型准确性）和资源利用率之间提供可调整的权衡。我们通过验证故障情况下的整体端到端延迟来验证系统的鲁棒性。我们使用 ImageNet-1K 数据集评估了 RobustDiCE 在各种设备故障情况下对几个具有代表性的 CNN 模型的处理效果，并将其与几种最先进的分区方法以及一种最佳鲁棒性方法（即全神经元复制）进行了比较。此外，我们还展示了 RobustDiCE 在每个设备的内存使用和能耗方面的优势，以及在不同设备数量的各种系统设置下的系统吞吐量。

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引用次数: 0

VLFF — A very low-power flip-flop with only two clock transistors VLFF - 仅有两个时钟晶体管的超低功耗触发器

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-10-19 DOI: 10.1016/j.vlsi.2024.102300

Yugal Kishore Maheshwari, Manoj Sachdev

Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively.

触发器（FF）是数字电路的重要组成部分，但其功耗和能耗却很高。本文介绍了 VLFF，一种仅使用两个单相时钟晶体管运行的超低功耗触发器。提取的仿真结果表明，在 0% 至 45% 的数据活动（DA）范围内，VLFF 是所有受检 FF 中最省电的 FF。采用 TSMC CMOS 65 nm gp PDK 设计的测试芯片测量结果表明，在 VDD = 1 V 时，与 TGFF 和 18TSPC 相比，12.5% DA 的功耗分别降低了 63% 和 16%，25% DA 的功耗分别降低了 52% 和 6%。

引用次数: 0

Efficient and cost-effective maximum power point tracking technique for solar photovoltaic systems with Li-ion battery charging 针对锂离子电池充电太阳能光伏系统的高效、经济的最大功率点跟踪技术

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-10-13 DOI: 10.1016/j.vlsi.2024.102298

Salam J. Yaqoob , Salah Kamel , Francisco Jurado , Saad Motahhir , Abdelilah Chalh , Husam Arnoos

This paper presents an effective approach to achieve maximum power point tracking (MPPT) in photovoltaic (PV) systems for battery charging using a single-sensor incremental conductance (InC) method. The objective is to optimize the MPPT process while minimizing the number of sensors required. The suggested technique leverages the relationship between the PV module's output voltage and the duty cycle to automatically adjust and reach the MPP, resulting in optimal power generation. By eliminating the PV current sensor from the control circuit, the developed method reduces both the cost and size of the MPPT circuit. Compared to the conventional InC method, the developed approach demonstrates improved response speed and accuracy in steady-state operation, along with the ability to damp oscillations near the MPP. Extensive simulations using MATLAB/Simulink validate the performance of the developed technique across various environmental conditions. The results highlight the recommended method's realistic and effective MPP tracking capabilities, achieving higher efficiency (99.12 %) compared to the classical method (97.8 %) under high irradiance levels.

本文提出了一种有效的方法，利用单传感器增量电导（InC）方法实现光伏（PV）系统中的最大功率点跟踪（MPPT），为电池充电。目标是优化 MPPT 过程，同时尽量减少所需的传感器数量。所建议的技术利用光伏模块输出电压与占空比之间的关系，自动调整并达到 MPP，从而实现最佳发电效果。通过消除控制电路中的光伏电流传感器，所开发的方法降低了 MPPT 电路的成本和体积。与传统的 InC 方法相比，所开发的方法提高了稳态运行的响应速度和精度，并能抑制 MPP 附近的振荡。使用 MATLAB/Simulink 进行的大量仿真验证了所开发技术在各种环境条件下的性能。结果凸显了所推荐方法真实有效的 MPP 跟踪能力，在高辐照度条件下，与传统方法（97.8%）相比，效率更高（99.12%）。

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引用次数: 0

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance 新型混合 TFET-FinFET 12T SRAM 单元，可提高写入裕度和读取性能

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-10-10 DOI: 10.1016/j.vlsi.2024.102294

Seyed Arman Sabaghpour, Behzad Ebrahimi, Pooya Torkzadeh

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across V_DD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.

这项研究提出了两种结合隧道场效应晶体管（TFET）和鳍式场效应晶体管（FinFET）技术的创新型 12T 单元。这些单元通过为读取数据和写入增强型切割晶体管整合独立路径、增强保持/读取/写入静态噪声裕度 (H/R/WSNM)、缩短读取时间以及最大限度降低 TFET 漏电功耗，解决了反向偏置电流问题。在 0.6 V 电压下，第一（第二）SRAM 单元的 WSNM 比 O_7T、8T、CA_10T、12T 和 HF_10T 单元分别提高了 152 %（93 %）、152 %（93 %）、157.7 %（97.5 %）、95 %（50 %）和 104 %（57 %）。第一个（第二个）12T TFET SRAM 单元的漏功率比 O_7T 和 8T SRAM 单元低两（四）个数量级。与 12T 和 CA_10T SRAM 相比，这些混合 SRAM 单元的读取操作速度更快，跨 VDD 电压电平（0.3 V-1 V），第一个 12T 单元的写入访问时间更短。这些特性使拟议的单元特别适用于高能效物联网设备和医疗应用，在这些应用中，平衡功耗、面积、性能和数据完整性至关重要。

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引用次数: 0

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection 基于时延神经网络和遗传算法特征选择的流水线 ADC 数字背景校准算法

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-10-10 DOI: 10.1016/j.vlsi.2024.102295

Yongsheng Yin, Long Li, Jiashen Li, Yukun Song, Honghui Deng, Hongmei Chen, Luotian Wu, Muqi Li, Xu Meng

This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm². Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.

本文针对流水线模数转换器 (ADC) 提出了一种新型背景校准方法，该方法使用时延神经网络 (TDNN)，并通过遗传算法 (GA) 技术进行了优化。所提出的技术利用 TDNN 创建增强型特征集，显著改善了表现出记忆效应的非线性误差的校准。它利用遗传算法的全局优化能力进行特征选择，有效降低了特征维度，从而减轻了 NN 的计算负担。为校准电路设计了并行流水线架构，并在 FPGA 上实现，以方便前向推理处理。推理电路采用台积电 90 纳米 CMOS 工艺合成，功耗为 40.11 mW，面积为 0.45 mm2。基于 MATLAB 的 14 位流水线 ADC 仿真表明，所提出的校准方法显著提高了 SFDR，从 59.77 dB 提高到 165.52 dB，ENOB 从 8.79 bits 提高到 19.23 bits，超过了目标 ADC 的规格。此外，在不影响校准性能的情况下，特征维数有效降低了 34%。

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引用次数: 0

A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques 采用 DFVF 和混合级联补偿技术设计的新型高性能全差分两级 RFC OTA 架构

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2024-10-10 DOI: 10.1016/j.vlsi.2024.102296

Annu Dabas , Shweta Kumari , Maneesha Gupta , Richa Yadav

In this work, a novel fully differential two stage class AB Recycling Folded Cascode Operational Transconductance Amplifier (RFC OTA) using Differential Flipped Voltage Follower (DFVF) has been proposed. The DFVF and Dynamic Threshold Metal Oxide Semiconductor (DTMOS) transistors have been used as differential input stage of the proposed RFC OTA. These techniques provide enhancement in gain and bandwidth of the proposed OTA. To further improve the performance of proposed circuit, positive feedback at current mirror load along with Hybrid Cascode compensation have been implemented. A common source (CS) amplifier has been used between gate and source terminals of differential input stage which further boosts the transconductance. The proposed RFC OTA is designed and simulated using 180 nm CMOS technology with load capacitance of 10 pF. It provides an excellent dc gain of 112.61 dB and gain bandwidth product (GBW) of 25.88 MHz along with 88.14⁰ phase margin. The proposed circuit dissipates 124.66 μW of power at ± 0.5V supply voltage. The Monte Carlo analysis against device mismatch has also been performed to prove robustness of the proposed circuit.

本研究提出了一种使用差分翻转电压跟随器（DFVF）的新型全差分两级 AB 类回收折叠级联运算跨导放大器（RFC OTA）。DFVF 和动态阈值金属氧化物半导体（DTMOS）晶体管被用作拟议 RFC OTA 的差分输入级。这些技术提高了拟议 OTA 的增益和带宽。为了进一步提高拟议电路的性能，在电流镜负载上实施了正反馈以及混合级联补偿。在差分输入级的栅极和源极之间使用了共源（CS）放大器，从而进一步提高了跨导。拟议的 RFC OTA 采用 180 nm CMOS 技术设计和仿真，负载电容为 10 pF。它的直流增益高达 112.61 dB，增益带宽积 (GBW) 为 25.88 MHz，相位裕度为 88.140。在 ± 0.5V 电源电压下，拟议电路的耗散功率为 124.66 μW。此外，还针对器件失配进行了蒙特卡罗分析，以证明所提电路的稳健性。

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引用次数: 0

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