Integration-The Vlsi Journal最新文献_第7页

A comparative study on formal verification techniques to verify large integer multiplier circuits 大整数乘法器电路形式化验证技术的比较研究

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-20 DOI: 10.1016/j.vlsi.2025.102606

Jitendra Kumar , Asutosh Srivastava , Masahiro Fujita

Arithmetic circuits are the fundamental building blocks of circuitry with applications including digital signal processing, cryptography processors, and multimedia. Integer multiplier circuits with high bit width of the operands dominate the extensive circuitry area of new-generation technologies. Traditionally, various multiplication algorithms are available to generate multiplier circuits considering area, delay, and power. Custom optimization is performed to reduce the circuit size, which increases the probability of logical bugs in the design. In the past over thirty years, prominent formal verification techniques such as Satisfiability (SAT) checking, Binary Decision Diagram (BDD), and Symbolic Computer Algebra (SCA) made massive progress in analyzing the correctness of the circuits. In this paper, we study the best state-of-the-art techniques from each method available in the academic domain and perform a comparative analysis to verify integer multiplier circuits with different architectures after logic optimization. Although the complexity of BDDs is constantly exponential with the input size of the circuit, and BDDs can be constructed only up to 18 bits, the method is robust to verify a variety of multiplier structures. Algebraic backward rewriting based on Symbolic Computer Algebra (SCA) facilitates the formal verification of high-bit-width multiplier circuits. Conventional approaches that leverage hierarchical structural information are constrained to algebraic-friendly multipliers, wherein adder sub-circuits are preserved in their canonical form, an assumption often invalidated post logic synthesis and optimization. In contrast, advanced algebraic techniques that operate directly on flattened net-lists demonstrate scalability and robustness in verifying large multiplier designs. Formal analysis with straightforward SAT techniques does not work well for comparing two structural non-similar circuits, which is often the case after applying logic optimization. If the degree of similarity is not excessively low, SAT-Sweeping can effectively reduce structural non-similarity, and SAT techniques can verify multipliers up to 512 bits. However, the verification of complex circuits, characterized by their non-algebraic-friendly nature, near-zero similarity to reference circuits, and larger input sizes, remains an open challenge.

算术电路是电路的基本组成部分，其应用包括数字信号处理、密码处理器和多媒体。具有高操作数位宽的整数乘法器电路在新一代技术的广泛电路领域占据主导地位。传统上，考虑到面积、延迟和功耗，各种乘法算法可用于生成乘法器电路。执行自定义优化以减小电路尺寸，这增加了设计中逻辑错误的概率。在过去的三十多年里，主要的形式化验证技术如可满足性（Satisfiability， SAT）检查、二进制决策图（Binary Decision Diagram， BDD）和符号计算机代数（Symbolic Computer Algebra， SCA）在分析电路正确性方面取得了巨大的进步。在本文中，我们研究了学术领域中每种方法中最先进的技术，并进行了比较分析，以验证逻辑优化后具有不同架构的整数乘法器电路。虽然bdd的复杂度随电路的输入尺寸呈指数增长，并且bdd最多只能构造18位，但该方法对于验证各种乘法器结构具有鲁棒性。基于符号计算机代数（SCA）的代数反向重写简化了高位宽乘法器电路的形式化验证。利用分层结构信息的传统方法仅限于代数友好的乘法器，其中加法子电路以其规范形式保存，这一假设通常在逻辑综合和优化后无效。相比之下，直接在扁平网表上操作的先进代数技术在验证大型乘法器设计方面表现出可扩展性和鲁棒性。使用直接的SAT技术进行形式分析，对于比较两个结构上不相似的电路，效果并不好，这是应用逻辑优化后经常出现的情况。如果相似度不是太低，SAT- sweep可以有效地减少结构不相似，并且SAT技术可以验证最多512位的乘法器。然而，复杂电路的验证，其特点是非代数友好的性质，与参考电路接近零的相似性，更大的输入尺寸，仍然是一个开放的挑战。

{"title":"A comparative study on formal verification techniques to verify large integer multiplier circuits","authors":"Jitendra Kumar , Asutosh Srivastava , Masahiro Fujita","doi":"10.1016/j.vlsi.2025.102606","DOIUrl":"10.1016/j.vlsi.2025.102606","url":null,"abstract":"<div><div>Arithmetic circuits are the fundamental building blocks of circuitry with applications including digital signal processing, cryptography processors, and multimedia. Integer multiplier circuits with high bit width of the operands dominate the extensive circuitry area of new-generation technologies. Traditionally, various multiplication algorithms are available to generate multiplier circuits considering area, delay, and power. Custom optimization is performed to reduce the circuit size, which increases the probability of logical bugs in the design. In the past over thirty years, prominent formal verification techniques such as Satisfiability (SAT) checking, Binary Decision Diagram (BDD), and Symbolic Computer Algebra (SCA) made massive progress in analyzing the correctness of the circuits. In this paper, we study the best state-of-the-art techniques from each method available in the academic domain and perform a comparative analysis to verify integer multiplier circuits with different architectures after logic optimization. Although the complexity of BDDs is constantly exponential with the input size of the circuit, and BDDs can be constructed only up to 18 bits, the method is robust to verify a variety of multiplier structures. Algebraic backward rewriting based on Symbolic Computer Algebra (SCA) facilitates the formal verification of high-bit-width multiplier circuits. Conventional approaches that leverage hierarchical structural information are constrained to algebraic-friendly multipliers, wherein adder sub-circuits are preserved in their canonical form, an assumption often invalidated post logic synthesis and optimization. In contrast, advanced algebraic techniques that operate directly on flattened net-lists demonstrate scalability and robustness in verifying large multiplier designs. Formal analysis with straightforward SAT techniques does not work well for comparing two structural non-similar circuits, which is often the case after applying logic optimization. If the degree of similarity is not excessively low, SAT-Sweeping can effectively reduce structural non-similarity, and SAT techniques can verify multipliers up to 512 bits. However, the verification of complex circuits, characterized by their non-algebraic-friendly nature, near-zero similarity to reference circuits, and larger input sizes, remains an open challenge.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102606"},"PeriodicalIF":2.5,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145572012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Adaptive congestion-aware high performance scalable 2-D and 3-D topologies for network-on-chip based interconnect for quantum computing 用于量子计算的片上网络互连的自适应拥塞感知高性能可扩展二维和三维拓扑

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-20 DOI: 10.1016/j.vlsi.2025.102597

Jayshree , Gopalakrishnan Seetharaman , Jitendra Kumar

This work presents challenges and solutions of global interconnect in Network-on-Chip (NoC) based System-on-Chips (SoCs) for congestion-free communication between different quantum accelerators in quantum computing systems. To address these problems, we have proposed two novel topologies in two-dimensional (2-D) and four topologies in three-dimensional (3-D). These topologies are based on two different architectural connection methods. The first two are the hybrid connection of the ring-of-mesh, with partial-diagonal-link (HMRPD) in 2-D and 3-D, and the other two are the hybrid connection of the ring-of-torus, with partial-diagonal-link (HTRPD) in 2-D and 3-D. Initially, the parametric analysis performed for both 2-D topologies and result shows that the interconnect has less diameter and average distance, which leads to reduce latency. It requires a small node degree, which makes it more accessible to design a network. It has a high bisection bandwidth, which helps in achieving low communication cost and high throughput. The scalability is higher than that of another existing interconnect. Further, we have examined the throughput, packet latency, and energy consumption of the interconnect for performance comparison of topologies under synthetic traffic patterns. We found that the proposed technique improves performance, optimizes communication cost, and energy consumption. Next, the 2-D HMRPD and 2-D HTRPD extended to 3-D symmetric network architectures by appending two additional ports in 2-D router architectures, namely up port and down port, and connecting these ports by Through Silicon Via (TSV), and routing of packets performed by a quasi-minimal routing technique. The result shows that these 3-D HMRPD and HTRPD have better performance than the 2-D HMRPD, 2-D HTRPD, and existing topologies. Unfortunately, these 3-D topologies result in extra energy consumption issues. Therefore, to solve this issue, heterogeneous layout of 2-D and 3-D router integration techniques applied in 3-D topologies for reducing number of TSV. Furthermore, we have presented two 3-D HTRPD topologies with TSV optimized and compared them with a full TSV-connected 3-D HTRPD. We found that 1P-3DR-HTRPD topology has the lowest gate count, area, dynamic, and static power consumption in comparison to fully connected 3-D HTRPD topology. This work has been designed by modifying network system simulator and also implemented in the Xc7z020clg484-1 ZYNQ FPGA device for validation. Furthermore, we have also examined that these 2-D topologies are more area-efficient and require a maximum crossbar size of 6x6 and have a high frequency of 2.29 GHz and 2.22 GHz for 2-D HMRPD and 2-D HTRPD, respectively, in comparison to other diagonal link topologies.

本研究提出了在基于片上网络（NoC）的片上系统（soc）中实现量子计算系统中不同量子加速器之间无拥塞通信的全局互连的挑战和解决方案。为了解决这些问题，我们提出了两种新的二维拓扑（2-D）和四种三维拓扑（3-D）。这些拓扑基于两种不同的体系结构连接方法。前两种是网格环的混合连接，具有二维和三维的部分对角连接（HMRPD），另外两种是环面环的混合连接，具有二维和三维的部分对角连接（HTRPD）。首先，对二维拓扑进行了参数分析，结果表明互连的直径和平均距离较小，从而减少了延迟。它需要较小的节点度，这使得设计网络更容易。它具有很高的对分带宽，有助于实现低通信成本和高吞吐量。可扩展性高于现有的另一种互连。此外，我们还检查了互连的吞吐量、数据包延迟和能耗，以便在综合流量模式下对拓扑结构进行性能比较。我们发现所提出的技术提高了性能，优化了通信成本和能耗。接下来，二维HMRPD和二维HTRPD扩展到三维对称网络架构，通过在二维路由器架构中附加两个额外的端口，即上行端口和下行端口，并通过通过硅孔（TSV）连接这些端口，并通过准最小路由技术进行分组路由。结果表明，这些三维HMRPD和HTRPD比二维HMRPD、二维HTRPD和现有拓扑具有更好的性能。不幸的是，这些3-D拓扑会导致额外的能源消耗问题。因此，为了解决这一问题，将二维和三维路由器集成的异构布局技术应用于三维拓扑中，以减少TSV的数量。此外，我们提出了两种优化了TSV的3-D HTRPD拓扑，并将其与完整的TSV连接的3-D HTRPD进行了比较。我们发现，与完全连接的3-D HTRPD拓扑相比，1P-3DR-HTRPD拓扑具有最低的栅极数、面积、动态和静态功耗。该工作通过修改网络系统模拟器进行设计，并在Xc7z020clg484-1 ZYNQ FPGA器件上实现验证。此外，我们还研究了与其他对角链路拓扑相比，这些二维拓扑具有更高的面积效率，要求最大横条尺寸为6x6，并且二维HMRPD和二维HTRPD分别具有2.29 GHz和2.22 GHz的高频。

{"title":"Adaptive congestion-aware high performance scalable 2-D and 3-D topologies for network-on-chip based interconnect for quantum computing","authors":"Jayshree , Gopalakrishnan Seetharaman , Jitendra Kumar","doi":"10.1016/j.vlsi.2025.102597","DOIUrl":"10.1016/j.vlsi.2025.102597","url":null,"abstract":"<div><div>This work presents challenges and solutions of global interconnect in Network-on-Chip (NoC) based System-on-Chips (SoCs) for congestion-free communication between different quantum accelerators in quantum computing systems. To address these problems, we have proposed two novel topologies in two-dimensional (2-D) and four topologies in three-dimensional (3-D). These topologies are based on two different architectural connection methods. The first two are the hybrid connection of the ring-of-mesh, with partial-diagonal-link (HMRPD) in 2-D and 3-D, and the other two are the hybrid connection of the ring-of-torus, with partial-diagonal-link (HTRPD) in 2-D and 3-D. Initially, the parametric analysis performed for both 2-D topologies and result shows that the interconnect has less diameter and average distance, which leads to reduce latency. It requires a small node degree, which makes it more accessible to design a network. It has a high bisection bandwidth, which helps in achieving low communication cost and high throughput. The scalability is higher than that of another existing interconnect. Further, we have examined the throughput, packet latency, and energy consumption of the interconnect for performance comparison of topologies under synthetic traffic patterns. We found that the proposed technique improves performance, optimizes communication cost, and energy consumption. Next, the 2-D HMRPD and 2-D HTRPD extended to 3-D symmetric network architectures by appending two additional ports in 2-D router architectures, namely up port and down port, and connecting these ports by Through Silicon Via (TSV), and routing of packets performed by a quasi-minimal routing technique. The result shows that these 3-D HMRPD and HTRPD have better performance than the 2-D HMRPD, 2-D HTRPD, and existing topologies. Unfortunately, these 3-D topologies result in extra energy consumption issues. Therefore, to solve this issue, heterogeneous layout of 2-D and 3-D router integration techniques applied in 3-D topologies for reducing number of TSV. Furthermore, we have presented two 3-D HTRPD topologies with TSV optimized and compared them with a full TSV-connected 3-D HTRPD. We found that 1P-3DR-HTRPD topology has the lowest gate count, area, dynamic, and static power consumption in comparison to fully connected 3-D HTRPD topology. This work has been designed by modifying network system simulator and also implemented in the Xc7z020clg484-1 ZYNQ FPGA device for validation. Furthermore, we have also examined that these 2-D topologies are more area-efficient and require a maximum crossbar size of 6x6 and have a high frequency of 2.29 GHz and 2.22 GHz for 2-D HMRPD and 2-D HTRPD, respectively, in comparison to other diagonal link topologies.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102597"},"PeriodicalIF":2.5,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Security-oriented printed-circuit-board routing with deep reinforcement learning 基于深度强化学习的面向安全的印刷电路板路由

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-20 DOI: 10.1016/j.vlsi.2025.102602

Katherine Shu-Min Li , Fang-Chi Wu , Ching-Han Lai , Sying-Jyan Wang

With the rapid advancement of artificial intelligence (AI) technologies and the increasing proliferation of electronic devices, the demand for high-performance and secure printed circuit boards (PCBs) has grown substantially. In particular, the requirements for high-frequency operation, high-speed signal integrity, and enhanced security have become increasingly critical in modern PCB design. This study presents an integrated framework that incorporates test point insertion directly into the PCB routing process, simultaneously addressing testability and security concerns at the design stage. For the routing task, we propose a method that prioritizes nets by assigning routing sequences prior to trace generation. The A∗ search algorithm is then employed to perform multilayer routing, utilizing a customized heuristic function to minimize overall trace length while considering the known number of board layers. To determine optimal test point placement, we adopt a reinforcement learning approach, wherein an agent learns to select appropriate insertion actions guided by a carefully designed reward function. Experimental results demonstrate that the proposed approach achieves 100 % routing success and full test point coverage across all evaluated PCB designs. The resulting design allows for improved accessibility for electrical testing and lays the groundwork for subsequent security assessment.

随着人工智能（AI）技术的快速发展和电子设备的日益普及，对高性能和安全的印刷电路板（pcb）的需求大幅增长。特别是对高频工作、高速信号完整性和增强安全性的要求在现代PCB设计中变得越来越重要。本研究提出了一个集成框架，将测试点插入直接集成到PCB布线过程中，同时解决了设计阶段的可测试性和安全性问题。对于路由任务，我们提出了一种方法，通过在跟踪生成之前分配路由序列来确定网络的优先级。然后使用A *搜索算法来执行多层路由，利用自定义的启发式函数来最小化总走线长度，同时考虑到已知的板层数。为了确定最佳的测试点放置，我们采用了强化学习方法，其中智能体在精心设计的奖励函数的指导下学习选择适当的插入动作。实验结果表明，该方法在所有评估的PCB设计中实现了100%的路由成功率和完全的测试点覆盖。最终的设计允许改进电气测试的可访问性，并为后续的安全评估奠定基础。

{"title":"Security-oriented printed-circuit-board routing with deep reinforcement learning","authors":"Katherine Shu-Min Li , Fang-Chi Wu , Ching-Han Lai , Sying-Jyan Wang","doi":"10.1016/j.vlsi.2025.102602","DOIUrl":"10.1016/j.vlsi.2025.102602","url":null,"abstract":"<div><div>With the rapid advancement of artificial intelligence (AI) technologies and the increasing proliferation of electronic devices, the demand for high-performance and secure printed circuit boards (PCBs) has grown substantially. In particular, the requirements for high-frequency operation, high-speed signal integrity, and enhanced security have become increasingly critical in modern PCB design. This study presents an integrated framework that incorporates test point insertion directly into the PCB routing process, simultaneously addressing testability and security concerns at the design stage. For the routing task, we propose a method that prioritizes nets by assigning routing sequences prior to trace generation. The A∗ search algorithm is then employed to perform multilayer routing, utilizing a customized heuristic function to minimize overall trace length while considering the known number of board layers. To determine optimal test point placement, we adopt a reinforcement learning approach, wherein an agent learns to select appropriate insertion actions guided by a carefully designed reward function. Experimental results demonstrate that the proposed approach achieves 100 % routing success and full test point coverage across all evaluated PCB designs. The resulting design allows for improved accessibility for electrical testing and lays the groundwork for subsequent security assessment.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102602"},"PeriodicalIF":2.5,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An area-efficient 1st order noise shaping SAR using C-2C ladder DAC for biomedical applications 使用C-2C梯形DAC的生物医学应用的面积高效一阶噪声整形SAR

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-19 DOI: 10.1016/j.vlsi.2025.102598

Mauricio Velázquez Díaz , Victor R. Gonzalez-Diaz , Gisela De La Fuente-Cortes , Guillermo Espinosa Flores-Verdad , Roberto S. Murphy-Arteaga

This article presents the design and implementation of a fully differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) in 65 nm UMC technology, specifically targeting biomedical applications where area efficiency is a critical requirement. The design prioritizes achieving clean and precise first-order Noise Shaping (NS) by integrating a switched-capacitor-based integrator with our proposed C-2C ladder DAC topology, which is instrumental in significantly reducing area consumption. Noise performance is optimized by carefully correlating the capacitances of the integrator and DAC, ensuring precision and stability. To achieve robust operation, the design incorporates a process, voltage, and temperature (PVT)-resilient methodology for all system blocks, providing consistent performance and reliability under challenging conditions and variations in fabrication. The implemented prototype achieves an area efficiency of 0.058

{mm}^{2}

, 10.37 ENOB over a 20 kHz Bandwidth, and operates at a 1 MHz sampling rate with a power consumption of

448 μ W

.

本文介绍了65纳米UMC技术中全差分逐次逼近寄存器（SAR）模数转换器（ADC）的设计和实现，特别是针对区域效率是关键要求的生物医学应用。该设计通过将基于开关电容的积分器与我们提出的C-2C梯形DAC拓扑集成在一起，优先实现清洁和精确的一阶噪声整形（NS），这有助于显着降低面积消耗。通过仔细关联积分器和DAC的电容，优化了噪声性能，确保了精度和稳定性。为了实现稳健的运行，该设计为所有系统模块集成了工艺、电压和温度（PVT）弹性方法，在具有挑战性的条件和制造变化下提供一致的性能和可靠性。所实现的样机在20khz带宽下的面积效率为0.058 mm2， ENOB为10.37，采样率为1 MHz，功耗为448μW。

{"title":"An area-efficient 1st order noise shaping SAR using C-2C ladder DAC for biomedical applications","authors":"Mauricio Velázquez Díaz , Victor R. Gonzalez-Diaz , Gisela De La Fuente-Cortes , Guillermo Espinosa Flores-Verdad , Roberto S. Murphy-Arteaga","doi":"10.1016/j.vlsi.2025.102598","DOIUrl":"10.1016/j.vlsi.2025.102598","url":null,"abstract":"<div><div>This article presents the design and implementation of a fully differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) in 65 nm UMC technology, specifically targeting biomedical applications where area efficiency is a critical requirement. The design prioritizes achieving clean and precise first-order Noise Shaping (NS) by integrating a switched-capacitor-based integrator with our proposed C-2C ladder DAC topology, which is instrumental in significantly reducing area consumption. Noise performance is optimized by carefully correlating the capacitances of the integrator and DAC, ensuring precision and stability. To achieve robust operation, the design incorporates a process, voltage, and temperature (PVT)-resilient methodology for all system blocks, providing consistent performance and reliability under challenging conditions and variations in fabrication. The implemented prototype achieves an area efficiency of 0.058 <span><math><msup><mrow><mi>mm</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span>, 10.37 ENOB over a 20 kHz Bandwidth, and operates at a 1 MHz sampling rate with a power consumption of <span><math><mrow><mn>448</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span>.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102598"},"PeriodicalIF":2.5,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A CMOS circuit for ultra high frequency chaos generation utilizing a Clapp oscillator with dual memristors 一种利用克拉普振荡器和双忆阻器产生超高频混沌的CMOS电路

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-15 DOI: 10.1016/j.vlsi.2025.102601

Zhikui Duan , Dayi Yang , Shaobo He , Xinmei Yu , Zhuorui Tang , Qingyu Wu

This paper introduces a chaotic circuit design that integrates a Clapp oscillator with dual ultra-high-frequency (UHF) memristors. The circuit architecture marries the conventional Clapp oscillator topology with two UHF memristors, which operate at frequencies extending up to 1.5 GHz, and induces chaotic behavior by leveraging the inherent nonlinear properties of the memristors. The memristive circuit has been realized using the SMIC 0.18

μ

m CMOS technology. Simulation outcomes indicate that, powered by a 3.3 V supply, the chaotic circuit is capable of producing both single-vortex and double-vortex-like chaotic attractors by adjusting the capacitance and inductance parameters. Additionally, the chaotic attributes of the circuit have been substantiated through phase portraits, Lyapunov exponent analysis, 0-1 test, Bifurcation diagram, and Poincaré section analysis. The circuit exhibits characteristics of ultra-high-frequency operation, a wealth of chaotic dynamics, and a stable signal output. This study provides a new solution for the generation of high frequency chaotic sequences, which has potential application prospects in the field of information security.

本文介绍了一种将克拉普振荡器与双超高频忆阻器集成在一起的混沌电路设计。该电路结构将传统的克拉普振荡器拓扑结构与两个超高频忆阻器结合在一起，其工作频率可达1.5 GHz，并利用忆阻器固有的非线性特性诱导混沌行为。该忆阻电路采用中芯0.18 μm CMOS技术实现。仿真结果表明，在3.3 V电源下，通过调整电容和电感参数，混沌电路能够产生单涡和双涡混沌吸引子。此外，通过相位图、Lyapunov指数分析、0-1检验、分岔图和poincarcarcarr截面分析证实了电路的混沌属性。该电路具有超高频工作、丰富的混沌动力学和稳定的信号输出等特点。该研究为高频混沌序列的生成提供了一种新的解决方案，在信息安全领域具有潜在的应用前景。

{"title":"A CMOS circuit for ultra high frequency chaos generation utilizing a Clapp oscillator with dual memristors","authors":"Zhikui Duan , Dayi Yang , Shaobo He , Xinmei Yu , Zhuorui Tang , Qingyu Wu","doi":"10.1016/j.vlsi.2025.102601","DOIUrl":"10.1016/j.vlsi.2025.102601","url":null,"abstract":"<div><div>This paper introduces a chaotic circuit design that integrates a Clapp oscillator with dual ultra-high-frequency (UHF) memristors. The circuit architecture marries the conventional Clapp oscillator topology with two UHF memristors, which operate at frequencies extending up to 1.5 GHz, and induces chaotic behavior by leveraging the inherent nonlinear properties of the memristors. The memristive circuit has been realized using the SMIC 0.18 <span><math><mi>μ</mi></math></span>m CMOS technology. Simulation outcomes indicate that, powered by a 3.3 V supply, the chaotic circuit is capable of producing both single-vortex and double-vortex-like chaotic attractors by adjusting the capacitance and inductance parameters. Additionally, the chaotic attributes of the circuit have been substantiated through phase portraits, Lyapunov exponent analysis, 0-1 test, Bifurcation diagram, and Poincaré section analysis. The circuit exhibits characteristics of ultra-high-frequency operation, a wealth of chaotic dynamics, and a stable signal output. This study provides a new solution for the generation of high frequency chaotic sequences, which has potential application prospects in the field of information security.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102601"},"PeriodicalIF":2.5,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145571743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

VLSI implementation of adaptable threshold and projection aware OMP with reconfigurable LUT-based MAC unit for ECG signal reconstruction 基于可重构lut的MAC单元的自适应阈值和投影感知OMP的VLSI实现用于心电信号重构

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-14 DOI: 10.1016/j.vlsi.2025.102600

T. Delphine Sheeba, G. Athisha

Compressed sensing applications frequently employ sparse signal recovery techniques, including Orthogonal Matching Pursuit (OMP), to effectively reconstruct signals. However, traditional OMP suffers from limitations in atom selection due to its reliance on single-atom selection methods, which can lead to inaccurate reconstructions and increased computational complexity. A novel Adaptable Threshold and Projection-Aware Orthogonal Matching Pursuit (ATPAwOMP) algorithm is suggested in this study to overcome these issues. By combining an adaptive thresholding method with projection-based atom selection, ATPAwOMP improves conventional OMP by iteratively improving reconstruction accuracy. By eliminating unnecessary atoms from the support set during the backtracking phase of the method, redundant computations are decreased, and the importance of the chosen atoms is increased. A lightweight VLSI design with a parallel multiplication and accumulation (MAC) unit, sorting unit, and matrix inversion unit is presented in order to further optimize the method for hardware deployment. A Newton-Raphson-based reciprocal operator decreases resource requirements for matrix inversion. At the same time, a Reconfigurable Adder/Subtractor Module (RASM) and a low-complexity LUT-based multiplier are integrated to minimize hardware overhead in the MAC unit. The proposed work is implemented in the Xilinx platform using the MIT-BIH arrhythmia database. The FPGA measures and the error metrics, such as signal to noise ratio (SNR), root mean square error (RMSE), percentage root mean square difference (PRD), and normalized PRDN, are evaluated. The ATPAwOMP algorithm is well-suited for real-time and resource-constrained applications like wearable ECG monitoring devices because of its adaptive thresholding and projection-aware approach, which provide notable increases in reconstruction accuracy and processing efficiency.

压缩感知应用经常采用稀疏信号恢复技术，包括正交匹配追踪（OMP），以有效地重建信号。然而，由于传统的OMP依赖于单原子选择方法，因此在原子选择方面存在局限性，这可能导致不准确的重建和增加的计算复杂性。为了克服这些问题，本文提出了一种新的自适应阈值和投影感知正交匹配追踪（ATPAwOMP）算法。通过将自适应阈值法与基于投影的原子选择相结合，ATPAwOMP通过迭代提高重建精度来改进传统OMP。通过在方法回溯阶段从支持集中剔除不必要的原子，减少了冗余计算，增加了所选原子的重要性。为了进一步优化硬件部署方法，提出了一种具有并行乘法和累积（MAC）单元、排序单元和矩阵反演单元的轻量级VLSI设计。基于牛顿-拉斐尔的互反算子减少了矩阵反演的资源需求。同时，集成了可重构加/减模块（RASM）和低复杂度的基于lut的乘法器，最大限度地减少了MAC单元的硬件开销。这项工作是在Xilinx平台上使用MIT-BIH心律失常数据库实现的。评估了FPGA测量和误差指标，如信噪比（SNR）、均方根误差（RMSE）、百分比均方根差（PRD）和归一化PRDN。ATPAwOMP算法非常适合实时和资源受限的应用，如可穿戴式心电监护设备，因为它的自适应阈值和投影感知方法，可以显著提高重建精度和处理效率。

{"title":"VLSI implementation of adaptable threshold and projection aware OMP with reconfigurable LUT-based MAC unit for ECG signal reconstruction","authors":"T. Delphine Sheeba, G. Athisha","doi":"10.1016/j.vlsi.2025.102600","DOIUrl":"10.1016/j.vlsi.2025.102600","url":null,"abstract":"<div><div>Compressed sensing applications frequently employ sparse signal recovery techniques, including Orthogonal Matching Pursuit (OMP), to effectively reconstruct signals. However, traditional OMP suffers from limitations in atom selection due to its reliance on single-atom selection methods, which can lead to inaccurate reconstructions and increased computational complexity. A novel Adaptable Threshold and Projection-Aware Orthogonal Matching Pursuit (ATPAwOMP) algorithm is suggested in this study to overcome these issues. By combining an adaptive thresholding method with projection-based atom selection, ATPAwOMP improves conventional OMP by iteratively improving reconstruction accuracy. By eliminating unnecessary atoms from the support set during the backtracking phase of the method, redundant computations are decreased, and the importance of the chosen atoms is increased. A lightweight VLSI design with a parallel multiplication and accumulation (MAC) unit, sorting unit, and matrix inversion unit is presented in order to further optimize the method for hardware deployment. A Newton-Raphson-based reciprocal operator decreases resource requirements for matrix inversion. At the same time, a Reconfigurable Adder/Subtractor Module (RASM) and a low-complexity LUT-based multiplier are integrated to minimize hardware overhead in the MAC unit. The proposed work is implemented in the Xilinx platform using the MIT-BIH arrhythmia database. The FPGA measures and the error metrics, such as signal to noise ratio (SNR), root mean square error (RMSE), percentage root mean square difference (PRD), and normalized PRDN, are evaluated. The ATPAwOMP algorithm is well-suited for real-time and resource-constrained applications like wearable ECG monitoring devices because of its adaptive thresholding and projection-aware approach, which provide notable increases in reconstruction accuracy and processing efficiency.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102600"},"PeriodicalIF":2.5,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A hybrid 16-bit Ripple Carry Adder with Doublet Transmission Gate-based Compressor for performance boost 混合16位纹波进位加法器与基于双态传输门的压缩器，用于性能提升

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-13 DOI: 10.1016/j.vlsi.2025.102594

Parthiv Bhau , Vijay Savani

This work introduces five novel 1-bit Transmission Gate Diffusion Input (TGDI)-based Hybrid Full Adders (HFAs), optimized for low power consumption and high-speed performance, outperforming recent architectures. Additionally, an innovative 16-bit Ripple Carry Adder (RCA) is developed, leveraging a Doublet Transmission Gate Adder-based Compressor Structure (DTGAC) to address driving strength challenges while achieving a low power-delay product and improved Figure of Merit (FoM). The proposed architectures are simulated using the Cadence Virtuoso tool with 18 nm Fin Field Effect Transistor (FinFET) technology and a nominal supply voltage of 0.8 V (±10%) at 27 °C. Post-layout simulations validate the real-world electrical behavior of the proposed circuits. Process corner and Monte Carlo analysis confirm the robustness of the designs. The results reveal a significant FoM improvement of 45.16%–59.3% for the proposed 1-bit TGDI-based HFAs compared to the 1-bit conventional mirror adder. Furthermore, the 16-bit RCA with DTGAC structures utilizing the proposed adders achieves a FoM enhancement of 19.94%–28.88% as compared to the DTGAC-based 16-bit RCA with a mirror adder. These advancements establish the proposed architectures as highly efficient and robust solutions for low-power, high-performance digital arithmetic circuits.

本研究介绍了五种新型的基于1位传输门扩散输入（TGDI）的混合全加法器（hfa），优化了低功耗和高速性能，优于最近的架构。此外，还开发了一种创新的16位纹波进位加法器（RCA），利用基于双态传输门加法器的压缩器结构（DTGAC）来解决驱动强度挑战，同时实现低功耗延迟产品和改进的性能图（FoM）。采用Cadence Virtuoso工具，采用18nm翅片场效应晶体管（FinFET）技术，在27°C下的标称电源电压为0.8 V（±10%）进行模拟。布局后仿真验证了所提出电路的真实电行为。过程角分析和蒙特卡罗分析证实了设计的鲁棒性。结果表明，与传统的1位镜像加法器相比，基于1位tgdi的HFAs的FoM显著提高了45.16%-59.3%。此外，与使用镜像加法器的基于DTGAC的16位RCA相比，使用所提加法器的具有DTGAC结构的16位RCA实现了19.94%-28.88%的FoM增强。这些进步使所提出的架构成为低功耗、高性能数字算术电路的高效、稳健的解决方案。

{"title":"A hybrid 16-bit Ripple Carry Adder with Doublet Transmission Gate-based Compressor for performance boost","authors":"Parthiv Bhau , Vijay Savani","doi":"10.1016/j.vlsi.2025.102594","DOIUrl":"10.1016/j.vlsi.2025.102594","url":null,"abstract":"<div><div>This work introduces five novel 1-bit Transmission Gate Diffusion Input (TGDI)-based Hybrid Full Adders (HFAs), optimized for low power consumption and high-speed performance, outperforming recent architectures. Additionally, an innovative 16-bit Ripple Carry Adder (RCA) is developed, leveraging a Doublet Transmission Gate Adder-based Compressor Structure (DTGAC) to address driving strength challenges while achieving a low power-delay product and improved Figure of Merit (FoM). The proposed architectures are simulated using the Cadence Virtuoso tool with 18 nm Fin Field Effect Transistor (FinFET) technology and a nominal supply voltage of 0.8 V (±10%) at 27 °C. Post-layout simulations validate the real-world electrical behavior of the proposed circuits. Process corner and Monte Carlo analysis confirm the robustness of the designs. The results reveal a significant FoM improvement of 45.16%–59.3% for the proposed 1-bit TGDI-based HFAs compared to the 1-bit conventional mirror adder. Furthermore, the 16-bit RCA with DTGAC structures utilizing the proposed adders achieves a FoM enhancement of 19.94%–28.88% as compared to the DTGAC-based 16-bit RCA with a mirror adder. These advancements establish the proposed architectures as highly efficient and robust solutions for low-power, high-performance digital arithmetic circuits.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102594"},"PeriodicalIF":2.5,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145536940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Inductorless dynamic logic based on 2ϕ-Josephson junctions 基于2ϕ-Josephson结的无电感器动态逻辑

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-12 DOI: 10.1016/j.vlsi.2025.102599

Ana Mitrovic, Eby G. Friedman

Despite offering significant performance and energy efficiency advantages over CMOS, superconductive digital circuits face several challenges including scaling limitations. Traditional single flux quantum (SFQ) circuits require synchronous clock signals, leading to complex clock distribution networks. The integration density of SFQ circuits is also hindered by the need for large storage inductors. To overcome these challenges, an inductorless dynamic logic based on ferromagnetic bistable 2

ϕ

-Josephson junctions (JJ) is proposed. This logic family offers a scalable solution for asynchronous superconductive logic circuits. The behavior of 2

ϕ

-Josephson junctions is reviewed, and all-JJ dynamic circuits facilitating clockless operation are introduced. Inductorless dynamic AND and OR gates are evaluated in a half adder. The characteristics, margins, and effects of the parasitic inductances on circuit operation are discussed. As compared to RSFQ gates in the same technology (1

kA / {cm}^{2}

), these logic gates exhibit 59% less delay (9 ps). 2

ϕ

-JJs require less energy to switch between equilibrium states. As a result, a decrease of 65% in bias current as compared to standard dynamic SFQ circuits is achieved. The reduction in bias current in half flux quantum operation requires 6.7X less energy per transition. Utilizing standard Josephson junctions rather than inductors saves

42 μ m^{2}

and

53 μ m^{2}

of loop inductance area within, respectively, a dynamic AND gate and dynamic OR gate for the 10

kA / {cm}^{2}

MIT LL SFQ5ee technology.

尽管与CMOS相比，超导数字电路具有显著的性能和能效优势，但仍面临一些挑战，包括缩放限制。传统的单通量量子（SFQ）电路需要同步时钟信号，导致时钟分配网络复杂。SFQ电路的集成密度也因为需要大的存储电感器而受到阻碍。为了克服这些挑战，提出了一种基于铁磁双稳态2ϕ-Josephson结（JJ）的无电感器动态逻辑。该逻辑系列为异步超导逻辑电路提供了可扩展的解决方案。回顾了2ϕ-Josephson结的行为，并介绍了促进无时钟操作的全jj动态电路。在半加法器中评估无电感器的动态与或门。讨论了寄生电感的特性、余量以及对电路工作的影响。与相同技术的RSFQ门（1 kA/cm2）相比，这些逻辑门的延迟减少了59% （9 ps）。在平衡状态之间切换所需的能量更少。因此，与标准动态SFQ电路相比，偏置电流降低了65%。在半通量量子运算中，减少偏置电流所需的每次跃迁能量减少6.7倍。采用标准约瑟夫森结而不是电感，在10 kA/cm2的MIT LL SFQ5ee技术中，动态与门和动态或门分别节省了42μm2和53μm2的环路电感面积。

{"title":"Inductorless dynamic logic based on 2ϕ-Josephson junctions","authors":"Ana Mitrovic, Eby G. Friedman","doi":"10.1016/j.vlsi.2025.102599","DOIUrl":"10.1016/j.vlsi.2025.102599","url":null,"abstract":"<div><div>Despite offering significant performance and energy efficiency advantages over CMOS, superconductive digital circuits face several challenges including scaling limitations. Traditional single flux quantum (SFQ) circuits require synchronous clock signals, leading to complex clock distribution networks. The integration density of SFQ circuits is also hindered by the need for large storage inductors. To overcome these challenges, an inductorless dynamic logic based on ferromagnetic bistable 2<span><math><mi>ϕ</mi></math></span>-Josephson junctions (JJ) is proposed. This logic family offers a scalable solution for asynchronous superconductive logic circuits. The behavior of 2<span><math><mi>ϕ</mi></math></span>-Josephson junctions is reviewed, and all-JJ dynamic circuits facilitating clockless operation are introduced. Inductorless dynamic AND and OR gates are evaluated in a half adder. The characteristics, margins, and effects of the parasitic inductances on circuit operation are discussed. As compared to RSFQ gates in the same technology (1 <span><math><mrow><mi>kA</mi><mo>/</mo><msup><mrow><mi>cm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>), these logic gates exhibit 59% less delay (9 ps). 2<span><math><mi>ϕ</mi></math></span>-JJs require less energy to switch between equilibrium states. As a result, a decrease of 65% in bias current as compared to standard dynamic SFQ circuits is achieved. The reduction in bias current in half flux quantum operation requires 6.7X less energy per transition. Utilizing standard Josephson junctions rather than inductors saves <span><math><mrow><mn>42</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and <span><math><mrow><mn>53</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> of loop inductance area within, respectively, a dynamic AND gate and dynamic OR gate for the 10 <span><math><mrow><mi>kA</mi><mo>/</mo><msup><mrow><mi>cm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> MIT LL SFQ5ee technology.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102599"},"PeriodicalIF":2.5,"publicationDate":"2025-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145519608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FTPUF:Feedback structure of TERO PUF for high reliability FTPUF: TERO PUF的反馈结构，可靠性高

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-08 DOI: 10.1016/j.vlsi.2025.102596

Yingchun Lu , Xinkai Wu , Jinlin Chen , Huaguo Liang , Zhengfeng Huang , Xiumin Xu , Bo Liu

Physical Unclonable Function (PUF), a new hardware security primitive, provides a unique trustworthy root for a system by extracting deviations from a circuit's process. However, existing PUFs are difficult to achieve high reliability under temperature and voltage variations. In this paper, To address the problem of low reliability of Transient Effect Ring Oscillator (TERO) PUF, we propose a feedback TERO PUF based on Mueller gate, which uses the accumulation of RO loop delays to isolate the final PUF response, and stabilises the PUF quickly by introducing the delay of the feedback loop as a threshold. Experimental results on HSPICE show that the FT PUF reduces the BER to the worst 10.28 % over the temperature range of -20-80 °C and the voltage range of 0.8–1.2 V, and the uniqueness and uniformity are 51.38 % and 49.87 %, respectively. When implemented on several 7-series Xilinx devices, it achieved an 8.07 % reduction in unstable bit rate over conventional TERO PUFs under standard conditions (25 °C, 1.0V) and a worst-case unstable bit rate improvement of 3.15 % over the manufacturer's recommended voltage range.

物理不可克隆函数（Physical unclable Function， PUF）是一种新的硬件安全原语，它通过从电路过程中提取偏差，为系统提供一个唯一的可信赖的根。然而，现有的puf在温度和电压变化下难以实现高可靠性。为了解决瞬态效应环振荡器（TERO） PUF可靠性低的问题，本文提出了一种基于穆勒门的反馈TERO PUF，利用RO环路延迟的积累来隔离PUF的最终响应，并通过引入反馈环路的延迟作为阈值来快速稳定PUF。HSPICE上的实验结果表明，在-20 ~ 80℃的温度范围和0.8 ~ 1.2 V的电压范围内，FT PUF将误码率降低了10.28%，唯一性和均匀性分别为51.38%和49.87%。当在几个7系列Xilinx设备上实施时，在标准条件下（25°C, 1.0V），它比传统TERO puf的不稳定比特率降低了8.07%，在制造商推荐的电压范围内，最坏情况下不稳定比特率提高了3.15%。

{"title":"FTPUF:Feedback structure of TERO PUF for high reliability","authors":"Yingchun Lu , Xinkai Wu , Jinlin Chen , Huaguo Liang , Zhengfeng Huang , Xiumin Xu , Bo Liu","doi":"10.1016/j.vlsi.2025.102596","DOIUrl":"10.1016/j.vlsi.2025.102596","url":null,"abstract":"<div><div>Physical Unclonable Function (PUF), a new hardware security primitive, provides a unique trustworthy root for a system by extracting deviations from a circuit's process. However, existing PUFs are difficult to achieve high reliability under temperature and voltage variations. In this paper, To address the problem of low reliability of Transient Effect Ring Oscillator (TERO) PUF, we propose a feedback TERO PUF based on Mueller gate, which uses the accumulation of RO loop delays to isolate the final PUF response, and stabilises the PUF quickly by introducing the delay of the feedback loop as a threshold. Experimental results on HSPICE show that the FT PUF reduces the BER to the worst 10.28 % over the temperature range of -20-80 °C and the voltage range of 0.8–1.2 V, and the uniqueness and uniformity are 51.38 % and 49.87 %, respectively. When implemented on several 7-series Xilinx devices, it achieved an 8.07 % reduction in unstable bit rate over conventional TERO PUFs under standard conditions (25 °C, 1.0V) and a worst-case unstable bit rate improvement of 3.15 % over the manufacturer's recommended voltage range.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102596"},"PeriodicalIF":2.5,"publicationDate":"2025-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145519610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Review: Application and development of machine learning in semiconductor manufacturing for automated wafer map pattern recognition and classification 综述：机器学习在半导体制造中的应用与发展，用于自动化晶圆图模式识别与分类

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-11-07 DOI: 10.1016/j.vlsi.2025.102595

Wei Zhou, Guo-Xing Wang, Yongfu Li

The rapid development of the integrated circuit (IC) industry has continuously increased the complexity of IC manufacturing processes. Massive data analysis, exemplified by Wafer Map analysis, poses growing challenges for engineers and technicians in the field. With the ongoing advancement and maturation of machine learning in artificial intelligence, the application of machine learning algorithms for automated recognition and classification of wafer map patterns, known as Wafer Map Pattern Recognition and Classification, has emerged as a prominent research focus within the industry over the past decade. This paper conducts a systematic and comprehensive study, analyzing various machine learning algorithms applied to the problem of wafer map pattern recognition and classification. Starting from traditional machine learning techniques to neural networks and deep learning, the study identifies convolutional neural networks (CNNs) as one of the most effective approaches for addressing this problem currently. The research also highlights the continuous optimization of deep learning algorithms, focusing on improvements in architecture, depth, feature fusion, and the introduction of attention mechanisms to enhance the extraction of fine local features. Furthermore, the paper addresses issues related to data dependency, emphasizing innovations such as data augmentation, data generation, and semi-supervised learning models to mitigate the adverse effects of data scarcity and imbalance on deep learning training. These advancements aim to facilitate superior results for deep learning algorithms in solving the problem of wafer map pattern recognition and classification, thereby contributing to the field's ongoing progress.

集成电路产业的快速发展使集成电路制造工艺的复杂性不断增加。以Wafer Map分析为例的海量数据分析给该领域的工程师和技术人员带来了越来越大的挑战。随着人工智能中机器学习的不断发展和成熟，机器学习算法在晶圆图模式自动识别和分类中的应用，被称为晶圆图模式识别和分类，在过去十年中已经成为业界的一个突出的研究热点。本文进行了系统全面的研究，分析了应用于晶圆图模式识别与分类问题的各种机器学习算法。从传统的机器学习技术到神经网络和深度学习，本研究确定卷积神经网络（cnn）是目前解决这一问题最有效的方法之一。研究还强调了深度学习算法的不断优化，重点在架构、深度、特征融合等方面进行改进，并引入注意机制来增强对精细局部特征的提取。此外，本文还讨论了与数据依赖相关的问题，强调了数据增强、数据生成和半监督学习模型等创新，以减轻数据稀缺和不平衡对深度学习训练的不利影响。这些进步旨在促进深度学习算法在解决晶圆图模式识别和分类问题方面的卓越结果，从而促进该领域的持续发展。

{"title":"Review: Application and development of machine learning in semiconductor manufacturing for automated wafer map pattern recognition and classification","authors":"Wei Zhou, Guo-Xing Wang, Yongfu Li","doi":"10.1016/j.vlsi.2025.102595","DOIUrl":"10.1016/j.vlsi.2025.102595","url":null,"abstract":"<div><div>The rapid development of the integrated circuit (IC) industry has continuously increased the complexity of IC manufacturing processes. Massive data analysis, exemplified by Wafer Map analysis, poses growing challenges for engineers and technicians in the field. With the ongoing advancement and maturation of machine learning in artificial intelligence, the application of machine learning algorithms for automated recognition and classification of wafer map patterns, known as Wafer Map Pattern Recognition and Classification, has emerged as a prominent research focus within the industry over the past decade. This paper conducts a systematic and comprehensive study, analyzing various machine learning algorithms applied to the problem of wafer map pattern recognition and classification. Starting from traditional machine learning techniques to neural networks and deep learning, the study identifies convolutional neural networks (CNNs) as one of the most effective approaches for addressing this problem currently. The research also highlights the continuous optimization of deep learning algorithms, focusing on improvements in architecture, depth, feature fusion, and the introduction of attention mechanisms to enhance the extraction of fine local features. Furthermore, the paper addresses issues related to data dependency, emphasizing innovations such as data augmentation, data generation, and semi-supervised learning models to mitigate the adverse effects of data scarcity and imbalance on deep learning training. These advancements aim to facilitate superior results for deep learning algorithms in solving the problem of wafer map pattern recognition and classification, thereby contributing to the field's ongoing progress.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"107 ","pages":"Article 102595"},"PeriodicalIF":2.5,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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