Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10220987
Amandus Bach, Jan Mathé, Benedict J. Mortimer, Tim Karsten, R. D. Doncker
Input-series output-parallel (ISOP) dc-dc converter systems require a dedicated input-voltage-sharing (IVS) control strategy. A centralized IVS control typically reduces system modularity and reliability. Thus, this paper adopts a decentralized IVS control method to the ISOP-connected three-phase dual-active bridge (DAB3) converter. It contributes to exploring decentralized control methods for ISOP systems by linking the theory of the negative incremental-resistance behavior to the instability of the IVS-transfer function. For the stability assessment, closed-loop input impedance models of the DAB3 converter are derived that include the effects of the control and the output-parallel connection into a single-input single-output (SISO) model. The derived analytical models are verified via multitone analyses of a switching model in offline simulations. This way, the stability of the whole ISOP system can be predicted solely based on the SISO model. The model-based stability regions are validated on a real-time simulation system of a two-module system at a switching frequency of 10 kHz. Experimental results are presented for an eight-module system with an input voltage of 5 kV.
{"title":"Impedance-Based Modeling and Stability Analysis of the Input-Series Output-Parallel DAB3 Converter with Decentralized Control","authors":"Amandus Bach, Jan Mathé, Benedict J. Mortimer, Tim Karsten, R. D. Doncker","doi":"10.1109/COMPEL52896.2023.10220987","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10220987","url":null,"abstract":"Input-series output-parallel (ISOP) dc-dc converter systems require a dedicated input-voltage-sharing (IVS) control strategy. A centralized IVS control typically reduces system modularity and reliability. Thus, this paper adopts a decentralized IVS control method to the ISOP-connected three-phase dual-active bridge (DAB3) converter. It contributes to exploring decentralized control methods for ISOP systems by linking the theory of the negative incremental-resistance behavior to the instability of the IVS-transfer function. For the stability assessment, closed-loop input impedance models of the DAB3 converter are derived that include the effects of the control and the output-parallel connection into a single-input single-output (SISO) model. The derived analytical models are verified via multitone analyses of a switching model in offline simulations. This way, the stability of the whole ISOP system can be predicted solely based on the SISO model. The model-based stability regions are validated on a real-time simulation system of a two-module system at a switching frequency of 10 kHz. Experimental results are presented for an eight-module system with an input voltage of 5 kV.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"251 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73104043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221007
Vikas Kumar Rathore, M. Evzelman, M. Peretz
An efficient first stage interleaving technique for Boost Extender topology is presented. A unique single conversion operation of the boost extender topology, and current stress distribution between the modules pose a challenge on creating a successful and efficient interleaving scheme with this converter. A mechanism is developed, where a supporting first stage in a multilevel high voltage gain structure is added. The supporting stage shares the high current stress of the first boosting stage, compatible with interleaving technique, which reduces the ripples of each inductor along with the input and first stage output capacitor ripples. In addition, the voltage multiplication modules are shared between the interleaved stages providing significant component reduction comparing to traditional interleaving schemes. The concept was validated on a 260W experimental laboratory prototype. Theoretical predictions well agree with simulation and experimental results.
{"title":"Interleaving Boost Extender Topology","authors":"Vikas Kumar Rathore, M. Evzelman, M. Peretz","doi":"10.1109/COMPEL52896.2023.10221007","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221007","url":null,"abstract":"An efficient first stage interleaving technique for Boost Extender topology is presented. A unique single conversion operation of the boost extender topology, and current stress distribution between the modules pose a challenge on creating a successful and efficient interleaving scheme with this converter. A mechanism is developed, where a supporting first stage in a multilevel high voltage gain structure is added. The supporting stage shares the high current stress of the first boosting stage, compatible with interleaving technique, which reduces the ripples of each inductor along with the input and first stage output capacitor ripples. In addition, the voltage multiplication modules are shared between the interleaved stages providing significant component reduction comparing to traditional interleaving schemes. The concept was validated on a 260W experimental laboratory prototype. Theoretical predictions well agree with simulation and experimental results.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"26 1","pages":"1-6"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78711114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221018
Bar Halivni, Daniel Beniaminson, Lee Maman, Adi Yankovich, M. Evzelman, M. Peretz
This paper introduces a scalable power hardware-in-the-loop (PHiL) battery emulation system. The battery emulator enables the simulation of real battery voltage profiles with full power rating sink and sourcing capabilities using off-the-shelf components. The battery emulator tracks battery voltage, temperature, and current to provide real-time monitoring of the emulated battery’s state of charge (SOC) and remaining useful life (RUL). The emulator operates in a continuous battery emulation mode or a cyclic mode for repetitive battery testing. The new battery emulator can replace end-product batteries during system development and is realized in two parts, PC Graphical User Interface (GUI) and battery emulator (Hardware). A battery profile-generating algorithm is introduced to accurately reflect the behavior of an actual battery during emulation. All measured data and battery voltage profiles are transferred via Wi-Fi to enable maximal freedom in system deployment. An experimental prototype has been built and tested to verify the battery emulation operation. The prototype handles a maximum input voltage of 150V and an input current of 60A.
{"title":"Scalable High-Power Battery Emulator for Power Hardware-in-the-Loop Applications","authors":"Bar Halivni, Daniel Beniaminson, Lee Maman, Adi Yankovich, M. Evzelman, M. Peretz","doi":"10.1109/COMPEL52896.2023.10221018","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221018","url":null,"abstract":"This paper introduces a scalable power hardware-in-the-loop (PHiL) battery emulation system. The battery emulator enables the simulation of real battery voltage profiles with full power rating sink and sourcing capabilities using off-the-shelf components. The battery emulator tracks battery voltage, temperature, and current to provide real-time monitoring of the emulated battery’s state of charge (SOC) and remaining useful life (RUL). The emulator operates in a continuous battery emulation mode or a cyclic mode for repetitive battery testing. The new battery emulator can replace end-product batteries during system development and is realized in two parts, PC Graphical User Interface (GUI) and battery emulator (Hardware). A battery profile-generating algorithm is introduced to accurately reflect the behavior of an actual battery during emulation. All measured data and battery voltage profiles are transferred via Wi-Fi to enable maximal freedom in system deployment. An experimental prototype has been built and tested to verify the battery emulation operation. The prototype handles a maximum input voltage of 150V and an input current of 60A.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"2 1","pages":"1-6"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78769657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221179
A. A. Khan, N. Zaffar, M. Ikram
This work investigates the comparative assessment of DC-link current ripples in perspective of reduced common mode voltage (RCMV) PWM schemes. The anticipated simultaneous reduction of ripple current on DC-link capacitor and common mode voltage compared to traditional PWM approach is seen to exist in certain regions of operation. This may result in reduced thermal stress and consequently in enhanced reliability and operational lifetime. Another increasingly important consideration is for DC microgrids where the inverters are connected directly to the dc-bus and ripple reduction and RCMV for one or more of these inverters is critical for reliable operation. This work utilizes the piece-wise sinusoidal form of DC-link current computing a closed form RMS current expression that is further analyzed for varying load and mod-indices. The RMS DC-link current of conventional space vector PWM has also been analyzed as base case. It would be seen that these modified PWMs mostly put higher ripple stresses on capacitor. However, there are specific regions where one PWM scheme can be employed for reducing DC-link stress.
{"title":"Comparative Evaluation of DC-link Capacitor RMS Current Stress for Conventional and Reduced Common Mode Voltage SVPWM based Inverters","authors":"A. A. Khan, N. Zaffar, M. Ikram","doi":"10.1109/COMPEL52896.2023.10221179","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221179","url":null,"abstract":"This work investigates the comparative assessment of DC-link current ripples in perspective of reduced common mode voltage (RCMV) PWM schemes. The anticipated simultaneous reduction of ripple current on DC-link capacitor and common mode voltage compared to traditional PWM approach is seen to exist in certain regions of operation. This may result in reduced thermal stress and consequently in enhanced reliability and operational lifetime. Another increasingly important consideration is for DC microgrids where the inverters are connected directly to the dc-bus and ripple reduction and RCMV for one or more of these inverters is critical for reliable operation. This work utilizes the piece-wise sinusoidal form of DC-link current computing a closed form RMS current expression that is further analyzed for varying load and mod-indices. The RMS DC-link current of conventional space vector PWM has also been analyzed as base case. It would be seen that these modified PWMs mostly put higher ripple stresses on capacitor. However, there are specific regions where one PWM scheme can be employed for reducing DC-link stress.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"71 1","pages":"1-7"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88150341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221027
Markus Mogensen Henriksen, Jens Otten, Adrian Gehl, B. Wicht
This paper presents an inspection method for analyzing the soft-charging capabilities of switched-capacitor converters (SCC). The method utilizes a multi-step visual approach to derive the voltage changes (ΔV) across each flying capacitor, leading to an intuitive way of understanding the behavior of hybrid-SCC topologies on circuit level. The method is presented by examples and is used to obtain capacitance ratios and split-phase timings for Hybrid Dickson topologies.
{"title":"The ΔV-Method: An Intuitive Method for Analyzing Soft-Charging Capabilities of Hybrid Switched-Capacitor DC-DC Converters","authors":"Markus Mogensen Henriksen, Jens Otten, Adrian Gehl, B. Wicht","doi":"10.1109/COMPEL52896.2023.10221027","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221027","url":null,"abstract":"This paper presents an inspection method for analyzing the soft-charging capabilities of switched-capacitor converters (SCC). The method utilizes a multi-step visual approach to derive the voltage changes (ΔV) across each flying capacitor, leading to an intuitive way of understanding the behavior of hybrid-SCC topologies on circuit level. The method is presented by examples and is used to obtain capacitance ratios and split-phase timings for Hybrid Dickson topologies.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"10 1","pages":"1-6"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80931747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221146
Firehiwot Gurara, K. Afridi
This paper introduces control and design methodology for high-efficiency synchronous resistance compression network (RCN) based resonant dc-dc converter utilizing matching network in its transformation stage. RCN converters typically comprise inverter, transformer, and differential reactances connected to two phase-shifted rectifiers at the output. Conventionally, these converters rely on a transformer to provide large gain across a wide load range. A generalized approach to develop phase-shift control methodology for a synchronous RCN converter that incorporates matching network to reduce the step-up requirement of its transformer is proposed. A systematic methodology is also presented to design and co-optimize the transformer and matching network efficiency across a wide load range. An example design which applies the proposed design methodology in a 300 W, 12-V input, 200-400-V output synchronous RCN dc-dc converter is also discussed.
{"title":"High-Performance Synchronous Resistance Compression Network-based Resonant DC-DC Converter Utilizing Matching Network","authors":"Firehiwot Gurara, K. Afridi","doi":"10.1109/COMPEL52896.2023.10221146","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221146","url":null,"abstract":"This paper introduces control and design methodology for high-efficiency synchronous resistance compression network (RCN) based resonant dc-dc converter utilizing matching network in its transformation stage. RCN converters typically comprise inverter, transformer, and differential reactances connected to two phase-shifted rectifiers at the output. Conventionally, these converters rely on a transformer to provide large gain across a wide load range. A generalized approach to develop phase-shift control methodology for a synchronous RCN converter that incorporates matching network to reduce the step-up requirement of its transformer is proposed. A systematic methodology is also presented to design and co-optimize the transformer and matching network efficiency across a wide load range. An example design which applies the proposed design methodology in a 300 W, 12-V input, 200-400-V output synchronous RCN dc-dc converter is also discussed.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"24 1","pages":"1-7"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79479684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221028
Pengxiang Huang, Shahil Shah, L. Vanfretti
DC faults of MMC can result in a significantly large fault current due to the discharge of submodule capacitors. The fault current not only risks damaging the MMC but also demands a considerable breaking capacity from the dc circuit breaker (DCCBs). This paper introduces two novel active fault current limiting methods (AFCLs), namely virtual impedance-based and energy control-based AFCL. The first method utilizes circulating current feedforward, which introduces a virtual arm impedance to suppress the rate of rise of the fault current. Meanwhile, the second method relies on the control of the internally stored energy of the MMC to automatically minimize the number of submodules that discharge during a dc-side fault. Therefore, both the dc-side current and the MMC arm current can be effectively suppressed after the occurrence of the fault. The proposed methods do not require fault detection and their response is proportional to the rate of rise in the fault current. Simulation case studies are presented to demonstrate the proposed methods.
{"title":"Active Fault Current Limiting Control for Half-bridge MMC in HVDC Systems","authors":"Pengxiang Huang, Shahil Shah, L. Vanfretti","doi":"10.1109/COMPEL52896.2023.10221028","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221028","url":null,"abstract":"DC faults of MMC can result in a significantly large fault current due to the discharge of submodule capacitors. The fault current not only risks damaging the MMC but also demands a considerable breaking capacity from the dc circuit breaker (DCCBs). This paper introduces two novel active fault current limiting methods (AFCLs), namely virtual impedance-based and energy control-based AFCL. The first method utilizes circulating current feedforward, which introduces a virtual arm impedance to suppress the rate of rise of the fault current. Meanwhile, the second method relies on the control of the internally stored energy of the MMC to automatically minimize the number of submodules that discharge during a dc-side fault. Therefore, both the dc-side current and the MMC arm current can be effectively suppressed after the occurrence of the fault. The proposed methods do not require fault detection and their response is proportional to the rate of rise in the fault current. Simulation case studies are presented to demonstrate the proposed methods.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"3 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83478822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221002
Kamlesh Sawant, Jungwon Choi
This paper presents discrete frequency and phase-shift control for a bidirectional class-E2 converter, enabling a wide range of output power in energy storage applications. Class-E² converters typically operate within a narrow power range to achieve zero voltage switching (ZVS) across the switching devices and ensure high efficiency. To address this limitation, we propose an adaptive frequency control algorithm that utilizes multiple frequency steps to reduce output ripple and minimize output capacitor requirements. Our adaptive frequency control algorithm ensures high efficiency across a wide output power range by using 16 discrete switching frequency steps ranging from 800 kHz to 1.6 MHz. Duty ratios are pre-computed and stored in a lookup table to provide ZVS at each frequency. We also apply a variable phase shift between the switching devices to maintain ZVS and control the power flow direction. By directly selecting and applying the appropriate frequency from the lookup table instead of sequential searching, our proposed algorithm enables faster dynamic response with minimal undershoot and overshoot. Through simulation and implementation of closed-loop control of the bidirectional class-E2 converter prototype using an MCU, we achieved bidirectional output power level variation from 13 W to 350 W with a maximum efficiency of 93.5%.
{"title":"Closed-Loop Adaptive Frequency and Phase-Shift Control of Bidirectional Class-E² Converter for Energy Storage Applications","authors":"Kamlesh Sawant, Jungwon Choi","doi":"10.1109/COMPEL52896.2023.10221002","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221002","url":null,"abstract":"This paper presents discrete frequency and phase-shift control for a bidirectional class-E2 converter, enabling a wide range of output power in energy storage applications. Class-E² converters typically operate within a narrow power range to achieve zero voltage switching (ZVS) across the switching devices and ensure high efficiency. To address this limitation, we propose an adaptive frequency control algorithm that utilizes multiple frequency steps to reduce output ripple and minimize output capacitor requirements. Our adaptive frequency control algorithm ensures high efficiency across a wide output power range by using 16 discrete switching frequency steps ranging from 800 kHz to 1.6 MHz. Duty ratios are pre-computed and stored in a lookup table to provide ZVS at each frequency. We also apply a variable phase shift between the switching devices to maintain ZVS and control the power flow direction. By directly selecting and applying the appropriate frequency from the lookup table instead of sequential searching, our proposed algorithm enables faster dynamic response with minimal undershoot and overshoot. Through simulation and implementation of closed-loop control of the bidirectional class-E2 converter prototype using an MCU, we achieved bidirectional output power level variation from 13 W to 350 W with a maximum efficiency of 93.5%.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"2 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89660836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221009
Roderick S. Bayliss, Nathan C. Brooks, R. Pilawa-Podgurski
Single-stage Power Factor Correction (PFC) ac-dc rectifiers open a pathway to achieve high power density and efficiency in grid-connected rectifier applications where the target dc voltage is lower than the peak ac voltage (e.g. data center power delivery, LED drivers). Typically in data center and similar applications, a two-stage solution employing a step-up ac-dc stage followed by a step-down dc-dc stage is employed to achieve grid to 48 V conversion. This approach suffers from the efficiency penalty of a cascade of power converters and typically lower power density due to the design of two separate power conversion stages. A single-stage, buck-type PFC rectifier where the output dc voltage is lower than the peak ac voltage circumvents these issues. This work analyzes and develops a single-stage buck-type PFC rectifier utilizing a six-level flying capacitor multilevel (FCML) converter with active flying capacitor voltage balancing and current control to achieve high power density rectification in a single-stage solution. This work is the first to achieve active balancing of capacitors combined with PFC operation in a step-down FCML rectifier.
{"title":"A Combined Power Factor Correcting and Active Voltage Balancing Control Technique for Buck-Type AC/DC Grid-Tied Flying Capacitor Multilevel Converters","authors":"Roderick S. Bayliss, Nathan C. Brooks, R. Pilawa-Podgurski","doi":"10.1109/COMPEL52896.2023.10221009","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221009","url":null,"abstract":"Single-stage Power Factor Correction (PFC) ac-dc rectifiers open a pathway to achieve high power density and efficiency in grid-connected rectifier applications where the target dc voltage is lower than the peak ac voltage (e.g. data center power delivery, LED drivers). Typically in data center and similar applications, a two-stage solution employing a step-up ac-dc stage followed by a step-down dc-dc stage is employed to achieve grid to 48 V conversion. This approach suffers from the efficiency penalty of a cascade of power converters and typically lower power density due to the design of two separate power conversion stages. A single-stage, buck-type PFC rectifier where the output dc voltage is lower than the peak ac voltage circumvents these issues. This work analyzes and develops a single-stage buck-type PFC rectifier utilizing a six-level flying capacitor multilevel (FCML) converter with active flying capacitor voltage balancing and current control to achieve high power density rectification in a single-stage solution. This work is the first to achieve active balancing of capacitors combined with PFC operation in a step-down FCML rectifier.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"36 1","pages":"1-5"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85860886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221075
Audrey Cheshire, Aarranon Bharathan, D. Maksimović
This paper presents a four-level flying capacitor multi-level (FCML) converter operating as a drain supply modulator (DSM) for radio frequency power amplifiers (RFPAs). The proposed FCML-based DSM excludes the standard output LC filter and employs a direct multi-level DSM approach, changing the output according to an external RFPA drain-supply level demand. A simple state-machine-based controller ensures that the flying capacitor voltages remain balanced for arbitrary sequences of requested output voltage levels. The functionality of the state-machine controlled converter is verified with a GaN-based DSM prototype with output voltage levels of 0V, 6.67V, 13.33 V, and 20 V generated from an input dc voltage of 20 V, and with the state-machine controller sampling period of 5$mu$s. Experimental results show the converter is able to maintain capacitor charge balance across the flying capacitors while outputting the requested RFPA level demand. The maximum output current of the converter is 0.8 A, while efficiencies measured at each output level range between 99.0-99.8%.
{"title":"Flying Capacitor Four-Level Supply Modulator with Active Balancing for RF Power Amplifier Applications","authors":"Audrey Cheshire, Aarranon Bharathan, D. Maksimović","doi":"10.1109/COMPEL52896.2023.10221075","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221075","url":null,"abstract":"This paper presents a four-level flying capacitor multi-level (FCML) converter operating as a drain supply modulator (DSM) for radio frequency power amplifiers (RFPAs). The proposed FCML-based DSM excludes the standard output LC filter and employs a direct multi-level DSM approach, changing the output according to an external RFPA drain-supply level demand. A simple state-machine-based controller ensures that the flying capacitor voltages remain balanced for arbitrary sequences of requested output voltage levels. The functionality of the state-machine controlled converter is verified with a GaN-based DSM prototype with output voltage levels of 0V, 6.67V, 13.33 V, and 20 V generated from an input dc voltage of 20 V, and with the state-machine controller sampling period of 5$mu$s. Experimental results show the converter is able to maintain capacitor charge balance across the flying capacitors while outputting the requested RFPA level demand. The maximum output current of the converter is 0.8 A, while efficiencies measured at each output level range between 99.0-99.8%.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"3 1","pages":"1-7"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82511372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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