The power system is witnessing an increasing penetration of power converters due to the integration of renewables, HVDC, DC and AC microgrids, etc. In line with this increasing penetration, the system needs units with grid-forming capabilities on the AC and DC sides. We propose a dual grid forming controller for power converters, particularly for modular multilevel converters (MMC), that forms the voltage in the DC grid and voltage and frequency on the AC grid. Nowadays, the parameter tuning of MMC controllers heavily relies on manual effort and rich engineering experience, which usually leads to suboptimal power system operation. Instead, we propose an optimal $H_{infty}$ controller, which considers AC and DC grid dynamics. We impose grid-forming conditions, among other control objectives, by using weighting functions. Finally, using a simple AC/DC grid we demonstrate that the proposed double grid forming algorithm is suitable for hybrid grid applications.
{"title":"H∞-Based Double Grid Forming Controller of Multi-Modular Converters in a Hybrid AC/DC Grid","authors":"Baron-Prada Eder, Anta Adolfo, Makoschitz Markus, Dörfler Florian","doi":"10.1109/COMPEL52896.2023.10221196","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221196","url":null,"abstract":"The power system is witnessing an increasing penetration of power converters due to the integration of renewables, HVDC, DC and AC microgrids, etc. In line with this increasing penetration, the system needs units with grid-forming capabilities on the AC and DC sides. We propose a dual grid forming controller for power converters, particularly for modular multilevel converters (MMC), that forms the voltage in the DC grid and voltage and frequency on the AC grid. Nowadays, the parameter tuning of MMC controllers heavily relies on manual effort and rich engineering experience, which usually leads to suboptimal power system operation. Instead, we propose an optimal $H_{infty}$ controller, which considers AC and DC grid dynamics. We impose grid-forming conditions, among other control objectives, by using weighting functions. Finally, using a simple AC/DC grid we demonstrate that the proposed double grid forming algorithm is suitable for hybrid grid applications.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"32 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82749098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221132
Qijia Li, Yuetao Hou, K. Afridi
Piezoelectric devices have recently emerged as a promising candidate to replace magnetic components. Past research has explored different topologies and control strategies for dc-dc converters which only use a single piezoelectric resonator as the main energy-storage component. However, such converters exhibit relatively low efficiency when the voltage conversion ratio deviates from its nominal value. In this paper, a new merged switched-capacitor piezoelectric-resonator based dc-dc converter which can achieve high and flat efficiency across a wide voltage conversion ratio is proposed. The switched capacitor and the piezoelectric resonator are combined in the proposed converter to form a multi-level structure and controlled in a manner to achieve high efficiency across a wide voltage conversion ratio. The proposed topology and control strategy enable the switched capacitor to be soft-charged by the current from the piezoelectric resonator and achieve zero-voltage-switching (ZVS) for all its switches. The steady-state operation of the proposed converter is analyzed in detail. Simulation and experimental results are presented to verify the advantages of the proposed converter. Finally, a family of merged switched-capacitor piezoelectric-resonator based dc-dc converters, based on the proposed principle, is also presented.
{"title":"Merged Switched-Capacitor Piezoelectric-Resonator Based DC-DC Converter with High Voltage Conversion Ratio","authors":"Qijia Li, Yuetao Hou, K. Afridi","doi":"10.1109/COMPEL52896.2023.10221132","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221132","url":null,"abstract":"Piezoelectric devices have recently emerged as a promising candidate to replace magnetic components. Past research has explored different topologies and control strategies for dc-dc converters which only use a single piezoelectric resonator as the main energy-storage component. However, such converters exhibit relatively low efficiency when the voltage conversion ratio deviates from its nominal value. In this paper, a new merged switched-capacitor piezoelectric-resonator based dc-dc converter which can achieve high and flat efficiency across a wide voltage conversion ratio is proposed. The switched capacitor and the piezoelectric resonator are combined in the proposed converter to form a multi-level structure and controlled in a manner to achieve high efficiency across a wide voltage conversion ratio. The proposed topology and control strategy enable the switched capacitor to be soft-charged by the current from the piezoelectric resonator and achieve zero-voltage-switching (ZVS) for all its switches. The steady-state operation of the proposed converter is analyzed in detail. Simulation and experimental results are presented to verify the advantages of the proposed converter. Finally, a family of merged switched-capacitor piezoelectric-resonator based dc-dc converters, based on the proposed principle, is also presented.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"89 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83886947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221100
Yanqiao Li, Bahlakoana Mabetha, J. Stauth
High voltage drivers are needed for electrostatic and piezoelectric actuators in small-scale electromechanical systems such as microrobotics and haptics. This paper presents a miniaturized platform for a modular switched-capacitor-based driver, implemented in a 180nm HV-SOI CMOS integrated circuit (IC), that uses less than 5 $mu$A quiescent current per chip and includes an auxiliary (magnetic) boost converter to interface with low-voltage (~2.5-3.7V) batteries. The platform allows multiple PCB modules to stack in series voltage domains, extending drive voltages to the kilovolt-range, beyond the process and buried-oxide (BOX) limits of a single chip. Compared to past work with the same IC [1], the improved platform achieves >100$times$ volume reduction and >30$times$ weight reduction; with eight boards stacked, the system can provide peak-peak drive voltages up to 3 kV from a 3.7V supply (voltage conversion ratios VCR >800), delivering and recovering ~1W reactive power with over 97% efficiency.
{"title":"A Miniaturized Platform for a Modular High-Voltage Electrostatic Actuator Driver","authors":"Yanqiao Li, Bahlakoana Mabetha, J. Stauth","doi":"10.1109/COMPEL52896.2023.10221100","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221100","url":null,"abstract":"High voltage drivers are needed for electrostatic and piezoelectric actuators in small-scale electromechanical systems such as microrobotics and haptics. This paper presents a miniaturized platform for a modular switched-capacitor-based driver, implemented in a 180nm HV-SOI CMOS integrated circuit (IC), that uses less than 5 $mu$A quiescent current per chip and includes an auxiliary (magnetic) boost converter to interface with low-voltage (~2.5-3.7V) batteries. The platform allows multiple PCB modules to stack in series voltage domains, extending drive voltages to the kilovolt-range, beyond the process and buried-oxide (BOX) limits of a single chip. Compared to past work with the same IC [1], the improved platform achieves >100$times$ volume reduction and >30$times$ weight reduction; with eight boards stacked, the system can provide peak-peak drive voltages up to 3 kV from a 3.7V supply (voltage conversion ratios VCR >800), delivering and recovering ~1W reactive power with over 97% efficiency.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"2 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88485744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221096
Alireza Ramyar, Yukun Lou, A. Avestruz
High breakdown voltage, low on-resistance, and high speed have made wide-bandgap power semiconductors suitable for many applications such as wireless power transfer, electric vehicles, hybrid and electric aircraft, and aerospace. However, the maximum power density of these devices is limited by the channel temperature rise. Thus, accurate temperature measurement of the active area is essential in research on wide-bandgap power semiconductors, which is often hampered by packaging and cooling methods. Employing temperature sensitive electrical parameters (TSEP) is a promising approach for the temperature measurement of power semiconductors. This paper uses a vector of three TSEPs, i.e., the gate-source voltage biased at weak, moderate, and strong inversion regions, to extract more information for accurate temperature measurement of the active area in GaN FETs.
{"title":"Accurate Temperature Measurement of Active Area for Wide-Bandgap Power Semiconductors","authors":"Alireza Ramyar, Yukun Lou, A. Avestruz","doi":"10.1109/COMPEL52896.2023.10221096","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221096","url":null,"abstract":"High breakdown voltage, low on-resistance, and high speed have made wide-bandgap power semiconductors suitable for many applications such as wireless power transfer, electric vehicles, hybrid and electric aircraft, and aerospace. However, the maximum power density of these devices is limited by the channel temperature rise. Thus, accurate temperature measurement of the active area is essential in research on wide-bandgap power semiconductors, which is often hampered by packaging and cooling methods. Employing temperature sensitive electrical parameters (TSEP) is a promising approach for the temperature measurement of power semiconductors. This paper uses a vector of three TSEPs, i.e., the gate-source voltage biased at weak, moderate, and strong inversion regions, to extract more information for accurate temperature measurement of the active area in GaN FETs.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"86 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88534796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221103
T. Kato, Kaoru Inoue, Yoshiki Miwa, Takaya Karino
This paper proposes a unified admittance measurement method for a three-phase system which is described in the stationary or in the synchronous domain only by two-phase excitation with sinusoidal waveforms in positive and negative frequency components. There are frequency couplings in the two components when the system is asymmetric. A measurement method that scans for a desired frequency range is proposed. It is based on two-phase voltage application and response current measurement processes at coupling frequencies. Two applications examples, a resistive-inductive (RL) circuit and an IPM motor in a respective domain, are investigated to validate the proposed measurement method for unified admittances.
{"title":"Measurement of Unified Admittance Model for Three-Phase System by Two-Phase Excitation","authors":"T. Kato, Kaoru Inoue, Yoshiki Miwa, Takaya Karino","doi":"10.1109/COMPEL52896.2023.10221103","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221103","url":null,"abstract":"This paper proposes a unified admittance measurement method for a three-phase system which is described in the stationary or in the synchronous domain only by two-phase excitation with sinusoidal waveforms in positive and negative frequency components. There are frequency couplings in the two components when the system is asymmetric. A measurement method that scans for a desired frequency range is proposed. It is based on two-phase voltage application and response current measurement processes at coupling frequencies. Two applications examples, a resistive-inductive (RL) circuit and an IPM motor in a respective domain, are investigated to validate the proposed measurement method for unified admittances.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"25 1","pages":"1-7"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85288771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221076
Jacob R. Anderson, Mike K. Ranjram
Core loss is often reported using power-law fits on a limited amount of data collected on a single core shape. The development of automated testers which output a full ‘loss map’ is one approach towards improving this reporting. Conventional measurement techniques are automatable but only to 500 kHz-1MHz. In this paper, we develop an automated core loss tester suitable for the > 1MHz regime and discuss its implementation and trade-offs. The tester produces data that is within 12.6%-57% of manufacturer-reported data, following similar trends for flux-density versus power loss density but tending to overestimate core loss. Sources of error in the automation procedure are discussed as well as strategies for future improvement of the system.
{"title":"Automation of High-Frequency Magnetic Core Loss Data Collection","authors":"Jacob R. Anderson, Mike K. Ranjram","doi":"10.1109/COMPEL52896.2023.10221076","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221076","url":null,"abstract":"Core loss is often reported using power-law fits on a limited amount of data collected on a single core shape. The development of automated testers which output a full ‘loss map’ is one approach towards improving this reporting. Conventional measurement techniques are automatable but only to 500 kHz-1MHz. In this paper, we develop an automated core loss tester suitable for the > 1MHz regime and discuss its implementation and trade-offs. The tester produces data that is within 12.6%-57% of manufacturer-reported data, following similar trends for flux-density versus power loss density but tending to overestimate core loss. Sources of error in the automation procedure are discussed as well as strategies for future improvement of the system.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"115 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81253451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221073
L. Horowitz, Nathan C. Brooks, N. Ellis, R. Pilawa-Podgurski
In this work, we combine two popular power conversion topologies, the flying capacitor multilevel (FCML) converter and the LLC converter, to arrive at the proposed flying capacitor LLC (FCLLC) solution with advantages of each. The FCLLC comprises a step-down resonant switched-capacitor (ReSC) stage followed by a resonant transformer-based stage which provides soft charging of the flying capacitors, galvanic isolation, and an additional step-down through the transformer. These conversion ratios are multiplied, making the FCLLC especially suited for extreme conversion ratios. An FCLLC prototype capable of direct 400V to 1V conversion is fabricated, which demonstrates the potential this topology has for future datacenter applications.
{"title":"The Flying Capacitor LLC Converter: A Hybrid Switched Capacitor Converter with Galvanic Isolation for Large Step-Down Applications","authors":"L. Horowitz, Nathan C. Brooks, N. Ellis, R. Pilawa-Podgurski","doi":"10.1109/COMPEL52896.2023.10221073","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221073","url":null,"abstract":"In this work, we combine two popular power conversion topologies, the flying capacitor multilevel (FCML) converter and the LLC converter, to arrive at the proposed flying capacitor LLC (FCLLC) solution with advantages of each. The FCLLC comprises a step-down resonant switched-capacitor (ReSC) stage followed by a resonant transformer-based stage which provides soft charging of the flying capacitors, galvanic isolation, and an additional step-down through the transformer. These conversion ratios are multiplied, making the FCLLC especially suited for extreme conversion ratios. An FCLLC prototype capable of direct 400V to 1V conversion is fabricated, which demonstrates the potential this topology has for future datacenter applications.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"121 1","pages":"1-7"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75259351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221163
D. Menzi, S. Weihe, J. A. Anderson, M. Kasper, J. Huber, J. Kolar
On-Board Chargers (OBCs) comprising an ac-dc front-end and a subsequent isolated dc-dc converter stage represent a crucial component of Electric Vehicles (EVs), and must be able to charge the EV battery from both, a three-phase mains and a single-phase mains. Further, a lightweight and compact realization of the OBC is key in mobile applications. This requirement for high gravimetric and volumetric power density is often hindered by the large (electrolytic) dc-link capacitor required to buffer the power pulsation at twice the mains frequency in single-phase operation, which can be omitted by employing an active Power Pulsation Buffer (PPB) circuit allowing to minimize the overall capacitor volume. This paper proposes a novel Smart-dc-Link (S-Link) concept which improves the OBC performance by utilizing the active PPB circuitry also in three-phase operation. There, the S-Link facilitates a six-pulse dc-link voltage variation enabling a substantial switching loss reduction in the ac-dc converter front-end, while advantageously the dc output voltage can be kept constant.
{"title":"Novel S-Link Enabling Ultra-Compact and Ultra-Efficient Three-Phase and Single-Phase Operable On-Board EV Chargers","authors":"D. Menzi, S. Weihe, J. A. Anderson, M. Kasper, J. Huber, J. Kolar","doi":"10.1109/COMPEL52896.2023.10221163","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221163","url":null,"abstract":"On-Board Chargers (OBCs) comprising an ac-dc front-end and a subsequent isolated dc-dc converter stage represent a crucial component of Electric Vehicles (EVs), and must be able to charge the EV battery from both, a three-phase mains and a single-phase mains. Further, a lightweight and compact realization of the OBC is key in mobile applications. This requirement for high gravimetric and volumetric power density is often hindered by the large (electrolytic) dc-link capacitor required to buffer the power pulsation at twice the mains frequency in single-phase operation, which can be omitted by employing an active Power Pulsation Buffer (PPB) circuit allowing to minimize the overall capacitor volume. This paper proposes a novel Smart-dc-Link (S-Link) concept which improves the OBC performance by utilizing the active PPB circuitry also in three-phase operation. There, the S-Link facilitates a six-pulse dc-link voltage variation enabling a substantial switching loss reduction in the ac-dc converter front-end, while advantageously the dc output voltage can be kept constant.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"50 1","pages":"1-7"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73618289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221149
Yicheng Zhu, Ting Ge, N. Ellis, Jiarui Zou, R. Pilawa-Podgurski
This paper presents an ultra-high-current switching bus converter with direct 48-V-to-1-V power conversion for next-generation ultra-high-power digital loads (e.g., CPUs, GPUs, ASICs, etc.). In the proposed topology, two 2-to-1 switched-capacitor (SC) front-ends are merged with four 10-branch series-capacitor buck (SCB) modules through two switching buses. Compared to the DC-bus-based architecture, the switching-bus-based architecture does not require DC bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. Through two-phase operation within each SCB module, the switching bus converter extends the maximum duty ratio and achieves a very large SC stage conversion ratio of 20-to-1. Compared to existing 48-V-to-1-V hybrid SC demonstrations, the proposed topology has the lowest normalized switch stress and the smallest normalized passive component volume, showing great potential for both higher efficiency and higher power density than prior solutions. A 48-V-to-1-V hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards. Hybrid gate drive circuitry comprising gate-driven charge pump circuits and cascaded bootstrap circuits was customized for the high-side switches in the SCB modules to overcome the challenge of accumulative voltage drops in the conventional cascaded bootstrap circuit. The hardware prototype was tested up to 1200-A output current and achieved 92.4% peak system efficiency, 87.5% full-load efficiency (including gate drive loss), and 607 W/in3 power density (by box volume).
{"title":"A 48-V-to-1-V Switching Bus Converter for Ultra-High-Current Applications","authors":"Yicheng Zhu, Ting Ge, N. Ellis, Jiarui Zou, R. Pilawa-Podgurski","doi":"10.1109/COMPEL52896.2023.10221149","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221149","url":null,"abstract":"This paper presents an ultra-high-current switching bus converter with direct 48-V-to-1-V power conversion for next-generation ultra-high-power digital loads (e.g., CPUs, GPUs, ASICs, etc.). In the proposed topology, two 2-to-1 switched-capacitor (SC) front-ends are merged with four 10-branch series-capacitor buck (SCB) modules through two switching buses. Compared to the DC-bus-based architecture, the switching-bus-based architecture does not require DC bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. Through two-phase operation within each SCB module, the switching bus converter extends the maximum duty ratio and achieves a very large SC stage conversion ratio of 20-to-1. Compared to existing 48-V-to-1-V hybrid SC demonstrations, the proposed topology has the lowest normalized switch stress and the smallest normalized passive component volume, showing great potential for both higher efficiency and higher power density than prior solutions. A 48-V-to-1-V hardware prototype was designed and built with custom four-phase coupled inductors and gate drive daughterboards. Hybrid gate drive circuitry comprising gate-driven charge pump circuits and cascaded bootstrap circuits was customized for the high-side switches in the SCB modules to overcome the challenge of accumulative voltage drops in the conventional cascaded bootstrap circuit. The hardware prototype was tested up to 1200-A output current and achieved 92.4% peak system efficiency, 87.5% full-load efficiency (including gate drive loss), and 607 W/in3 power density (by box volume).","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"57 1","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75625576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-25DOI: 10.1109/COMPEL52896.2023.10221032
J. Motwani, Jian Liu, D. Boroyevich, R. Burgos, D. Dong
There has been a notable increase in the demand for medium-voltage high-power converters for applications like electric vehicle charging stations (EVCS), energy storage integration (ESS) and power hungry data centers. Additionally, for EVCS and ESS applications, converters are preferred to be bidirectional to support the grid, while also being modular to assist with redundancy. Modular multilevel converters (MMCs), which have gained significant prominence in high-voltage applications, have also found their way into aforementioned medium-voltage applications due to their excellent modularity and power quality. However, the high costs and large footprint of MMCs present obstacles to the wider adoption. Recently several other families of converters have emerged as potential alternatives for both high and medium-voltage domains. Among these alternatives, two stand out as particularly promising options: alternate-arm-converters, and hybrid-MMCs. Each of these families has unique advantages, limitations, and optimal operation areas, making them suitable for different uses. However, to date, no comprehensive and quantitative research has been conducted to compare these topologies and highlight their optimal operation points. This lack of objective quantification and clear selection criteria has greatly hindered their industrial adoption. This research paper aims to address this gap by comparing the three major converter families in terms of devices utilized, submodule capacitance, semiconductor losses and other practical considerations. The paper concludes by presenting comprehensive selection guidelines that offer a clear delineation among converters and their application scopes.
{"title":"A Comparative Evaluation between Hybrid Modular Multi-Level Converters and Alternate Arm Converter","authors":"J. Motwani, Jian Liu, D. Boroyevich, R. Burgos, D. Dong","doi":"10.1109/COMPEL52896.2023.10221032","DOIUrl":"https://doi.org/10.1109/COMPEL52896.2023.10221032","url":null,"abstract":"There has been a notable increase in the demand for medium-voltage high-power converters for applications like electric vehicle charging stations (EVCS), energy storage integration (ESS) and power hungry data centers. Additionally, for EVCS and ESS applications, converters are preferred to be bidirectional to support the grid, while also being modular to assist with redundancy. Modular multilevel converters (MMCs), which have gained significant prominence in high-voltage applications, have also found their way into aforementioned medium-voltage applications due to their excellent modularity and power quality. However, the high costs and large footprint of MMCs present obstacles to the wider adoption. Recently several other families of converters have emerged as potential alternatives for both high and medium-voltage domains. Among these alternatives, two stand out as particularly promising options: alternate-arm-converters, and hybrid-MMCs. Each of these families has unique advantages, limitations, and optimal operation areas, making them suitable for different uses. However, to date, no comprehensive and quantitative research has been conducted to compare these topologies and highlight their optimal operation points. This lack of objective quantification and clear selection criteria has greatly hindered their industrial adoption. This research paper aims to address this gap by comparing the three major converter families in terms of devices utilized, submodule capacitance, semiconductor losses and other practical considerations. The paper concludes by presenting comprehensive selection guidelines that offer a clear delineation among converters and their application scopes.","PeriodicalId":55233,"journal":{"name":"Compel-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering","volume":"62 5","pages":"1-8"},"PeriodicalIF":0.7,"publicationDate":"2023-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72577582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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