Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643958
B. Bercu, L. Montès, P. Morfouli
The objective of this contribution is the optimization of the response of a piezoresistive pressure sensor integrated into a heat spreader for microelectronic applications. Finite element analysis (FEA) calculations are employed to simulate the sensor behavior taking into account mechanical, thermal and electrical effects. The small sensors membrane area (150times150mum2) imposed by the heat spreader geometry, requires the use of an ultra thin membrane (thickness less than 1mum) for an optimal sensitivity. SOI technology is used in order to insure a better uniformity over the wafer. A double-side oxidized membrane configuration is analyzed in order to reduce the effects of the residual stress present in the membrane
{"title":"FEA Calculations for Ultra Thin Piezoresistive Pressure Sensor on SOI for Heatspreader Integration","authors":"B. Bercu, L. Montès, P. Morfouli","doi":"10.1109/ESIME.2006.1643958","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643958","url":null,"abstract":"The objective of this contribution is the optimization of the response of a piezoresistive pressure sensor integrated into a heat spreader for microelectronic applications. Finite element analysis (FEA) calculations are employed to simulate the sensor behavior taking into account mechanical, thermal and electrical effects. The small sensors membrane area (150times150mum2) imposed by the heat spreader geometry, requires the use of an ultra thin membrane (thickness less than 1mum) for an optimal sensitivity. SOI technology is used in order to insure a better uniformity over the wafer. A double-side oxidized membrane configuration is analyzed in order to reduce the effects of the residual stress present in the membrane","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80959188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644011
D. Peyrou, P. Pons, H. Granier, D. Leray, A. Ferrand, K. Yacine, M. Saadaoui, A. Nicolas, J. Tao, R. Plana
This paper presents a study on multiphysics software reliability provided by COMSOL and ANSYS. The goal is to give an overview about the fundamentals of how to set up RF simulations, mechanical contact and residual stress through three examples chosen as the main key points in order to make in the future a highly coupled model of the RF MEMS switches packaging
{"title":"Multiphysics Softwares Benchmark on Ansys / Comsol Applied For RF MEMS Switches Packaging Simulations","authors":"D. Peyrou, P. Pons, H. Granier, D. Leray, A. Ferrand, K. Yacine, M. Saadaoui, A. Nicolas, J. Tao, R. Plana","doi":"10.1109/ESIME.2006.1644011","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644011","url":null,"abstract":"This paper presents a study on multiphysics software reliability provided by COMSOL and ANSYS. The goal is to give an overview about the fundamentals of how to set up RF simulations, mechanical contact and residual stress through three examples chosen as the main key points in order to make in the future a highly coupled model of the RF MEMS switches packaging","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"1 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76634194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643990
A. Hirshberg, D. Elata
A new test device for measuring strength of brittle microbeams was recently proposed. This test device requires no measurement of applied forces or of deformation. In this work, the theoretical analysis that explains how the strength of microbeams may be deduced from the length of the remaining ligament of broken beams is presented
{"title":"Measuring the Strength of Brittle Microbeams Without Measuring Forces or Displacements","authors":"A. Hirshberg, D. Elata","doi":"10.1109/ESIME.2006.1643990","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643990","url":null,"abstract":"A new test device for measuring strength of brittle microbeams was recently proposed. This test device requires no measurement of applied forces or of deformation. In this work, the theoretical analysis that explains how the strength of microbeams may be deduced from the length of the remaining ligament of broken beams is presented","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"70 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83164266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643989
D. Elata, E. Elka, H. Abramovich
The constitutive equations of multi-layered piezoelectric structures are derived in a new form. In this form, the electromechanical coupling is presented as an additional stiffness matrix. This matrix is a true property of the piezoelectric structure and is independent of specific mechanical boundary conditions that may apply to the structure. A novel model of the electromechanical response of such structures is presented. This model accounts for the 3D kinematics of the structure deformation. Solution of example problems using the new model shows excellent agreement with full 3D finite element simulations. These solutions are also compared with the results of previous 2D model approximations presented in literature, and the inaccuracies associated with these previous models are discussed
{"title":"Analytic Model of the Deflection of Piezoelectric Unimorph and Bimorph Structures with Numerical Verification","authors":"D. Elata, E. Elka, H. Abramovich","doi":"10.1109/ESIME.2006.1643989","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643989","url":null,"abstract":"The constitutive equations of multi-layered piezoelectric structures are derived in a new form. In this form, the electromechanical coupling is presented as an additional stiffness matrix. This matrix is a true property of the piezoelectric structure and is independent of specific mechanical boundary conditions that may apply to the structure. A novel model of the electromechanical response of such structures is presented. This model accounts for the 3D kinematics of the structure deformation. Solution of example problems using the new model shows excellent agreement with full 3D finite element simulations. These solutions are also compared with the results of previous 2D model approximations presented in literature, and the inaccuracies associated with these previous models are discussed","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"60 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73792722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643957
C. Méndez, C. Louis, S. Paquay, P. De Vincenzo, I. Klapka, V. Rochus, F. Iker, N. André, J. Raskin
In this paper we present out-of-plane 3D self assembled SOI (silicon-on-insulator) MEMS that can be directly integrated to the electronic components. Because of their 3D nature, these structures can be used, for instance, as the basic elements for the construction of thermal actuators or flow sensors. We make a description of the fabrication and operation of these devices and we show how these two stages can be numerically simulated
{"title":"Modeling of the Fabrication and Operation of 3-D Self-Assembled SOI MEMS","authors":"C. Méndez, C. Louis, S. Paquay, P. De Vincenzo, I. Klapka, V. Rochus, F. Iker, N. André, J. Raskin","doi":"10.1109/ESIME.2006.1643957","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643957","url":null,"abstract":"In this paper we present out-of-plane 3D self assembled SOI (silicon-on-insulator) MEMS that can be directly integrated to the electronic components. Because of their 3D nature, these structures can be used, for instance, as the basic elements for the construction of thermal actuators or flow sensors. We make a description of the fabrication and operation of these devices and we show how these two stages can be numerically simulated","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"118 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80322211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644041
O. van der Sluis, R. Engelen, W. V. van Driel, M. van Gils, R. van Silfhout
This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken
{"title":"Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy","authors":"O. van der Sluis, R. Engelen, W. V. van Driel, M. van Gils, R. van Silfhout","doi":"10.1109/ESIME.2006.1644041","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644041","url":null,"abstract":"This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"190 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77724957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643963
J. Thijsse, W. V. van Driel, M. van Gils, O. van der Sluis
Currently, prediction of interface strength is typically done using the critical energy release rate. Interface strength, however, is heavily dependent on mode mixity. Accurately predicting delamination therefore requires a material model that includes the mode dependency of interface strength. A novel test setup is designed which allows mixed mode delamination testing. The setup is a stabilized version of the mixed mode bending test previously described by Reeder and Crews (1990, 1991). It allows for the measurement of stable crack growth over the full range of mode mixities, using a single specimen design. The crack length, necessary for calculation of the energy release rate, is obtained from an analytical model. Crack length and displacement data are used in a finite element model containing a crack tip to calculate the mode mixity
{"title":"Interfacial Adhesion Method for Semiconductor Applications Covering the Full Mode Mixity","authors":"J. Thijsse, W. V. van Driel, M. van Gils, O. van der Sluis","doi":"10.1109/ESIME.2006.1643963","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643963","url":null,"abstract":"Currently, prediction of interface strength is typically done using the critical energy release rate. Interface strength, however, is heavily dependent on mode mixity. Accurately predicting delamination therefore requires a material model that includes the mode dependency of interface strength. A novel test setup is designed which allows mixed mode delamination testing. The setup is a stabilized version of the mixed mode bending test previously described by Reeder and Crews (1990, 1991). It allows for the measurement of stable crack growth over the full range of mode mixities, using a single specimen design. The crack length, necessary for calculation of the energy release rate, is obtained from an analytical model. Crack length and displacement data are used in a finite element model containing a crack tip to calculate the mode mixity","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"9 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87848367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643947
S. Irving, Y. Liu, D. Connerny, T. Luk
The operational characteristics of silicon devices are strongly influenced by device temperature. For SOI devices power dissipation is a much more significant challenge than for non-SOI devices. As a result the thermal design of SOI devices is vital to proper product performance. To maximize the engineering understanding of SOI circuits we develop a method to examine the combined system of SOI device and the package by finite element analysis. These results are compared to results obtained from an equivalent electrical model. The use of on die structures as an aide to heat dissipation is explored
{"title":"SOI Die Heat Transfer Analysis from Device to Assembly Package","authors":"S. Irving, Y. Liu, D. Connerny, T. Luk","doi":"10.1109/ESIME.2006.1643947","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643947","url":null,"abstract":"The operational characteristics of silicon devices are strongly influenced by device temperature. For SOI devices power dissipation is a much more significant challenge than for non-SOI devices. As a result the thermal design of SOI devices is vital to proper product performance. To maximize the engineering understanding of SOI circuits we develop a method to examine the combined system of SOI device and the package by finite element analysis. These results are compared to results obtained from an equivalent electrical model. The use of on die structures as an aide to heat dissipation is explored","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"13 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88873064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643961
W. Driel, H. P. Hochstenbach, Guoqi Zhang
Wafer level packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years we have seen a tremendous growth in the application of wafer level packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without it's challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of wafer level packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of wafer level packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within wafer level packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the under bump metallisation. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Different repassivation materials and different structures are explored to their potential reliability benefits. By combining the experimental results with reliability prediction models and advanced simulation-based optimisation methods, the complete wafer level package design space in terms of distance from neutral point, PCB thickness, PCB copper layout, and use of improved structures is explored. Our numerical results explain the experimentally obtained reliability results for the effects of package size and PCB thickness. Even more, they indicate that by properly designing the copper layout in the PCB, a 10-20% improvement can be achieved for the WLP 2nd level reliability
{"title":"Design for Reliability of Wafer Level Packages","authors":"W. Driel, H. P. Hochstenbach, Guoqi Zhang","doi":"10.1109/ESIME.2006.1643961","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643961","url":null,"abstract":"Wafer level packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years we have seen a tremendous growth in the application of wafer level packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without it's challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of wafer level packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of wafer level packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within wafer level packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the under bump metallisation. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Different repassivation materials and different structures are explored to their potential reliability benefits. By combining the experimental results with reliability prediction models and advanced simulation-based optimisation methods, the complete wafer level package design space in terms of distance from neutral point, PCB thickness, PCB copper layout, and use of improved structures is explored. Our numerical results explain the experimentally obtained reliability results for the effects of package size and PCB thickness. Even more, they indicate that by properly designing the copper layout in the PCB, a 10-20% improvement can be achieved for the WLP 2nd level reliability","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"118 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76448542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643998
A. Augustin, T. Hauck, A. Ghazinour
The paper presents the thermal design process of a transmitter chip by means of analytical solutions and numerical simulation. Thermo-electrical models representing the heat transfer mechanisms were developed. Parametric simulation studies have been applied for the device optimization. Special emphasis was put onto the multi-scale problem that appears with very small heat sources and dimensions in the square-micrometer range respectively. Submodeling technique is used to manage associated numerical difficulties. A parametric model is generated for a transmitter module with multiple transistor blocks on single chip. The model is validated by analytical solutions for heat sources on finite regions and associated experimental temperature measurements on wafer. Solutions and results of the parametric design studies are presented
{"title":"Thermo-Electric Simulation of a 77GHz Radar Transmitter Chip for Automotive Applications","authors":"A. Augustin, T. Hauck, A. Ghazinour","doi":"10.1109/ESIME.2006.1643998","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643998","url":null,"abstract":"The paper presents the thermal design process of a transmitter chip by means of analytical solutions and numerical simulation. Thermo-electrical models representing the heat transfer mechanisms were developed. Parametric simulation studies have been applied for the device optimization. Special emphasis was put onto the multi-scale problem that appears with very small heat sources and dimensions in the square-micrometer range respectively. Submodeling technique is used to manage associated numerical difficulties. A parametric model is generated for a transmitter module with multiple transistor blocks on single chip. The model is validated by analytical solutions for heat sources on finite regions and associated experimental temperature measurements on wafer. Solutions and results of the parametric design studies are presented","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86185376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：