Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643943
L. Del Tin, R. Gaddi, A. Gnudi, E. Rudnyi, A. Greiner, J. Korvink
A simulation methodology to reduce computational time of pre-stressed harmonic analysis of radio frequency (RF) microresonators is demonstrated. The methodology is based on the application of model order reduction to a system of ordinary differential equations obtained after spatial discretization by finite element software. Model order reduction produces a low dimensional approximation of the original system and hence enables a substantial reduction of simulation time while maintaining a very small approximation error. The approach allows performing rapid device design and optimization. Once the device design and working conditions have been defined its reduced model can also be used to implement a behavioural model that can be employed in system level simulations
{"title":"Efficient Pre-stressed Harmonic Analysis of RF-Microresonators by Means of Model Order Reduction","authors":"L. Del Tin, R. Gaddi, A. Gnudi, E. Rudnyi, A. Greiner, J. Korvink","doi":"10.1109/ESIME.2006.1643943","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643943","url":null,"abstract":"A simulation methodology to reduce computational time of pre-stressed harmonic analysis of radio frequency (RF) microresonators is demonstrated. The methodology is based on the application of model order reduction to a system of ordinary differential equations obtained after spatial discretization by finite element software. Model order reduction produces a low dimensional approximation of the original system and hence enables a substantial reduction of simulation time while maintaining a very small approximation error. The approach allows performing rapid device design and optimization. Once the device design and working conditions have been defined its reduced model can also be used to implement a behavioural model that can be employed in system level simulations","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76515822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643944
S.T. Wang, Mei-Hui Chung, Chunlei Yu
Surface transverse waves (STW) resonators exhibit substantial advantages over conventional surface acoustic wave (SAW) resonators. They demonstrate higher operating frequencies, better temperature stability, higher intrinsic material quality, and etc. In this work, two low loss and high quality factor STW resonators with center frequencies at 622MHz and 1244MHz for SONET/SDH were uniquely designed and fabricated on quartz substrate. The insertion loss of the devices was as low as 3dB, loaded quality factor was as high as 1600, and sidelobe suppression reached 30dB. The temperature behavior of these two resonators were also presented by experiment with turnover temperatures at about 50degC for 622MHz and 20degC for 1244MHz, repectively
{"title":"Design of High Performance Surface Transverse Waver Resonators","authors":"S.T. Wang, Mei-Hui Chung, Chunlei Yu","doi":"10.1109/ESIME.2006.1643944","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643944","url":null,"abstract":"Surface transverse waves (STW) resonators exhibit substantial advantages over conventional surface acoustic wave (SAW) resonators. They demonstrate higher operating frequencies, better temperature stability, higher intrinsic material quality, and etc. In this work, two low loss and high quality factor STW resonators with center frequencies at 622MHz and 1244MHz for SONET/SDH were uniquely designed and fabricated on quartz substrate. The insertion loss of the devices was as low as 3dB, loaded quality factor was as high as 1600, and sidelobe suppression reached 30dB. The temperature behavior of these two resonators were also presented by experiment with turnover temperatures at about 50degC for 622MHz and 20degC for 1244MHz, repectively","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77065250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643971
A. Pandolfi, M. Ortiz
We present a new design of PDMS microvalves based on bistable configuration of the separation membrane. PDMS elastomers are sensitive to several chemical solvents, which induce changes in the mechanical properties and swelling of the material. By using a soft rubber constitutive model, we numerically analyze the performance of new design of microvalves and microfluidic systems, able to reduce the magnitude of the activation pressure and the duration of the activation time
{"title":"Modeling New Design of Fluidic Microvalves","authors":"A. Pandolfi, M. Ortiz","doi":"10.1109/ESIME.2006.1643971","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643971","url":null,"abstract":"We present a new design of PDMS microvalves based on bistable configuration of the separation membrane. PDMS elastomers are sensitive to several chemical solvents, which induce changes in the mechanical properties and swelling of the material. By using a soft rubber constitutive model, we numerically analyze the performance of new design of microvalves and microfluidic systems, able to reduce the magnitude of the activation pressure and the duration of the activation time","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77467350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643984
A. Corigliano, F. Cacchione, A. Frangi, S. Zerbini
The problem of impact rupture in polysilicon MEMS is addressed in this paper employing a numerical 2D geometrical model of the polycrystal obtained by means of a Voronoi tessellation coupled with a FE mesh. The intergranular and transgranular rupture is simulated by means of cohesive traction-jumps softening laws; accidental drop is simulated through a simplified three-level multi scale approach
{"title":"Simulation of Impact Rupture in Polysilicon Mems","authors":"A. Corigliano, F. Cacchione, A. Frangi, S. Zerbini","doi":"10.1109/ESIME.2006.1643984","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643984","url":null,"abstract":"The problem of impact rupture in polysilicon MEMS is addressed in this paper employing a numerical 2D geometrical model of the polycrystal obtained by means of a Voronoi tessellation coupled with a FE mesh. The intergranular and transgranular rupture is simulated by means of cohesive traction-jumps softening laws; accidental drop is simulated through a simplified three-level multi scale approach","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83238299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644042
J. Auersperg, R. Dudek, B. Michel
Microelectronic assemblies are basically compounds of several high precision materials with quite different Young's moduli and thermal expansion coefficients (CTE). Additionally, various kinds of inhomogeneity, residual stresses generated by several steps of the manufacturing process and extreme thermal environmental conditions contribute to interface delamination, chip cracking and fatigue of solder interconnects. For that reason, numerical investigations by means of nonlinear FEA together with conventional strength hypotheses are frequently used for design optimizations and sensitivity analyses. So, design studies on the basis of parameterized FE-models and DOE/RSM-approaches help to optimize electronic components at early phases of the product development process. But, this methodology typically bases on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches, whereas delamination or bulk fracture mechanisms usually remain unconsidered. By means of a representative microelectronics assembly this contribution is going to figure out and discuss ways and challenges of using numerical fatigue evaluation and fracture mechanics approaches in connection with parameterized finite element modeling based DOE/RSM-concepts. That is, the evaluation of mixed mode interface delamination phenomena utilizing the VCCT-methodology, classical strength hypotheses along with fracture mechanics approaches and modified Coffin-Manson thermal fatigue estimation of solder joints will be simultaneously applied within a multi-objective optimization towards a thermo-mechanical reliable design
{"title":"Combined Fracture, Delamination Risk and Fatigue Evaluation of Advanced Microelectronics Applications towards RSM/DOE Concepts","authors":"J. Auersperg, R. Dudek, B. Michel","doi":"10.1109/ESIME.2006.1644042","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644042","url":null,"abstract":"Microelectronic assemblies are basically compounds of several high precision materials with quite different Young's moduli and thermal expansion coefficients (CTE). Additionally, various kinds of inhomogeneity, residual stresses generated by several steps of the manufacturing process and extreme thermal environmental conditions contribute to interface delamination, chip cracking and fatigue of solder interconnects. For that reason, numerical investigations by means of nonlinear FEA together with conventional strength hypotheses are frequently used for design optimizations and sensitivity analyses. So, design studies on the basis of parameterized FE-models and DOE/RSM-approaches help to optimize electronic components at early phases of the product development process. But, this methodology typically bases on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches, whereas delamination or bulk fracture mechanisms usually remain unconsidered. By means of a representative microelectronics assembly this contribution is going to figure out and discuss ways and challenges of using numerical fatigue evaluation and fracture mechanics approaches in connection with parameterized finite element modeling based DOE/RSM-concepts. That is, the evaluation of mixed mode interface delamination phenomena utilizing the VCCT-methodology, classical strength hypotheses along with fracture mechanics approaches and modified Coffin-Manson thermal fatigue estimation of solder joints will be simultaneously applied within a multi-objective optimization towards a thermo-mechanical reliable design","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83187966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643999
T. Hauck, G. Li, A. McNeill, H. Knoll, M. Ebert, J. Bagdahn
Drop testing of micromachined accelerometers from the height of a table top to a solid surface shows that a moderate impact can result in severe damage of transducer elements. The relative high stiffness of the accelerometer device in combination with a high contact stiffness of the solid surface cause extremely high acceleration pulses at the impact. This paper presents a detailed analysis of the consequences of dropping a micromachined transducer structure to a solid surface. The analysis is composed of experimental testing and numerical simulation. Impact forces are measured for bare sensor chips and molded sensor devices by means of an instrumented drop test. Structural simulation models are generated for micromachined transducers. These models consider the dynamics of the deformation behavior of moveable elements including a travel stop and associated possible impact inside the sensor element. Maximum stresses are calculated in critical regions of the transducer. Weibull theory and statistical distributions of material strength are considered in order to predict the probability for crack initiation due to stress concentrations
{"title":"Drop Simulation and Stress Analysis of MEMS Devices","authors":"T. Hauck, G. Li, A. McNeill, H. Knoll, M. Ebert, J. Bagdahn","doi":"10.1109/ESIME.2006.1643999","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643999","url":null,"abstract":"Drop testing of micromachined accelerometers from the height of a table top to a solid surface shows that a moderate impact can result in severe damage of transducer elements. The relative high stiffness of the accelerometer device in combination with a high contact stiffness of the solid surface cause extremely high acceleration pulses at the impact. This paper presents a detailed analysis of the consequences of dropping a micromachined transducer structure to a solid surface. The analysis is composed of experimental testing and numerical simulation. Impact forces are measured for bare sensor chips and molded sensor devices by means of an instrumented drop test. Structural simulation models are generated for micromachined transducers. These models consider the dynamics of the deformation behavior of moveable elements including a travel stop and associated possible impact inside the sensor element. Maximum stresses are calculated in critical regions of the transducer. Weibull theory and statistical distributions of material strength are considered in order to predict the probability for crack initiation due to stress concentrations","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74383717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643949
Y. Liu, S. Irving, D. Desbiens, T. Luk
The manufacturing process for package assembly is a key to assuring the reliability and quality of the semiconductor products. There are a significant number of challenging mechanics problems in assembly manufacturing process that may lead to the failure of die, delamination and package cracking. Identifying potential root causes of quality and reliability problems during the development of an assembly process and during package design is very important; it can reduce scrap during manufacturing, save development time, as well as help insure the product meets the requirements of customers. Simulation can find the root cause quickly and accurately, leading to reduced time and cost. It enables experiments that are too costly to be done by empirical methods. Using simulation we can find the conditions that optimize cost, performance and reliability under different sets of conditions. This paper focuses on modeling and simulation for typical package assembly manufacture processes which have large impact to the product quality and reliability. A finite element framework is developed to simulate the assembly package manufacturing process utilizing the ANSYS software platform. The framework tools are utilized to maximize the robustness of the assembly process in order to eliminate reliability issues, fast run time and minimize costs in development and from manufacturing scrap.
{"title":"Simulation and analysis for typical package assembly manufacture","authors":"Y. Liu, S. Irving, D. Desbiens, T. Luk","doi":"10.1109/ESIME.2006.1643949","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643949","url":null,"abstract":"The manufacturing process for package assembly is a key to assuring the reliability and quality of the semiconductor products. There are a significant number of challenging mechanics problems in assembly manufacturing process that may lead to the failure of die, delamination and package cracking. Identifying potential root causes of quality and reliability problems during the development of an assembly process and during package design is very important; it can reduce scrap during manufacturing, save development time, as well as help insure the product meets the requirements of customers. Simulation can find the root cause quickly and accurately, leading to reduced time and cost. It enables experiments that are too costly to be done by empirical methods. Using simulation we can find the conditions that optimize cost, performance and reliability under different sets of conditions. This paper focuses on modeling and simulation for typical package assembly manufacture processes which have large impact to the product quality and reliability. A finite element framework is developed to simulate the assembly package manufacturing process utilizing the ANSYS software platform. The framework tools are utilized to maximize the robustness of the assembly process in order to eliminate reliability issues, fast run time and minimize costs in development and from manufacturing scrap.","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78765746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643969
C. Yuan, G.Q. Zhang, Ching-Shun Huang, Chun-Hui Yu, Chin-Cheng Yang, Wen-Kung Yang, M. Yew, Cheng-Nan Han, K. Chiang
A novel solder on rubber (SOR) structure of the advanced wafer level chip scaled packaging (WLCSP), having the capability of releasing the deformation energy which is caused by the CTE mismatch between the silicon chip and the substrate, is proposed herein. In the SOR structure, a metallic trace and solder pad would be formed on the rubber-based polymer, and a solder is attached onto the said pad. Moreover, a delamination layer is designed and fabricated between the metallic trace and the stress buffer layer (SBL), and the metal trace is also designed as curved shape to prevent the over-stretching of the trace. By the failure of the designed delamination layer, the SOR structure could theoretically release more energy than the conventional WLCSP structure. In this paper, the design concept of the SOR structure, experimental measurement of the adhesion strength of the delamination layer and the finite element (FE) analysis of the SOR structure are discussed
{"title":"Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP","authors":"C. Yuan, G.Q. Zhang, Ching-Shun Huang, Chun-Hui Yu, Chin-Cheng Yang, Wen-Kung Yang, M. Yew, Cheng-Nan Han, K. Chiang","doi":"10.1109/ESIME.2006.1643969","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643969","url":null,"abstract":"A novel solder on rubber (SOR) structure of the advanced wafer level chip scaled packaging (WLCSP), having the capability of releasing the deformation energy which is caused by the CTE mismatch between the silicon chip and the substrate, is proposed herein. In the SOR structure, a metallic trace and solder pad would be formed on the rubber-based polymer, and a solder is attached onto the said pad. Moreover, a delamination layer is designed and fabricated between the metallic trace and the stress buffer layer (SBL), and the metal trace is also designed as curved shape to prevent the over-stretching of the trace. By the failure of the designed delamination layer, the SOR structure could theoretically release more energy than the conventional WLCSP structure. In this paper, the design concept of the SOR structure, experimental measurement of the adhesion strength of the delamination layer and the finite element (FE) analysis of the SOR structure are discussed","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84989402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644002
C. Noritake, P. Limaye, M. Gonzalez, B. Vandevelde
This study is aimed at analysing the reliability of a three-dimensional (3D) chip stacked package under cyclic thermal loading. The critical areas in the 3D chip stacked package are defined with finite element modeling (FEM) based simulations to correlate the thermal cycling experiments. The 3D chip stacked package consists of two 300mum thick Si chips vertically connected with Sn-Ag-Cu solder bump joints and then assembled on a conventional FR-4 printed circuit aboard (PCB). Two thermal cycle conditions are studied, namely: -40 to 125degC and 0 to 100degC. FEM simulations indicate that in both conditions, the critical failure location is expected to be in the chip side region of the corner solder bump of the lower chip connecting the package to the PCB. Creep strain per single thermal cycle averaged over a critical damage volume; Deltaepsivcr is used as the damage parameter. Furthermore, we have investigated the possible approaches to improve the thermo-mechanical reliability for this package. The results indicate that adding an underfill or thinning Si chips will achieve lower creep strain in solder bumps. Furthermore, the stress levels in Si and Cu via in the Si chip are low. Therefore fracture of Si chips and fatigue of Cu vias is not expected under thermal cycling conditions
{"title":"Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis","authors":"C. Noritake, P. Limaye, M. Gonzalez, B. Vandevelde","doi":"10.1109/ESIME.2006.1644002","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644002","url":null,"abstract":"This study is aimed at analysing the reliability of a three-dimensional (3D) chip stacked package under cyclic thermal loading. The critical areas in the 3D chip stacked package are defined with finite element modeling (FEM) based simulations to correlate the thermal cycling experiments. The 3D chip stacked package consists of two 300mum thick Si chips vertically connected with Sn-Ag-Cu solder bump joints and then assembled on a conventional FR-4 printed circuit aboard (PCB). Two thermal cycle conditions are studied, namely: -40 to 125degC and 0 to 100degC. FEM simulations indicate that in both conditions, the critical failure location is expected to be in the chip side region of the corner solder bump of the lower chip connecting the package to the PCB. Creep strain per single thermal cycle averaged over a critical damage volume; Deltaepsivcr is used as the damage parameter. Furthermore, we have investigated the possible approaches to improve the thermo-mechanical reliability for this package. The results indicate that adding an underfill or thinning Si chips will achieve lower creep strain in solder bumps. Furthermore, the stress levels in Si and Cu via in the Si chip are low. Therefore fracture of Si chips and fatigue of Cu vias is not expected under thermal cycling conditions","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91264713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644012
R. Dudek, H. Walter, R. Doering, B. Michel, T. Meyer, J. Zapf, H. Hedler
Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased reliability on module level with advantages in processing and the capability of full wafer level test and burn-in is ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology), particularly developed for memory products. The new failure risks are mainly related to fatigue of the metallic redistribution layer (RDL). Parametric studies using finite element analyses (FEA) were performed to avoid excessive straining of the metal lines. A balance of metal straining and solder straining had to be achieved. Comparisons were made for different soft bump layouts and RDL patterns. Optimal solutions figured out by FEA were also investigated experimentally by thermal cycle tests. However, the thermo-mechanical characteristics like stress-strain behaviour and fatigue resistance of the metallic films are the most important parameters for reliability predictions. In particular, the elastic-plastic properties of thin metallic Cu and Ni films are shown to depend on features like film thickness, grain size and orientation, resulting in a thin film strength exceeding the bulk strength of the same metal by several hundred percent
晶圆级封装(WLP)技术是一种成本效益高的封装解决方案，应用越来越广泛。二级可靠性，即热循环过程中的热机械可靠性，是WLP的主要关注点。为了避免焊料过度拉伸，焊料球被弹性互连所取代，它可以采用热失配变形的主要部分。ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology)是一种结合了模块级可靠性提高、处理优势和全晶圆级测试和老化能力的解决方案，特别为存储产品开发。新的失效风险主要与金属重分布层(RDL)的疲劳有关。采用有限元分析(FEA)进行参数化研究，以避免金属线过度拉伸。必须达到金属张力和焊料张力的平衡。比较了不同的软凹凸布局和RDL模式。并通过热循环试验对有限元分析得到的最优解进行了验证。然而，热机械特性，如金属薄膜的应力应变行为和抗疲劳性能是可靠性预测的最重要参数。特别是，薄金属Cu和Ni薄膜的弹塑性性能取决于薄膜厚度、晶粒尺寸和取向等特征，从而导致薄膜强度超过相同金属的体积强度数百倍
{"title":"Thermo-mechanical Design of Resilient Contact Systems for Wafer Level Packaging","authors":"R. Dudek, H. Walter, R. Doering, B. Michel, T. Meyer, J. Zapf, H. Hedler","doi":"10.1109/ESIME.2006.1644012","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644012","url":null,"abstract":"Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased reliability on module level with advantages in processing and the capability of full wafer level test and burn-in is ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology), particularly developed for memory products. The new failure risks are mainly related to fatigue of the metallic redistribution layer (RDL). Parametric studies using finite element analyses (FEA) were performed to avoid excessive straining of the metal lines. A balance of metal straining and solder straining had to be achieved. Comparisons were made for different soft bump layouts and RDL patterns. Optimal solutions figured out by FEA were also investigated experimentally by thermal cycle tests. However, the thermo-mechanical characteristics like stress-strain behaviour and fatigue resistance of the metallic films are the most important parameters for reliability predictions. In particular, the elastic-plastic properties of thin metallic Cu and Ni films are shown to depend on features like film thickness, grain size and orientation, resulting in a thin film strength exceeding the bulk strength of the same metal by several hundred percent","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81391810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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