Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643962
R. van Silfhout, O. van der Sluis, W. V. van Driel, J. Janssen, G.Q. Zhang
For Integrated Circuit (IC) wafer backend development, process developers have to design robust backend structures that guarantee both functionality and reliability during waferfab processes, packaging, qualification tests and lifetime. Figure 1 shows a simplified diagram for the design (and redesign) cycle forevelopment. Subsequently, package development IC development. Subsequently, package develop t . inherited runs a similar cycle. By using reliability modell relate it to the interaction of IC and package assembly, such as IC/compound delamination, we aim at integrating IC and packge prototyping in order to develop reliable IC packages faster. This paper presents parts of our research to approach thermo-mechanical IC reliability by virtually designing and quaifying IC backend structures in both IC processing, packaging and testing processes. By combining experimental and numerical results, targeted failure modes and mechanisms as well as their interactions are understood. It is found that delamination is the key trigger for passivation cracking and metal shift. Even more, the layout of interconnect metals in the backend of ICs has a major effect on under bond-pad wir delamination observed after wafer probing an wire ing. Reliable predictive modelling approaches enable IC package development towards a first-time-right practice.
{"title":"Virtual Design and Qualification of IC Backend Structures","authors":"R. van Silfhout, O. van der Sluis, W. V. van Driel, J. Janssen, G.Q. Zhang","doi":"10.1109/ESIME.2006.1643962","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643962","url":null,"abstract":"For Integrated Circuit (IC) wafer backend development, process developers have to design robust backend structures that guarantee both functionality and reliability during waferfab processes, packaging, qualification tests and lifetime. Figure 1 shows a simplified diagram for the design (and redesign) cycle forevelopment. Subsequently, package development IC development. Subsequently, package develop t . inherited runs a similar cycle. By using reliability modell relate it to the interaction of IC and package assembly, such as IC/compound delamination, we aim at integrating IC and packge prototyping in order to develop reliable IC packages faster. This paper presents parts of our research to approach thermo-mechanical IC reliability by virtually designing and quaifying IC backend structures in both IC processing, packaging and testing processes. By combining experimental and numerical results, targeted failure modes and mechanisms as well as their interactions are understood. It is found that delamination is the key trigger for passivation cracking and metal shift. Even more, the layout of interconnect metals in the backend of ICs has a major effect on under bond-pad wir delamination observed after wafer probing an wire ing. Reliable predictive modelling approaches enable IC package development towards a first-time-right practice.","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"47 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78370379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644037
Guangping Zhang, C. Volkert, R. Schwaiger, R. Mönig, Oliver Kraft
In this paper, we summarize several testing methods that are currently available for the characterization of fatigue properties of thin metal films. Using these testing methods, a number of experimental investigations of the fatigue and thermal fatigue of metal films with thicknesses ranging from micrometers to sub-micrometers are described. Extensive experimental observations as well as theoretical analyses reveal that the damage behavior, i.e. typical fatigue extrusions and cracking, are quite different from that of bulk materials, and are controlled by the length scales of the materials. Due to the high surface to volume ratio of thin films interface-induced and diffusion-related damage are prevalent in these small length scale materials. As a result, interfaces pose a serious threat to the reliability of thin films
{"title":"Fatigue and Thermal Fatigue Damage Analysis of Thin Metal Films","authors":"Guangping Zhang, C. Volkert, R. Schwaiger, R. Mönig, Oliver Kraft","doi":"10.1109/ESIME.2006.1644037","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644037","url":null,"abstract":"In this paper, we summarize several testing methods that are currently available for the characterization of fatigue properties of thin metal films. Using these testing methods, a number of experimental investigations of the fatigue and thermal fatigue of metal films with thicknesses ranging from micrometers to sub-micrometers are described. Extensive experimental observations as well as theoretical analyses reveal that the damage behavior, i.e. typical fatigue extrusions and cracking, are quite different from that of bulk materials, and are controlled by the length scales of the materials. Due to the high surface to volume ratio of thin films interface-induced and diffusion-related damage are prevalent in these small length scale materials. As a result, interfaces pose a serious threat to the reliability of thin films","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"22 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90586863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643984
A. Corigliano, F. Cacchione, A. Frangi, S. Zerbini
The problem of impact rupture in polysilicon MEMS is addressed in this paper employing a numerical 2D geometrical model of the polycrystal obtained by means of a Voronoi tessellation coupled with a FE mesh. The intergranular and transgranular rupture is simulated by means of cohesive traction-jumps softening laws; accidental drop is simulated through a simplified three-level multi scale approach
{"title":"Simulation of Impact Rupture in Polysilicon Mems","authors":"A. Corigliano, F. Cacchione, A. Frangi, S. Zerbini","doi":"10.1109/ESIME.2006.1643984","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643984","url":null,"abstract":"The problem of impact rupture in polysilicon MEMS is addressed in this paper employing a numerical 2D geometrical model of the polycrystal obtained by means of a Voronoi tessellation coupled with a FE mesh. The intergranular and transgranular rupture is simulated by means of cohesive traction-jumps softening laws; accidental drop is simulated through a simplified three-level multi scale approach","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"26 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83238299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644003
J. Anttonen, T. Kangasvieri, O. Nousiainen, J. Putaala, J. Vahakangas
In this paper, a reliability modeling methodology for BGA solder joints with plastic-core solder balls (PCSBs) has been presented. The methodology is applied to predict the board-level reliability of LTCC/BGA modules under accelerated thermal cycling conditions. The model takes into account both time- and temperature-dependent as well as time-independent plasticity and provides a detailed number of cycles needed to crack initiation, propagation and eventual solder joint failure. To assess the feasibility of the presented modeling procedure, the model is validated against experimental temperature cycling data obtained from LTCC/BGA module assemblies on a printed wiring board. The results demonstrate that this procedure can be used for life-time prediction of BGA solder joints with PCSBs
{"title":"Thermo-Mechanical Modeling of Plastic-Core Solder Balls in LTCC/BGA Assemblies","authors":"J. Anttonen, T. Kangasvieri, O. Nousiainen, J. Putaala, J. Vahakangas","doi":"10.1109/ESIME.2006.1644003","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644003","url":null,"abstract":"In this paper, a reliability modeling methodology for BGA solder joints with plastic-core solder balls (PCSBs) has been presented. The methodology is applied to predict the board-level reliability of LTCC/BGA modules under accelerated thermal cycling conditions. The model takes into account both time- and temperature-dependent as well as time-independent plasticity and provides a detailed number of cycles needed to crack initiation, propagation and eventual solder joint failure. To assess the feasibility of the presented modeling procedure, the model is validated against experimental temperature cycling data obtained from LTCC/BGA module assemblies on a printed wiring board. The results demonstrate that this procedure can be used for life-time prediction of BGA solder joints with PCSBs","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88398483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644024
J. Brufau-Penella, M. Puig-Vidal
In this paper the constituent equations that describe the behavior of a multi-layer piezoelectric cantilever on the coupled electronic and mechanical domain are presented. The study is based on the modal analysis of the partial differential equations governing the motion of an Euler-Bernoulli cantilever beam and on a pair of linearly coupled piezoelectric equations. An important element in the modelization of such materials is the energy loss term; in this paper a viscous damping contribution is considered which allows us to extract more realistic constituent equations for the material to work as sensor and actuator. The development of this equation as an infinite linear combination of each mode allows us to extract a compact lumped equivalent electrical circuit to work at any frequency region as sensor or actuator instead of the classical reduced models. Theory is reduced to study the dynamics of a triple-layer commercial cantilever and then is compared with experimental results
{"title":"Electromechanical Model of a Multi-Layer Piezoelectric Cantilever","authors":"J. Brufau-Penella, M. Puig-Vidal","doi":"10.1109/ESIME.2006.1644024","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644024","url":null,"abstract":"In this paper the constituent equations that describe the behavior of a multi-layer piezoelectric cantilever on the coupled electronic and mechanical domain are presented. The study is based on the modal analysis of the partial differential equations governing the motion of an Euler-Bernoulli cantilever beam and on a pair of linearly coupled piezoelectric equations. An important element in the modelization of such materials is the energy loss term; in this paper a viscous damping contribution is considered which allows us to extract more realistic constituent equations for the material to work as sensor and actuator. The development of this equation as an infinite linear combination of each mode allows us to extract a compact lumped equivalent electrical circuit to work at any frequency region as sensor or actuator instead of the classical reduced models. Theory is reduced to study the dynamics of a triple-layer commercial cantilever and then is compared with experimental results","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"39 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88425197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644050
Jiang Zhou, K. Sharan, S. Lahoti
Dynamic performance during drop impact is a great concern to semiconductor and electronic product manufacturers, especially for portable devices such as mobile phones. In this paper, the drop impact response of a mobile phone is investigated by an analytical dynamics model. In order to capture some most important affected factors, we decouple this problem to be a two-step analysis. First, finite element analysis is used to determine the effective stiffness for housing and PCB board, respectively. Second, a two-degree-of-freedom analytical dynamic model is developed to investigate the drop impact response. Such an approach allows parametric analysis to determine the important design parameters, which are important to the preliminary selection of geometries and materials of PCB boards and stiffness of housings so that the dynamic stability is maintained. Board level finite element analysis is also performed using input-acceleration model. The results are in good agreement with the analytical model results developed above. Finally, both methods are applied to evaluate the dynamic response of a commercially used cellular phone
{"title":"Analytical and Numerical Analysis of Drop Impact Behavior for a Portable Electronic Device","authors":"Jiang Zhou, K. Sharan, S. Lahoti","doi":"10.1109/ESIME.2006.1644050","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644050","url":null,"abstract":"Dynamic performance during drop impact is a great concern to semiconductor and electronic product manufacturers, especially for portable devices such as mobile phones. In this paper, the drop impact response of a mobile phone is investigated by an analytical dynamics model. In order to capture some most important affected factors, we decouple this problem to be a two-step analysis. First, finite element analysis is used to determine the effective stiffness for housing and PCB board, respectively. Second, a two-degree-of-freedom analytical dynamic model is developed to investigate the drop impact response. Such an approach allows parametric analysis to determine the important design parameters, which are important to the preliminary selection of geometries and materials of PCB boards and stiffness of housings so that the dynamic stability is maintained. Board level finite element analysis is also performed using input-acceleration model. The results are in good agreement with the analytical model results developed above. Finally, both methods are applied to evaluate the dynamic response of a commercially used cellular phone","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"60 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89700527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643949
Y. Liu, S. Irving, D. Desbiens, T. Luk
The manufacturing process for package assembly is a key to assuring the reliability and quality of the semiconductor products. There are a significant number of challenging mechanics problems in assembly manufacturing process that may lead to the failure of die, delamination and package cracking. Identifying potential root causes of quality and reliability problems during the development of an assembly process and during package design is very important; it can reduce scrap during manufacturing, save development time, as well as help insure the product meets the requirements of customers. Simulation can find the root cause quickly and accurately, leading to reduced time and cost. It enables experiments that are too costly to be done by empirical methods. Using simulation we can find the conditions that optimize cost, performance and reliability under different sets of conditions. This paper focuses on modeling and simulation for typical package assembly manufacture processes which have large impact to the product quality and reliability. A finite element framework is developed to simulate the assembly package manufacturing process utilizing the ANSYS software platform. The framework tools are utilized to maximize the robustness of the assembly process in order to eliminate reliability issues, fast run time and minimize costs in development and from manufacturing scrap.
{"title":"Simulation and analysis for typical package assembly manufacture","authors":"Y. Liu, S. Irving, D. Desbiens, T. Luk","doi":"10.1109/ESIME.2006.1643949","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643949","url":null,"abstract":"The manufacturing process for package assembly is a key to assuring the reliability and quality of the semiconductor products. There are a significant number of challenging mechanics problems in assembly manufacturing process that may lead to the failure of die, delamination and package cracking. Identifying potential root causes of quality and reliability problems during the development of an assembly process and during package design is very important; it can reduce scrap during manufacturing, save development time, as well as help insure the product meets the requirements of customers. Simulation can find the root cause quickly and accurately, leading to reduced time and cost. It enables experiments that are too costly to be done by empirical methods. Using simulation we can find the conditions that optimize cost, performance and reliability under different sets of conditions. This paper focuses on modeling and simulation for typical package assembly manufacture processes which have large impact to the product quality and reliability. A finite element framework is developed to simulate the assembly package manufacturing process utilizing the ANSYS software platform. The framework tools are utilized to maximize the robustness of the assembly process in order to eliminate reliability issues, fast run time and minimize costs in development and from manufacturing scrap.","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"33 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78765746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643969
C. Yuan, G.Q. Zhang, Ching-Shun Huang, Chun-Hui Yu, Chin-Cheng Yang, Wen-Kung Yang, M. Yew, Cheng-Nan Han, K. Chiang
A novel solder on rubber (SOR) structure of the advanced wafer level chip scaled packaging (WLCSP), having the capability of releasing the deformation energy which is caused by the CTE mismatch between the silicon chip and the substrate, is proposed herein. In the SOR structure, a metallic trace and solder pad would be formed on the rubber-based polymer, and a solder is attached onto the said pad. Moreover, a delamination layer is designed and fabricated between the metallic trace and the stress buffer layer (SBL), and the metal trace is also designed as curved shape to prevent the over-stretching of the trace. By the failure of the designed delamination layer, the SOR structure could theoretically release more energy than the conventional WLCSP structure. In this paper, the design concept of the SOR structure, experimental measurement of the adhesion strength of the delamination layer and the finite element (FE) analysis of the SOR structure are discussed
{"title":"Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP","authors":"C. Yuan, G.Q. Zhang, Ching-Shun Huang, Chun-Hui Yu, Chin-Cheng Yang, Wen-Kung Yang, M. Yew, Cheng-Nan Han, K. Chiang","doi":"10.1109/ESIME.2006.1643969","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643969","url":null,"abstract":"A novel solder on rubber (SOR) structure of the advanced wafer level chip scaled packaging (WLCSP), having the capability of releasing the deformation energy which is caused by the CTE mismatch between the silicon chip and the substrate, is proposed herein. In the SOR structure, a metallic trace and solder pad would be formed on the rubber-based polymer, and a solder is attached onto the said pad. Moreover, a delamination layer is designed and fabricated between the metallic trace and the stress buffer layer (SBL), and the metal trace is also designed as curved shape to prevent the over-stretching of the trace. By the failure of the designed delamination layer, the SOR structure could theoretically release more energy than the conventional WLCSP structure. In this paper, the design concept of the SOR structure, experimental measurement of the adhesion strength of the delamination layer and the finite element (FE) analysis of the SOR structure are discussed","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"42 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84989402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644002
C. Noritake, P. Limaye, M. Gonzalez, B. Vandevelde
This study is aimed at analysing the reliability of a three-dimensional (3D) chip stacked package under cyclic thermal loading. The critical areas in the 3D chip stacked package are defined with finite element modeling (FEM) based simulations to correlate the thermal cycling experiments. The 3D chip stacked package consists of two 300mum thick Si chips vertically connected with Sn-Ag-Cu solder bump joints and then assembled on a conventional FR-4 printed circuit aboard (PCB). Two thermal cycle conditions are studied, namely: -40 to 125degC and 0 to 100degC. FEM simulations indicate that in both conditions, the critical failure location is expected to be in the chip side region of the corner solder bump of the lower chip connecting the package to the PCB. Creep strain per single thermal cycle averaged over a critical damage volume; Deltaepsivcr is used as the damage parameter. Furthermore, we have investigated the possible approaches to improve the thermo-mechanical reliability for this package. The results indicate that adding an underfill or thinning Si chips will achieve lower creep strain in solder bumps. Furthermore, the stress levels in Si and Cu via in the Si chip are low. Therefore fracture of Si chips and fatigue of Cu vias is not expected under thermal cycling conditions
{"title":"Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis","authors":"C. Noritake, P. Limaye, M. Gonzalez, B. Vandevelde","doi":"10.1109/ESIME.2006.1644002","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644002","url":null,"abstract":"This study is aimed at analysing the reliability of a three-dimensional (3D) chip stacked package under cyclic thermal loading. The critical areas in the 3D chip stacked package are defined with finite element modeling (FEM) based simulations to correlate the thermal cycling experiments. The 3D chip stacked package consists of two 300mum thick Si chips vertically connected with Sn-Ag-Cu solder bump joints and then assembled on a conventional FR-4 printed circuit aboard (PCB). Two thermal cycle conditions are studied, namely: -40 to 125degC and 0 to 100degC. FEM simulations indicate that in both conditions, the critical failure location is expected to be in the chip side region of the corner solder bump of the lower chip connecting the package to the PCB. Creep strain per single thermal cycle averaged over a critical damage volume; Deltaepsivcr is used as the damage parameter. Furthermore, we have investigated the possible approaches to improve the thermo-mechanical reliability for this package. The results indicate that adding an underfill or thinning Si chips will achieve lower creep strain in solder bumps. Furthermore, the stress levels in Si and Cu via in the Si chip are low. Therefore fracture of Si chips and fatigue of Cu vias is not expected under thermal cycling conditions","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"230 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91264713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644012
R. Dudek, H. Walter, R. Doering, B. Michel, T. Meyer, J. Zapf, H. Hedler
Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased reliability on module level with advantages in processing and the capability of full wafer level test and burn-in is ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology), particularly developed for memory products. The new failure risks are mainly related to fatigue of the metallic redistribution layer (RDL). Parametric studies using finite element analyses (FEA) were performed to avoid excessive straining of the metal lines. A balance of metal straining and solder straining had to be achieved. Comparisons were made for different soft bump layouts and RDL patterns. Optimal solutions figured out by FEA were also investigated experimentally by thermal cycle tests. However, the thermo-mechanical characteristics like stress-strain behaviour and fatigue resistance of the metallic films are the most important parameters for reliability predictions. In particular, the elastic-plastic properties of thin metallic Cu and Ni films are shown to depend on features like film thickness, grain size and orientation, resulting in a thin film strength exceeding the bulk strength of the same metal by several hundred percent
晶圆级封装(WLP)技术是一种成本效益高的封装解决方案，应用越来越广泛。二级可靠性，即热循环过程中的热机械可靠性，是WLP的主要关注点。为了避免焊料过度拉伸，焊料球被弹性互连所取代，它可以采用热失配变形的主要部分。ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology)是一种结合了模块级可靠性提高、处理优势和全晶圆级测试和老化能力的解决方案，特别为存储产品开发。新的失效风险主要与金属重分布层(RDL)的疲劳有关。采用有限元分析(FEA)进行参数化研究，以避免金属线过度拉伸。必须达到金属张力和焊料张力的平衡。比较了不同的软凹凸布局和RDL模式。并通过热循环试验对有限元分析得到的最优解进行了验证。然而，热机械特性，如金属薄膜的应力应变行为和抗疲劳性能是可靠性预测的最重要参数。特别是，薄金属Cu和Ni薄膜的弹塑性性能取决于薄膜厚度、晶粒尺寸和取向等特征，从而导致薄膜强度超过相同金属的体积强度数百倍
{"title":"Thermo-mechanical Design of Resilient Contact Systems for Wafer Level Packaging","authors":"R. Dudek, H. Walter, R. Doering, B. Michel, T. Meyer, J. Zapf, H. Hedler","doi":"10.1109/ESIME.2006.1644012","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644012","url":null,"abstract":"Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased reliability on module level with advantages in processing and the capability of full wafer level test and burn-in is ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology), particularly developed for memory products. The new failure risks are mainly related to fatigue of the metallic redistribution layer (RDL). Parametric studies using finite element analyses (FEA) were performed to avoid excessive straining of the metal lines. A balance of metal straining and solder straining had to be achieved. Comparisons were made for different soft bump layouts and RDL patterns. Optimal solutions figured out by FEA were also investigated experimentally by thermal cycle tests. However, the thermo-mechanical characteristics like stress-strain behaviour and fatigue resistance of the metallic films are the most important parameters for reliability predictions. In particular, the elastic-plastic properties of thin metallic Cu and Ni films are shown to depend on features like film thickness, grain size and orientation, resulting in a thin film strength exceeding the bulk strength of the same metal by several hundred percent","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"107 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81391810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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