Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852868
S. Sidiropoulos, Dean Liu, Jaeha Kim, Gu-Yeon Wei, Mark Horowitz
A technique for designing DLLs and PLLs using CMOS buffers with a regulated supply is presented. By scaling the charge pump current and the output resistance of the regulating amplifier, the proposed loops achieve a wide bandwidth that tracks the operating frequency, a constant damping factor, large operating range and low noise sensitivity. Prototype loops designed in 0.35-/spl mu/m CMOS processes exhibit >10x operating range and less than 1% input tracking jitter.
{"title":"Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers","authors":"S. Sidiropoulos, Dean Liu, Jaeha Kim, Gu-Yeon Wei, Mark Horowitz","doi":"10.1109/VLSIC.2000.852868","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852868","url":null,"abstract":"A technique for designing DLLs and PLLs using CMOS buffers with a regulated supply is presented. By scaling the charge pump current and the output resistance of the regulating amplifier, the proposed loops achieve a wide bandwidth that tracks the operating frequency, a constant damping factor, large operating range and low noise sensitivity. Prototype loops designed in 0.35-/spl mu/m CMOS processes exhibit >10x operating range and less than 1% input tracking jitter.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"78 1","pages":"124-127"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75839875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852903
T. Kuo, B. Lusignan
A channel-select filter with on-chip PLL tuning for CDMA IS-95 has been integrated in a 0.35-/spl mu/m digital CMOS technology. To achieve both low power and robustness, dynamic range scaling is implemented on an elliptic ladder prototype. The dynamic range scaling is based on the special requirement for the wireless receiver. A new method to analyze the trade-off between filter noise and power consumption is presented. The filter and PLL dissipate 2.9 mW and 1.6 mW from a 3-V supply, and the die area is 1.06 mm/sup 2/. The filter achieves 61 dB stopband rejection, 0.05 dB/0.2/spl deg/ I/Q gain/phase mismatch, 100 /spl mu/Vrms input-referred noise, 20 dBm IIP3, and 58 dB SFDR.
{"title":"A very low power channel select filter for IS-95 CDMA receiver with on-chip tuning","authors":"T. Kuo, B. Lusignan","doi":"10.1109/VLSIC.2000.852903","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852903","url":null,"abstract":"A channel-select filter with on-chip PLL tuning for CDMA IS-95 has been integrated in a 0.35-/spl mu/m digital CMOS technology. To achieve both low power and robustness, dynamic range scaling is implemented on an elliptic ladder prototype. The dynamic range scaling is based on the special requirement for the wireless receiver. A new method to analyze the trade-off between filter noise and power consumption is presented. The filter and PLL dissipate 2.9 mW and 1.6 mW from a 3-V supply, and the die area is 1.06 mm/sup 2/. The filter achieves 61 dB stopband rejection, 0.05 dB/0.2/spl deg/ I/Q gain/phase mismatch, 100 /spl mu/Vrms input-referred noise, 20 dBm IIP3, and 58 dB SFDR.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"2 1","pages":"244-247"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75956421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852854
K. Agawa, H. Hara, T. Takayanagi, T. Kuroda
The bit-line leakage current of an SRAM, induced by transistor leakage at low V/sub DD/ and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V/sub th/ can be lowered to 0.23 V/sub DD/ in a 0.07 /spl mu/m/1.0 V CMOS, as it was before, keeping V/sub th/ and delay scalability of the high-speed SRAM.
{"title":"A bit-line leakage compensation scheme for low-voltage SRAM's","authors":"K. Agawa, H. Hara, T. Takayanagi, T. Kuroda","doi":"10.1109/VLSIC.2000.852854","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852854","url":null,"abstract":"The bit-line leakage current of an SRAM, induced by transistor leakage at low V/sub DD/ and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V/sub th/ can be lowered to 0.23 V/sub DD/ in a 0.07 /spl mu/m/1.0 V CMOS, as it was before, keeping V/sub th/ and delay scalability of the high-speed SRAM.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"29 1","pages":"70-71"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77919000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852880
H. Kurata, N. Kobayashi, S. Saeki, T. Kawahara
The demand for high density and high-speed programming in flash memories has grown because of audio- and video- storage applications. A multilevel technique is the most effective approach to improving memory density, but it requires precise control of a memory cell's Vth that doesn't degrade programming performance. To enable this, we have developed a selective verify scheme for high-speed programming based on simultaneous multilevel programming. A selective verify scheme with asymmetrical cell operation and two-bank operation makes 5-MB/s programming throughput in 3-bit/cell flash memories attainable.
{"title":"A selective verify scheme for achieving a 5-MB/s program rate in 3-bit/cell flash memories","authors":"H. Kurata, N. Kobayashi, S. Saeki, T. Kawahara","doi":"10.1109/VLSIC.2000.852880","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852880","url":null,"abstract":"The demand for high density and high-speed programming in flash memories has grown because of audio- and video- storage applications. A multilevel technique is the most effective approach to improving memory density, but it requires precise control of a memory cell's Vth that doesn't degrade programming performance. To enable this, we have developed a selective verify scheme for high-speed programming based on simultaneous multilevel programming. A selective verify scheme with asymmetrical cell operation and two-bank operation makes 5-MB/s programming throughput in 3-bit/cell flash memories attainable.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"117 1","pages":"166-167"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79389103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852899
J.L. Miller, J. Conary, D. DiMarco
A modular 256 KB advanced transfer cache tile has been developed to implement the on-die second level caches of the 0.18 /spl mu/m Intel(R) Pentium(R) III processor family. The cache tile is stepped from 1 to 8 times to form implementations from 256 KB to 2 MB. Each tile is a self-contained cache delivering a line of 32 B every 2 clock cycles at 1.0 GHz. A charge-share data sense technique overlaps the data and tag array accesses for reduced latency at lower power. Modular tiled cache design also achieves low power through hierarchical power management and reduced test time through PBIST (programmable built in self test).
{"title":"A 16 GB/s, 0.18 /spl mu/m cache tile for integrated L2 caches from 256 KB to 2 MB","authors":"J.L. Miller, J. Conary, D. DiMarco","doi":"10.1109/VLSIC.2000.852899","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852899","url":null,"abstract":"A modular 256 KB advanced transfer cache tile has been developed to implement the on-die second level caches of the 0.18 /spl mu/m Intel(R) Pentium(R) III processor family. The cache tile is stepped from 1 to 8 times to form implementations from 256 KB to 2 MB. Each tile is a self-contained cache delivering a line of 32 B every 2 clock cycles at 1.0 GHz. A charge-share data sense technique overlaps the data and tag array accesses for reduced latency at lower power. Modular tiled cache design also achieves low power through hierarchical power management and reduced test time through PBIST (programmable built in self test).","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"321 1","pages":"228-231"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76897827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852894
M. Figueroa, Chris Diorio
We have built a 16-tap, 7-bit, 200 MHz, mixed-signal FIR filter that consumes 3 mW at 3.3 V. The filter uses p-channel synapse transistors to store the tap coefficients; electron tunneling and hot-electron injection to modify the tap weights; digital registers for the delay line; and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap weights. The measured bandwidth is 225 MHz; the measured tap multiplier resolution is 7 bits at 200 MHz. The total die area is 0.13 mm/sup 2/; we can readily scale the design to higher bit resolutions and longer delay-lines.
{"title":"A 200 MHz, 3 mW, 16-tap mixed-signal FIR filter","authors":"M. Figueroa, Chris Diorio","doi":"10.1109/VLSIC.2000.852894","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852894","url":null,"abstract":"We have built a 16-tap, 7-bit, 200 MHz, mixed-signal FIR filter that consumes 3 mW at 3.3 V. The filter uses p-channel synapse transistors to store the tap coefficients; electron tunneling and hot-electron injection to modify the tap weights; digital registers for the delay line; and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap weights. The measured bandwidth is 225 MHz; the measured tap multiplier resolution is 7 bits at 200 MHz. The total die area is 0.13 mm/sup 2/; we can readily scale the design to higher bit resolutions and longer delay-lines.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"30 1","pages":"214-215"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72917740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852857
T. Hamamoto, S. Kawasaki, K. Furutani, K. Yasuda, Y. Konishi
This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.
{"title":"A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs","authors":"T. Hamamoto, S. Kawasaki, K. Furutani, K. Yasuda, Y. Konishi","doi":"10.1109/VLSIC.2000.852857","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852857","url":null,"abstract":"This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"75 1","pages":"76-81"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73112748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852892
C. Michalski
This analog-to-digital converter achieves a minimum sampling rate of 105 Msample/S at a total power dissipation of 850 mW while achieving 11.0 effective number of bits (SNR=68 dB) and an SFDR of >80 dB for sampling analog input frequencies up to 70 MHz. The converter uses a switched capacitor multi-bit per stage architecture and incorporates an on-chip differential input buffer, a dedicated track/hold amplifier and an internally compensated wideband differential reference amplifier. The converter is fabricated on a 0.6 /spl mu/m BiCMOS process.
{"title":"A 12 b 105 Msample/s, 850 mW analog to digital converter","authors":"C. Michalski","doi":"10.1109/VLSIC.2000.852892","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852892","url":null,"abstract":"This analog-to-digital converter achieves a minimum sampling rate of 105 Msample/S at a total power dissipation of 850 mW while achieving 11.0 effective number of bits (SNR=68 dB) and an SFDR of >80 dB for sampling analog input frequencies up to 70 MHz. The converter uses a switched capacitor multi-bit per stage architecture and incorporates an on-chip differential input buffer, a dedicated track/hold amplifier and an internally compensated wideband differential reference amplifier. The converter is fabricated on a 0.6 /spl mu/m BiCMOS process.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"19 1","pages":"208-211"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80483425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852839
Xuesong Jiang, J. Seeger, M. Kraft, B. Boser
A monolithic surface micromachined Z-axis vibratory rate gyroscope with an on-chip A/D converter is fabricated in a monolithic MEMS/circuits technology with 2 /spl mu/m CMOS and 2.25 /spl mu/m-thick mechanical polysilicon. The on-chip position sense circuit uses correlated double sampling to reject 1/f and kT/C noise and resolves 0.02 angstrom displacements. The gyroscope achieves a noise floor of 3/spl deg//sec//spl radic/Hz at atmospheric pressure and operates from a single 5 V supply.
采用2 /spl μ m CMOS和2.25 /spl μ m厚度的机械多晶硅，采用单片MEMS/电路技术制备了带片上A/D转换器的单片表面微加工z轴振动速率陀螺仪。片上位置检测电路采用相关双采样来抑制1/f和kT/C噪声，并解析0.02埃位移。陀螺仪在大气压下实现3/声压度//秒//声压径向/Hz的噪声底限，并从单个5 V电源工作。
{"title":"A monolithic surface micromachined Z-axis gyroscope with digital output","authors":"Xuesong Jiang, J. Seeger, M. Kraft, B. Boser","doi":"10.1109/VLSIC.2000.852839","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852839","url":null,"abstract":"A monolithic surface micromachined Z-axis vibratory rate gyroscope with an on-chip A/D converter is fabricated in a monolithic MEMS/circuits technology with 2 /spl mu/m CMOS and 2.25 /spl mu/m-thick mechanical polysilicon. The on-chip position sense circuit uses correlated double sampling to reject 1/f and kT/C noise and resolves 0.02 angstrom displacements. The gyroscope achieves a noise floor of 3/spl deg//sec//spl radic/Hz at atmospheric pressure and operates from a single 5 V supply.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"33 1","pages":"16-19"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85580476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852890
Y. Kanno, H. Mizuno, K. Tanaka, T. Watanabe
We have developed a pump-hopping level-up converter and a differential-input, level-down converter that, enable level conversion for I/O interfacing in sub-1-V LSIs. The level-up converter transforms signals of 0.64 V to 3.6 V within 5 ns with a 0.14-/spl mu/m CMOS technology. The differential input level down converter enables stable operation even at VDD of 0.5 V. These proposed level converters also provide the immunity against power-supply bouncing, which is essential for low-voltage and high-speed LSIs.
{"title":"Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs","authors":"Y. Kanno, H. Mizuno, K. Tanaka, T. Watanabe","doi":"10.1109/VLSIC.2000.852890","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852890","url":null,"abstract":"We have developed a pump-hopping level-up converter and a differential-input, level-down converter that, enable level conversion for I/O interfacing in sub-1-V LSIs. The level-up converter transforms signals of 0.64 V to 3.6 V within 5 ns with a 0.14-/spl mu/m CMOS technology. The differential input level down converter enables stable operation even at VDD of 0.5 V. These proposed level converters also provide the immunity against power-supply bouncing, which is essential for low-voltage and high-speed LSIs.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"10 1","pages":"202-203"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85905222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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