Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852843
A. Parssinen, J. Jussila, J. Ryynanen, L. Sumanen, K. Kivekas, K. Halonen
In wireless communications, the receiver architectures, which have on-chip channel selection filters like direct conversion or low-IF, are preferred to increase the integration level. Combining digital signal processing on the same chip with analog circuits would be desirable in the miniaturization. Some recent papers present highly integrated tranceivers with mixed-mode or digital circuits on the same chip. However, only little discussion or experimental results have been given on the potential problems related to the system. This paper focuses on the design aspects of the single-chip direct conversion receivers, and gives experimental results of the BiCMOS prototype. The chip includes RF front-end, analog baseband signal processing and 6-bit A/D converters on the same die. It operates in the third generation wideband CDMA wireless system at 2 GHz.
{"title":"A wide-band direct conversion receiver with on-chip A/D converters","authors":"A. Parssinen, J. Jussila, J. Ryynanen, L. Sumanen, K. Kivekas, K. Halonen","doi":"10.1109/VLSIC.2000.852843","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852843","url":null,"abstract":"In wireless communications, the receiver architectures, which have on-chip channel selection filters like direct conversion or low-IF, are preferred to increase the integration level. Combining digital signal processing on the same chip with analog circuits would be desirable in the miniaturization. Some recent papers present highly integrated tranceivers with mixed-mode or digital circuits on the same chip. However, only little discussion or experimental results have been given on the potential problems related to the system. This paper focuses on the design aspects of the single-chip direct conversion receivers, and gives experimental results of the BiCMOS prototype. The chip includes RF front-end, analog baseband signal processing and 6-bit A/D converters on the same die. It operates in the third generation wideband CDMA wireless system at 2 GHz.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"73 1","pages":"32-33"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73368516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852841
L.G. Mellrath
A CMOS image sensor with pixel-parallel A/D conversion fabricated with different array sizes and photodiode types in a 3-metal 0.5 /spl mu/m process is presented. Nominal power dissipation is 40 nW per pixel at V/sub DD/=3.3 V. A/D conversion results from sampling a free-running photocurrent-controlled oscillator to give a first-order /spl Sigma/-/spl Delta/ sequence. The sensor displays dynamic range capability of greater than 150000:1 and exhibits fixed pattern noise correctable to within 0.1% of signal.
{"title":"A low power, low noise, ultra-wide dynamic range CMOS imager with pixel-parallel A/D conversion","authors":"L.G. Mellrath","doi":"10.1109/VLSIC.2000.852841","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852841","url":null,"abstract":"A CMOS image sensor with pixel-parallel A/D conversion fabricated with different array sizes and photodiode types in a 3-metal 0.5 /spl mu/m process is presented. Nominal power dissipation is 40 nW per pixel at V/sub DD/=3.3 V. A/D conversion results from sampling a free-running photocurrent-controlled oscillator to give a first-order /spl Sigma/-/spl Delta/ sequence. The sensor displays dynamic range capability of greater than 150000:1 and exhibits fixed pattern noise correctable to within 0.1% of signal.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"5 1","pages":"24-27"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80351283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852873
P. Balmelli, Qiuting Huang, F. Piazza
A 5/sup th/-order single-loop /spl Sigma/-/spl Delta/ modulator has been implemented in a 0.25 /spl mu/m digital CMOS process, where the supply voltage is only 2.5 V and the capacitor option is not available. A tri-level quantizer is used to improve loop stability. The sampling frequency of the modulator is 80 MHz and the oversampling ratio is 32. Measured over a 1 MHz signal bandwidth, dynamic range is 86 dB, peak SNR is 80 dB and peak SNDR is 78 dB. The modulator consumes only 50 mW.
{"title":"A 50-mW 14-bit 2.5-MS/s /spl Sigma/-/spl Delta/ modulator in a 0.25 /spl mu/m digital CMOS technology","authors":"P. Balmelli, Qiuting Huang, F. Piazza","doi":"10.1109/VLSIC.2000.852873","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852873","url":null,"abstract":"A 5/sup th/-order single-loop /spl Sigma/-/spl Delta/ modulator has been implemented in a 0.25 /spl mu/m digital CMOS process, where the supply voltage is only 2.5 V and the capacitor option is not available. A tri-level quantizer is used to improve loop stability. The sampling frequency of the modulator is 80 MHz and the oversampling ratio is 32. Measured over a 1 MHz signal bandwidth, dynamic range is 86 dB, peak SNR is 80 dB and peak SNDR is 78 dB. The modulator consumes only 50 mW.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"47 1","pages":"142-143"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82478478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852836
K. Nagata
In this paper the requirements for devices such as LSI, DSP, LCD etc. are described from the IMT-2000 mobile terminal point of view. The article also mentions the mobile telecommunication's generations, its current market and service, IMT-2000 standardization status and the real system development in Japan so as to better understand its background.
{"title":"IMT-2000 terminal and its requirements for device technologies","authors":"K. Nagata","doi":"10.1109/VLSIC.2000.852836","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852836","url":null,"abstract":"In this paper the requirements for devices such as LSI, DSP, LCD etc. are described from the IMT-2000 mobile terminal point of view. The article also mentions the mobile telecommunication's generations, its current market and service, IMT-2000 standardization status and the real system development in Japan so as to better understand its background.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"4 1","pages":"2-5"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79816369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852867
H. Mizuno, N. Oodaira, Y. Kanno, T. Sakata, T. Watanabe
We have designed a CMOS-logic-circuit-compatible DRAM circuit with dual-precharge-level sensing and single-bitline rewriting schemes. This DRAM circuitry is well-matched to modern CMOS logic circuitry; both circuits show similar operating speed dependence on supply voltage and temperature: e.g., they operate down to 0.75 V under V/sub th/ of 0.35 V/spl plusmn/0.1 V with a 0.15-/spl mu/m CMOS technology. Hence, on DRAM containing both types of circuit on a single die: these circuits can reach their maximum performance at the same time over wide-voltage and wide-temperature ranges. The estimated t/sub cycle/ of such as a DRAM is 10 ns at V/sub DD/=1.0 V, V/sub th/=0.35 V, and T/sub j/=75/spl deg/C.
{"title":"CMOS-logic-circuit-compatible DRAM circuit designs for wide-voltage and wide-temperature-range applications","authors":"H. Mizuno, N. Oodaira, Y. Kanno, T. Sakata, T. Watanabe","doi":"10.1109/VLSIC.2000.852867","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852867","url":null,"abstract":"We have designed a CMOS-logic-circuit-compatible DRAM circuit with dual-precharge-level sensing and single-bitline rewriting schemes. This DRAM circuitry is well-matched to modern CMOS logic circuitry; both circuits show similar operating speed dependence on supply voltage and temperature: e.g., they operate down to 0.75 V under V/sub th/ of 0.35 V/spl plusmn/0.1 V with a 0.15-/spl mu/m CMOS technology. Hence, on DRAM containing both types of circuit on a single die: these circuits can reach their maximum performance at the same time over wide-voltage and wide-temperature ranges. The estimated t/sub cycle/ of such as a DRAM is 10 ns at V/sub DD/=1.0 V, V/sub th/=0.35 V, and T/sub j/=75/spl deg/C.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"70 1","pages":"120-121"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81163968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852870
D. Friedman, M. Meghelli, H. Ainspan, M. Soyuer
Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10 Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5 GHz clock with 0.4 ps rms jitter synthesized from a /spl sim/195.3 MHz reference. The receive PLL (RxPLL), which exhibits <0.56 ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5 Gb/s input bit stream. The RxPLL operates error-free when tested with a 14 km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3 V are 270 mW and 330 mW, respectively.
{"title":"Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication","authors":"D. Friedman, M. Meghelli, H. Ainspan, M. Soyuer","doi":"10.1109/VLSIC.2000.852870","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852870","url":null,"abstract":"Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10 Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5 GHz clock with 0.4 ps rms jitter synthesized from a /spl sim/195.3 MHz reference. The receive PLL (RxPLL), which exhibits <0.56 ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5 Gb/s input bit stream. The RxPLL operates error-free when tested with a 14 km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3 V are 270 mW and 330 mW, respectively.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"32 1","pages":"132-135"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88857136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852878
R. McPartland, R. Singh
A low cost, embedded flash memory cell, with read control-gate voltage as low as 1.25 volts, has been developed. Single cell testers and 4 kbit arrays have been fabricated and characterized. Fabrication requires only a single masking step (thick gate oxide) above that used in high-performance core CMOS logic technologies. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and other switch functions.
{"title":"1.25 volt, low cost, embedded flash memory for low density applications","authors":"R. McPartland, R. Singh","doi":"10.1109/VLSIC.2000.852878","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852878","url":null,"abstract":"A low cost, embedded flash memory cell, with read control-gate voltage as low as 1.25 volts, has been developed. Single cell testers and 4 kbit arrays have been fabricated and characterized. Fabrication requires only a single masking step (thick gate oxide) above that used in high-performance core CMOS logic technologies. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and other switch functions.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"319 1","pages":"158-161"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85423642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852897
R. Joshi, S. Kowalczyk, Y. Chan, W. Huott, S.C. Wilson, G. J. Scharff
This paper describes a high speed L1 directory (34 Kb) with read access time below 430 ps and a cycle of 2 GHz in 1.5 V, 0.18 /spl mu/m CMOS bulk technology. The key features of this high performance dynamic design are fast static input/output interface with the provision of converting internal signals from static to dynamic and then back to static at the output, L1/L2 latches at the input, modular building blocks, pseudo-static circuits, robust timing plan and capability for extensive test pattern coverage and access time evaluation using a programmable "Array-Built-In-Self-Test" (ABIST).
{"title":"A 2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 /spl mu/m CMOS bulk technology","authors":"R. Joshi, S. Kowalczyk, Y. Chan, W. Huott, S.C. Wilson, G. J. Scharff","doi":"10.1109/VLSIC.2000.852897","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852897","url":null,"abstract":"This paper describes a high speed L1 directory (34 Kb) with read access time below 430 ps and a cycle of 2 GHz in 1.5 V, 0.18 /spl mu/m CMOS bulk technology. The key features of this high performance dynamic design are fast static input/output interface with the provision of converting internal signals from static to dynamic and then back to static at the output, L1/L2 latches at the input, modular building blocks, pseudo-static circuits, robust timing plan and capability for extensive test pattern coverage and access time evaluation using a programmable \"Array-Built-In-Self-Test\" (ABIST).","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"1993 1","pages":"222-225"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82390088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852898
K. Zhang, K. Hose, V. De, B. Senyk
Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.
{"title":"The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies","authors":"K. Zhang, K. Hose, V. De, B. Senyk","doi":"10.1109/VLSIC.2000.852898","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852898","url":null,"abstract":"Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"39 1","pages":"226-227"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79514183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852889
R. Lal, W. Athas, L. Svensson
We present an ultra low-power driver system for driving the column lines of an active matrix liquid-crystal display. The demonstration system is a 160/spl times/120 pixel liquid-crystal-on-silicon (LCOS) microdisplay. Laboratory measurements show an energy saving of 50% to 65% relative to CV/sub dd/V/sub out/, which is the lower limit for the energy consumed by a conventional driver. The column drivers of this display dissipate only 10 /spl mu/W when displaying a checkered, black and white image at a 25 MHz pixel frequency, 60 Hz refresh rate, and 5 V operating voltage.
{"title":"A low-power adiabatic driver system for AMLCDs","authors":"R. Lal, W. Athas, L. Svensson","doi":"10.1109/VLSIC.2000.852889","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852889","url":null,"abstract":"We present an ultra low-power driver system for driving the column lines of an active matrix liquid-crystal display. The demonstration system is a 160/spl times/120 pixel liquid-crystal-on-silicon (LCOS) microdisplay. Laboratory measurements show an energy saving of 50% to 65% relative to CV/sub dd/V/sub out/, which is the lower limit for the energy consumed by a conventional driver. The column drivers of this display dissipate only 10 /spl mu/W when displaying a checkered, black and white image at a 25 MHz pixel frequency, 60 Hz refresh rate, and 5 V operating voltage.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"181 1","pages":"198-201"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76770811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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