Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852884
J. Guido, V. Leung, J. Kenney, J. Trackim, A. Agrillo, E. Zimany, R. Shariatdoust
A 0.6 um CMOS analog front end IC supporting ADSL central office and remote terminal (category I and II) modem applications is developed. The receive path contains a low-noise programmable gain amplifier, analog equalizer, antialiasing filter, and a 12 bit A/D converter. The transmit channel incorporates a 14 bit D/A converter and a low-pass filter. The IC consumes 525 mW on a 5 V supply.
开发了一种支持ADSL中局和远程终端(I类和II类)调制解调器应用的0.6 um CMOS模拟前端IC。接收路径包含一个低噪声可编程增益放大器、模拟均衡器、抗混叠滤波器和一个12位a /D转换器。发射通道包含一个14位的D/ a转换器和一个低通滤波器。集成电路在5v电源上消耗525mw。
{"title":"Analog front end IC for category I and II ADSL","authors":"J. Guido, V. Leung, J. Kenney, J. Trackim, A. Agrillo, E. Zimany, R. Shariatdoust","doi":"10.1109/VLSIC.2000.852884","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852884","url":null,"abstract":"A 0.6 um CMOS analog front end IC supporting ADSL central office and remote terminal (category I and II) modem applications is developed. The receive path contains a low-noise programmable gain amplifier, analog equalizer, antialiasing filter, and a 12 bit A/D converter. The transmit channel incorporates a 14 bit D/A converter and a low-pass filter. The IC consumes 525 mW on a 5 V supply.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"32 1","pages":"178-181"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83637183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852860
E. Sacchi, I. Bietti, F. Gatta, F. Svelto, R. Castello
A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.
{"title":"A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA","authors":"E. Sacchi, I. Bietti, F. Gatta, F. Svelto, R. Castello","doi":"10.1109/VLSIC.2000.852860","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852860","url":null,"abstract":"A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"87 1","pages":"94-97"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77075181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852856
Hideharu Yahata, Y. Okuda, Hiroki Miyashita, H. Chigasaki, Binhaku Taruishi, T. Akiba, Y. Kawase, T. Tachibana, S. Ueda, S. Aoyama, A. Tsukimori, Ken Shibata, M. Horiguchi, Yozo Saiki, Y. Nakagome
The developed 256-Mb double-data-rate (DDR) SDRAM employs a one-cycle stage-selection analog DLL (delayed-locked loop) circuit-running at IO mW with a 20-ps jitter and a 65- cycles lock-in - and a fully differential clocking system to provide 2~ 0.33-ns clock-to-data-output delay, 0.06-ns setup time and 0.26-ns hold time with respect to the data strobe. This performance represents the possibility of over 250-MHz (500 Mb/s/pin) operation. An even/odd-shared redundancy circuit for a 2-b prefetch reduces the number of fuses by 33%.
{"title":"A 256-Mb Double-Data-Rate SDRAM with a 10-mW Analog DLL Circuit","authors":"Hideharu Yahata, Y. Okuda, Hiroki Miyashita, H. Chigasaki, Binhaku Taruishi, T. Akiba, Y. Kawase, T. Tachibana, S. Ueda, S. Aoyama, A. Tsukimori, Ken Shibata, M. Horiguchi, Yozo Saiki, Y. Nakagome","doi":"10.1109/VLSIC.2000.852856","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852856","url":null,"abstract":"The developed 256-Mb double-data-rate (DDR) SDRAM employs a one-cycle stage-selection analog DLL (delayed-locked loop) circuit-running at IO mW with a 20-ps jitter and a 65- cycles lock-in - and a fully differential clocking system to provide 2~ 0.33-ns clock-to-data-output delay, 0.06-ns setup time and 0.26-ns hold time with respect to the data strobe. This performance represents the possibility of over 250-MHz (500 Mb/s/pin) operation. An even/odd-shared redundancy circuit for a 2-b prefetch reduces the number of fuses by 33%.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"48 13","pages":"74-75"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91455622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852871
J. Savoj, B. Razavi
A 10-Gb/s phase-locked clock and data recovery circuit incorporates a 5-GHz interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology, the circuit exhibits an rms jitter of 6.6 ps in the recovered clock with random data input of length 2/sup 23/-1. The power dissipation is 99 mW from a 2.6-V supply.
{"title":"A 10-Gb/s CMOS clock and data recovery circuit","authors":"J. Savoj, B. Razavi","doi":"10.1109/VLSIC.2000.852871","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852871","url":null,"abstract":"A 10-Gb/s phase-locked clock and data recovery circuit incorporates a 5-GHz interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology, the circuit exhibits an rms jitter of 6.6 ps in the recovered clock with random data input of length 2/sup 23/-1. The power dissipation is 99 mW from a 2.6-V supply.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"8 1","pages":"136-139"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74753369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852887
Jaehong Park, H. Ngo, S. Dhong
This paper presents a fast 64-bit parallel carry look-ahead binary adder implemented in a 1 GHz research prototype 64-bit PowerPC microprocessor. Efficient use of dynamic compound gates enables implementation of the adder in just three stages of delayed reset dynamic logic. The computation uses only G (Generate) and P (Propagate), and the inverse of Carry is computed from G, P, and a strobe signal.
{"title":"470 ps 64-bit parallel binary adder [for CPU chip]","authors":"Jaehong Park, H. Ngo, S. Dhong","doi":"10.1109/VLSIC.2000.852887","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852887","url":null,"abstract":"This paper presents a fast 64-bit parallel carry look-ahead binary adder implemented in a 1 GHz research prototype 64-bit PowerPC microprocessor. Efficient use of dynamic compound gates enables implementation of the adder in just three stages of delayed reset dynamic logic. The computation uses only G (Generate) and P (Propagate), and the inverse of Carry is computed from G, P, and a strobe signal.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"36 1","pages":"192-193"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84927287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852861
T. Wakimoto, T. Hatano, C. Yamaguchi, H. Morimura, S. Konaka
To lower the supply voltage and reduce the power dissipation of the RF front-end of wireless communication systems, a double-balanced square-law MOSFET mixer is proposed. It is applied to up- and down-conversion mixer cores. Implemented in a 0.35-/spl mu/m CMOS process, the up-conversion mixer core operates with a supply voltage of 0.5 V and a supply current of 0.8 mA in the 5-GHz band. The local leakage is suppressed below -40 dBc. The down-conversion mixer core drains 0.4 mA from a 1-V supply in the same band. The conversion gain is 6 dB and the 3rd-order input-referred intercept point (IIP3) is +5 dBm.
{"title":"Sub 1-V 5-GHz-band up- and down-conversion mixer cores in 0.35-/spl mu/m CMOS","authors":"T. Wakimoto, T. Hatano, C. Yamaguchi, H. Morimura, S. Konaka","doi":"10.1109/VLSIC.2000.852861","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852861","url":null,"abstract":"To lower the supply voltage and reduce the power dissipation of the RF front-end of wireless communication systems, a double-balanced square-law MOSFET mixer is proposed. It is applied to up- and down-conversion mixer cores. Implemented in a 0.35-/spl mu/m CMOS process, the up-conversion mixer core operates with a supply voltage of 0.5 V and a supply current of 0.8 mA in the 5-GHz band. The local leakage is suppressed below -40 dBc. The down-conversion mixer core drains 0.4 mA from a 1-V supply in the same band. The conversion gain is 6 dB and the 3rd-order input-referred intercept point (IIP3) is +5 dBm.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"34 1","pages":"98-99"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72922229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852881
H.H. Kim, S. Chandrasekhar, C. Burrus, J. Bauman
A trans-impedance amplifier integrated with an InP PIN photodiode has been demonstrated for 10 Gb SONET receiver. The shunt feedback trans-impedance amplifier is fabricated in 0.25 /spl mu/m modular Si BICMOS technology. The feedback resistance of 870 /spl Omega/ is achieved with a bandwidth of 8.5 GHz. The sensitivity of the trans-impedance amplifier at 10 Gb/s is -17 dBm at a bit-error-rate (BER) of 10/sup -12/ with 2/sup 31/-1 pseudo-random bits.
{"title":"A Si BiCMOS trans-impedance amplifier for 10 Gb SONET receiver","authors":"H.H. Kim, S. Chandrasekhar, C. Burrus, J. Bauman","doi":"10.1109/VLSIC.2000.852881","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852881","url":null,"abstract":"A trans-impedance amplifier integrated with an InP PIN photodiode has been demonstrated for 10 Gb SONET receiver. The shunt feedback trans-impedance amplifier is fabricated in 0.25 /spl mu/m modular Si BICMOS technology. The feedback resistance of 870 /spl Omega/ is achieved with a bandwidth of 8.5 GHz. The sensitivity of the trans-impedance amplifier at 10 Gb/s is -17 dBm at a bit-error-rate (BER) of 10/sup -12/ with 2/sup 31/-1 pseudo-random bits.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"22 1","pages":"170-173"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81522912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852866
T. Sakata, S. Morita, O. Nagashima, H. Noda, T. Takahashi, T. Sonoda, H. Tadokoro, H. Ichikawa, T. Adou, S. Hanzawa, M. Ohi, S. Ookuma, Y. Suzuki, H. Tanaka, K. Ishii
Two circuit techniques are proposed to design a SDRAM which operates both at a double-data-rate (DDR) and a single-data-rate (SDR). The common/separated I/O scheme enables 2-bit prefetching under a DDR and interrupt operations under an SDR with half the number of data-bus lines otherwise needed. The SSTL/LVTTL-compatible input buffer allows a narrow setup/hold time. Furthermore, the three-size flexible column redundancy enhances the yield. To evaluate these techniques, a 256-Mb SDRAM has been designed assuming 0.16-/spl mu/m technology and simulated with 167-MHz operations.
{"title":"A DDR/SDR-compatible SDRAM design with a three-size flexible column redundancy","authors":"T. Sakata, S. Morita, O. Nagashima, H. Noda, T. Takahashi, T. Sonoda, H. Tadokoro, H. Ichikawa, T. Adou, S. Hanzawa, M. Ohi, S. Ookuma, Y. Suzuki, H. Tanaka, K. Ishii","doi":"10.1109/VLSIC.2000.852866","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852866","url":null,"abstract":"Two circuit techniques are proposed to design a SDRAM which operates both at a double-data-rate (DDR) and a single-data-rate (SDR). The common/separated I/O scheme enables 2-bit prefetching under a DDR and interrupt operations under an SDR with half the number of data-bus lines otherwise needed. The SSTL/LVTTL-compatible input buffer allows a narrow setup/hold time. Furthermore, the three-size flexible column redundancy enhances the yield. To evaluate these techniques, a 256-Mb SDRAM has been designed assuming 0.16-/spl mu/m technology and simulated with 167-MHz operations.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"11 1","pages":"116-119"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90482031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852896
J. Silberman, N. Aoki, N. Kojima, Sang Dhong
A 64-kByte cache exploits combined address generation and word line decoding in the SRAM array, translation array, and directory. In place of a late select, set selection in the two-way associative cache is accomplished in the decode path by accessing a stored prediction from a sum-indexed array built into the decoder.
{"title":"A 1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache","authors":"J. Silberman, N. Aoki, N. Kojima, Sang Dhong","doi":"10.1109/VLSIC.2000.852896","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852896","url":null,"abstract":"A 64-kByte cache exploits combined address generation and word line decoding in the SRAM array, translation array, and directory. In place of a late select, set selection in the two-way associative cache is accomplished in the decode path by accessing a stored prediction from a sum-indexed array built into the decoder.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"51 1","pages":"220-221"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82867389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852859
C. Hwang
For the new millennium, several "third" dimensional approaches in the memory area will take place with continuous revolutionary development from current technologies for various customers' demands. In the mean time, various and combined evolutionary technologies such as micro-machining technology, multi-chip stacking techniques, mixed digital/analog circuits, merged memories on a chip, cloning and genetics, biochemistry and magnetics areas are awaiting a breakthrough and will be pursued toward the generic memory goals of high density, high speed and low power more closely.
{"title":"Where does memory go in the 21C? (Evolution and revolution of memory technology)","authors":"C. Hwang","doi":"10.1109/VLSIC.2000.852859","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852859","url":null,"abstract":"For the new millennium, several \"third\" dimensional approaches in the memory area will take place with continuous revolutionary development from current technologies for various customers' demands. In the mean time, various and combined evolutionary technologies such as micro-machining technology, multi-chip stacking techniques, mixed digital/analog circuits, merged memories on a chip, cloning and genetics, biochemistry and magnetics areas are awaiting a breakthrough and will be pursued toward the generic memory goals of high density, high speed and low power more closely.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"1 1","pages":"88-91"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89768090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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