Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117697
T. Yan, X. Shen, P. Jiang, J. J. Zhou
A high linear fully differential RF CMOS amplifier covering UHF band is presented in this paper. A novel structure with both NMOS and PMOS differential pairs is proposed to cancel IM3 induced by 1st order derivative of transconductance (gm') and 2nd order derivative of transconductance (gm"). With appropriate DC operating points and aspect ratios, the RF CMOS amplifier achieves 12.5dB noise figure (NF), 10.5dB voltage gain and 17.5dBm input third order intercept point (IIP3) with total current consumption of 2mA from 1.8V voltage supply. The proposed amplifier is designed in TSMC 0.18µm CMOS process.
{"title":"A 17.5dBm IIP3 high linear fully differential RF CMOS amplifier","authors":"T. Yan, X. Shen, P. Jiang, J. J. Zhou","doi":"10.1109/EDSSC.2011.6117697","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117697","url":null,"abstract":"A high linear fully differential RF CMOS amplifier covering UHF band is presented in this paper. A novel structure with both NMOS and PMOS differential pairs is proposed to cancel IM3 induced by 1st order derivative of transconductance (gm') and 2nd order derivative of transconductance (gm\"). With appropriate DC operating points and aspect ratios, the RF CMOS amplifier achieves 12.5dB noise figure (NF), 10.5dB voltage gain and 17.5dBm input third order intercept point (IIP3) with total current consumption of 2mA from 1.8V voltage supply. The proposed amplifier is designed in TSMC 0.18µm CMOS process.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74449200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117706
Weiyang Liu, N. Wu
A novel parallel random number generator (RNG) based on two dimensions feedback shift register (2-DFSR), genetic algorithm (GA) and cellular automaton (CA) algorithms is proposed for wireless medical security applications. The measurement results demonstrated that the RNG can successfully pass the NIST 800-22 statistical test suite. The highest bit rate is 16 Mbps. The typical power consumption is 61.81 µW. Its energy efficiency is 3.86 pJ/bit.
{"title":"A novel parallel random number generator for wireless medical security applications","authors":"Weiyang Liu, N. Wu","doi":"10.1109/EDSSC.2011.6117706","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117706","url":null,"abstract":"A novel parallel random number generator (RNG) based on two dimensions feedback shift register (2-DFSR), genetic algorithm (GA) and cellular automaton (CA) algorithms is proposed for wireless medical security applications. The measurement results demonstrated that the RNG can successfully pass the NIST 800-22 statistical test suite. The highest bit rate is 16 Mbps. The typical power consumption is 61.81 µW. Its energy efficiency is 3.86 pJ/bit.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"29 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80161309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117565
C. Tan, M. D. Le
Inductive Couple Plasma (ICP) etching tool has been commonly used for higher throughput and better width control in semiconductor processing. However, this process is often contaminated by particles, and Particle per Wafer Pass (PWP) test must be carried out to monitor the contamination. Unfortunately, in actual manufacturing, the gaseous recipes used during etching vary on the etched materials, which lead to unexpected and unpredictable byproducts and particle counts in a given production run, rendering the particle count from PWP highly stochastic which may result in missing of the time for necessary wet cleaning of the chamber. In this work, we analyze the daily PWP results from an inductively coupled plasma etching (ICP) chamber for an eight-month period. The behavior of the particle count can be modeled as a stochastic function of the accumulated gaseous recipes flowing though the chamber. The particle count is found to follow a Negative Binomial (NB) distribution with varied parameters. The model is useful in determining the optimal time for wet clean
{"title":"Contamination assessment of inductive couple plasma etching chamber under mixture of recipes using statistical method","authors":"C. Tan, M. D. Le","doi":"10.1109/EDSSC.2011.6117565","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117565","url":null,"abstract":"Inductive Couple Plasma (ICP) etching tool has been commonly used for higher throughput and better width control in semiconductor processing. However, this process is often contaminated by particles, and Particle per Wafer Pass (PWP) test must be carried out to monitor the contamination. Unfortunately, in actual manufacturing, the gaseous recipes used during etching vary on the etched materials, which lead to unexpected and unpredictable byproducts and particle counts in a given production run, rendering the particle count from PWP highly stochastic which may result in missing of the time for necessary wet cleaning of the chamber. In this work, we analyze the daily PWP results from an inductively coupled plasma etching (ICP) chamber for an eight-month period. The behavior of the particle count can be modeled as a stochastic function of the accumulated gaseous recipes flowing though the chamber. The particle count is found to follow a Negative Binomial (NB) distribution with varied parameters. The model is useful in determining the optimal time for wet clean","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80023592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117709
To-Po Wang
A low-power low-phase-noise wide-tuning-range 60-GHz push-push voltage-controlled oscillator (VCO) is presented in this paper. To eliminate the required λ/4 micropstrip or coplanar waveguide (CPW) line of the conventional push-push VCO, the enhanced second-harmonic output signal (2fo) is extracted at middle of the varactors, leading to a minimized chip area. By employing MOS varactors deposited between the drain and source terminations of the cross-coupled pair, the tuning range is effectively boosted, and the phase noise is improved. According to these techniques, the fabricated 0.18-µm CMOS VCO exhibits a measured 8.3% tuning range. Operating at 1.2-V supply voltage, the VCO dissipates 7.7-mW dc power excluding the testing buffers. The measured phase noise at 1-MHz offset from 61.5-GHz oscillation frequency is •91.5 dBc/Hz. Compared to recently published 60-GHz VCOs in 0.13-µm CMOS, this work can simultaneously achieve low phase noise, wide tuning range, and low dc power, resulting in the better figure of merit (FOM) and figure of merit considering the tuning range (FOMT).
{"title":"A low-power low-phase-noise wide-tuning-range 60-GHz voltage-controlled oscillator in 0.18-µm CMOS","authors":"To-Po Wang","doi":"10.1109/EDSSC.2011.6117709","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117709","url":null,"abstract":"A low-power low-phase-noise wide-tuning-range 60-GHz push-push voltage-controlled oscillator (VCO) is presented in this paper. To eliminate the required λ/4 micropstrip or coplanar waveguide (CPW) line of the conventional push-push VCO, the enhanced second-harmonic output signal (2fo) is extracted at middle of the varactors, leading to a minimized chip area. By employing MOS varactors deposited between the drain and source terminations of the cross-coupled pair, the tuning range is effectively boosted, and the phase noise is improved. According to these techniques, the fabricated 0.18-µm CMOS VCO exhibits a measured 8.3% tuning range. Operating at 1.2-V supply voltage, the VCO dissipates 7.7-mW dc power excluding the testing buffers. The measured phase noise at 1-MHz offset from 61.5-GHz oscillation frequency is •91.5 dBc/Hz. Compared to recently published 60-GHz VCOs in 0.13-µm CMOS, this work can simultaneously achieve low phase noise, wide tuning range, and low dc power, resulting in the better figure of merit (FOM) and figure of merit considering the tuning range (FOMT).","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"19 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88922178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117652
F. Meng, Kaixue Ma, K. Yeo, Shanshan Xu, M. Nagarajan
This paper presents a compact microstrip bandpass filter (BPF) with separate electric and magnetic coupling paths (SEMCPs) for 60 GHz applications. Either electric or magnetic coupling can be dominant in the total electromagnetic coupling, while the location of transmission zeros differs. The proposed fourth-order BPF is designed based on two metal layers of a 85 µm LTCC substrate. Without any via connections, the design configuration is very simple which facilitates the crafts of fabrications. The filter achieves a center frequency of 60.275 GHz, a 3-dB bandwidth of 3.15 GHz (5.22%), and a compact size of only 1.3 × 0.74 mm2. The minimum insertion loss of the filter is 2.7 dB and the return loss is better than 17 dB in the passband.
{"title":"A compact 60 GHz LTCC microstrip bandpass filter with controllable transmission zeros","authors":"F. Meng, Kaixue Ma, K. Yeo, Shanshan Xu, M. Nagarajan","doi":"10.1109/EDSSC.2011.6117652","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117652","url":null,"abstract":"This paper presents a compact microstrip bandpass filter (BPF) with separate electric and magnetic coupling paths (SEMCPs) for 60 GHz applications. Either electric or magnetic coupling can be dominant in the total electromagnetic coupling, while the location of transmission zeros differs. The proposed fourth-order BPF is designed based on two metal layers of a 85 µm LTCC substrate. Without any via connections, the design configuration is very simple which facilitates the crafts of fabrications. The filter achieves a center frequency of 60.275 GHz, a 3-dB bandwidth of 3.15 GHz (5.22%), and a compact size of only 1.3 × 0.74 mm2. The minimum insertion loss of the filter is 2.7 dB and the return loss is better than 17 dB in the passband.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"69 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85820572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a new structure of LED(Light-emitting diode) driver for obtaining a low mismatch output current between different channels and even reduces the chip area. It's fabricated with TSMC 0.35µm DDD process. The chip contains 16 channels and the maximum/minimum output current is 3mA/45mA, respectively. The value of each channel's output current is the same and controlled by a programmable 6-bits digital input signals. The circuit uses constant gate voltage of the power MOS working in the linear region whose (Vgs — Vth) is 10 to 50 times of Vds. The advantage is no DAC(Digital-to-Analog Converter) and no complex gate voltage generating circuit. Simple gate voltage generating circuit can also adapt to a wide range of external resistance changes. Because of the lower mismatch caused by threshold voltage mismatch, it can achieve a highly matched output current. The chip has only ±1.1% mismatch between different channels. The area of each channel's power MOS is only 200µm× 100µm. The area of analog part including current bias, bandgap reference, current mirror, and other control circuits is only 400µm×200µm.
{"title":"A small-area low-mismatch multi-channel constant current LED driver","authors":"Ze Huang, Wengao Lu, Lilan Yu, Guannan Wang, Xiangyun Meng, Yacong Zhang, Zhongjian Chen","doi":"10.1109/EDSSC.2011.6117624","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117624","url":null,"abstract":"This paper proposes a new structure of LED(Light-emitting diode) driver for obtaining a low mismatch output current between different channels and even reduces the chip area. It's fabricated with TSMC 0.35µm DDD process. The chip contains 16 channels and the maximum/minimum output current is 3mA/45mA, respectively. The value of each channel's output current is the same and controlled by a programmable 6-bits digital input signals. The circuit uses constant gate voltage of the power MOS working in the linear region whose (Vgs — Vth) is 10 to 50 times of Vds. The advantage is no DAC(Digital-to-Analog Converter) and no complex gate voltage generating circuit. Simple gate voltage generating circuit can also adapt to a wide range of external resistance changes. Because of the lower mismatch caused by threshold voltage mismatch, it can achieve a highly matched output current. The chip has only ±1.1% mismatch between different channels. The area of each channel's power MOS is only 200µm× 100µm. The area of analog part including current bias, bandgap reference, current mirror, and other control circuits is only 400µm×200µm.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"11 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81778021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a low-cost VLSI implementation for Block Matching (BM) in BM3D image denoising with novel architectures of the slip window and SSD tree are presented. The experimental results show that the proposed technique preserves the BM3D denoising performance and obtains excellent performances in terms of less logic gate count and better visual quality. The design requires only low computational complexity and less SRAM for slip window. Its hardware cost is quite low, about 350k gates. Synthesis results show that the proposed design at a throughput about 177MB/s by using UMC 0.18um technology.
{"title":"Analysis and architecture design of block matching in BM3D image denoising","authors":"Hongming Chen, Wenjiang Liu, Taizhi Liu, Yuhua Cheng","doi":"10.1109/EDSSC.2011.6117574","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117574","url":null,"abstract":"In this paper, a low-cost VLSI implementation for Block Matching (BM) in BM3D image denoising with novel architectures of the slip window and SSD tree are presented. The experimental results show that the proposed technique preserves the BM3D denoising performance and obtains excellent performances in terms of less logic gate count and better visual quality. The design requires only low computational complexity and less SRAM for slip window. Its hardware cost is quite low, about 350k gates. Synthesis results show that the proposed design at a throughput about 177MB/s by using UMC 0.18um technology.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79563703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117644
M. Nagarajan, Kaixue Ma, K. Yeo, Shouxian Mou, T. B. Kumar
A fully integrated fundamental and push-push voltage controlled oscillators (VCOs) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 µm SiGe BiCMOS technology is presented. To achieve a wide tuning range while maintaining a low VCO tuning sensitivity (Kvco), the coupled LC tanks and digital tuning capacitors are used. The VCOs achieve a frequency tuning range (FTR) of 17% with a low phase noise consuming 7 mW from 1.8V voltage supply.
{"title":"A low power 17% tuning range low phase noise VCOs using coupled LC tanks","authors":"M. Nagarajan, Kaixue Ma, K. Yeo, Shouxian Mou, T. B. Kumar","doi":"10.1109/EDSSC.2011.6117644","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117644","url":null,"abstract":"A fully integrated fundamental and push-push voltage controlled oscillators (VCOs) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 µm SiGe BiCMOS technology is presented. To achieve a wide tuning range while maintaining a low VCO tuning sensitivity (Kvco), the coupled LC tanks and digital tuning capacitors are used. The VCOs achieve a frequency tuning range (FTR) of 17% with a low phase noise consuming 7 mW from 1.8V voltage supply.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"83 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78215685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117613
Li De, Zhang Shilin, Mao Luhong, Xie Sheng, Deng Jianbao
A 512 bit EEPROM IP which is based on the SMIC 0.18 µm 2P6M embedded EEPROM process has been designed for RFID tag IC in this paper. The main improvement of the IP circuits includes timing control circuit of the digital circuit, charge pump and sense amplifier of the artificial circuit. A block erasing signal is added in the timing control circuit. Considering the request of low power consumption, the high voltage generator and the regulator of the charge pump are also improved. Current sensing scheme is employed in the design of sense amplifier (SA).
{"title":"An improved 512 bit EEPROM IP for RFID tag IC","authors":"Li De, Zhang Shilin, Mao Luhong, Xie Sheng, Deng Jianbao","doi":"10.1109/EDSSC.2011.6117613","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117613","url":null,"abstract":"A 512 bit EEPROM IP which is based on the SMIC 0.18 µm 2P6M embedded EEPROM process has been designed for RFID tag IC in this paper. The main improvement of the IP circuits includes timing control circuit of the digital circuit, charge pump and sense amplifier of the artificial circuit. A block erasing signal is added in the timing control circuit. Considering the request of low power consumption, the high voltage generator and the regulator of the charge pump are also improved. Current sensing scheme is employed in the design of sense amplifier (SA).","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85036210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117578
Xinming Duan, Jigang Wu
Fault tolerance is one of the most important issues for the design of cost-effective and high performance interconnection networks. In this paper, a new fault tolerance routing algorithm for n-dimensional meshes is presented. The presented algorithm is based on a planer fault model which only disables minimum fault-free nodes to form rectangular fault regions. The algorithm uses three virtual channels per physical channel and only employs a very simple deadlock avoidance scheme. In spit the variety fault regions in n-dimensional mesh, the presented algorithm is always connected as long as fault regions do not disconnect the network.
{"title":"A deadlock-free fault-tolerant routing algorithm for N-dimesional meshes","authors":"Xinming Duan, Jigang Wu","doi":"10.1109/EDSSC.2011.6117578","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117578","url":null,"abstract":"Fault tolerance is one of the most important issues for the design of cost-effective and high performance interconnection networks. In this paper, a new fault tolerance routing algorithm for n-dimensional meshes is presented. The presented algorithm is based on a planer fault model which only disables minimum fault-free nodes to form rectangular fault regions. The algorithm uses three virtual channels per physical channel and only employs a very simple deadlock avoidance scheme. In spit the variety fault regions in n-dimensional mesh, the presented algorithm is always connected as long as fault regions do not disconnect the network.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89034353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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