Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117613
Li De, Zhang Shilin, Mao Luhong, Xie Sheng, Deng Jianbao
A 512 bit EEPROM IP which is based on the SMIC 0.18 µm 2P6M embedded EEPROM process has been designed for RFID tag IC in this paper. The main improvement of the IP circuits includes timing control circuit of the digital circuit, charge pump and sense amplifier of the artificial circuit. A block erasing signal is added in the timing control circuit. Considering the request of low power consumption, the high voltage generator and the regulator of the charge pump are also improved. Current sensing scheme is employed in the design of sense amplifier (SA).
{"title":"An improved 512 bit EEPROM IP for RFID tag IC","authors":"Li De, Zhang Shilin, Mao Luhong, Xie Sheng, Deng Jianbao","doi":"10.1109/EDSSC.2011.6117613","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117613","url":null,"abstract":"A 512 bit EEPROM IP which is based on the SMIC 0.18 µm 2P6M embedded EEPROM process has been designed for RFID tag IC in this paper. The main improvement of the IP circuits includes timing control circuit of the digital circuit, charge pump and sense amplifier of the artificial circuit. A block erasing signal is added in the timing control circuit. Considering the request of low power consumption, the high voltage generator and the regulator of the charge pump are also improved. Current sensing scheme is employed in the design of sense amplifier (SA).","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85036210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117746
Wei Su, Y. Wang, Junlei Zhao, S. Jia, Xing Zhang
This paper presents a novel dynamic element matching (DEM) method called Thermo Data Weighted Average (TDWA) for Nyquist-rate current — steering digital to analog converter (DAC). When the input code changes, it only increase or decrease the number of unit current source which is be chosen. This approach can reach a better static performance than full random DEM technique but also eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as other DEM implementations.
{"title":"A novel dynamic element matching technique in current-steering DAC","authors":"Wei Su, Y. Wang, Junlei Zhao, S. Jia, Xing Zhang","doi":"10.1109/EDSSC.2011.6117746","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117746","url":null,"abstract":"This paper presents a novel dynamic element matching (DEM) method called Thermo Data Weighted Average (TDWA) for Nyquist-rate current — steering digital to analog converter (DAC). When the input code changes, it only increase or decrease the number of unit current source which is be chosen. This approach can reach a better static performance than full random DEM technique but also eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as other DEM implementations.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"35 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90867191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117652
F. Meng, Kaixue Ma, K. Yeo, Shanshan Xu, M. Nagarajan
This paper presents a compact microstrip bandpass filter (BPF) with separate electric and magnetic coupling paths (SEMCPs) for 60 GHz applications. Either electric or magnetic coupling can be dominant in the total electromagnetic coupling, while the location of transmission zeros differs. The proposed fourth-order BPF is designed based on two metal layers of a 85 µm LTCC substrate. Without any via connections, the design configuration is very simple which facilitates the crafts of fabrications. The filter achieves a center frequency of 60.275 GHz, a 3-dB bandwidth of 3.15 GHz (5.22%), and a compact size of only 1.3 × 0.74 mm2. The minimum insertion loss of the filter is 2.7 dB and the return loss is better than 17 dB in the passband.
{"title":"A compact 60 GHz LTCC microstrip bandpass filter with controllable transmission zeros","authors":"F. Meng, Kaixue Ma, K. Yeo, Shanshan Xu, M. Nagarajan","doi":"10.1109/EDSSC.2011.6117652","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117652","url":null,"abstract":"This paper presents a compact microstrip bandpass filter (BPF) with separate electric and magnetic coupling paths (SEMCPs) for 60 GHz applications. Either electric or magnetic coupling can be dominant in the total electromagnetic coupling, while the location of transmission zeros differs. The proposed fourth-order BPF is designed based on two metal layers of a 85 µm LTCC substrate. Without any via connections, the design configuration is very simple which facilitates the crafts of fabrications. The filter achieves a center frequency of 60.275 GHz, a 3-dB bandwidth of 3.15 GHz (5.22%), and a compact size of only 1.3 × 0.74 mm2. The minimum insertion loss of the filter is 2.7 dB and the return loss is better than 17 dB in the passband.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"69 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85820572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117565
C. Tan, M. D. Le
Inductive Couple Plasma (ICP) etching tool has been commonly used for higher throughput and better width control in semiconductor processing. However, this process is often contaminated by particles, and Particle per Wafer Pass (PWP) test must be carried out to monitor the contamination. Unfortunately, in actual manufacturing, the gaseous recipes used during etching vary on the etched materials, which lead to unexpected and unpredictable byproducts and particle counts in a given production run, rendering the particle count from PWP highly stochastic which may result in missing of the time for necessary wet cleaning of the chamber. In this work, we analyze the daily PWP results from an inductively coupled plasma etching (ICP) chamber for an eight-month period. The behavior of the particle count can be modeled as a stochastic function of the accumulated gaseous recipes flowing though the chamber. The particle count is found to follow a Negative Binomial (NB) distribution with varied parameters. The model is useful in determining the optimal time for wet clean
{"title":"Contamination assessment of inductive couple plasma etching chamber under mixture of recipes using statistical method","authors":"C. Tan, M. D. Le","doi":"10.1109/EDSSC.2011.6117565","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117565","url":null,"abstract":"Inductive Couple Plasma (ICP) etching tool has been commonly used for higher throughput and better width control in semiconductor processing. However, this process is often contaminated by particles, and Particle per Wafer Pass (PWP) test must be carried out to monitor the contamination. Unfortunately, in actual manufacturing, the gaseous recipes used during etching vary on the etched materials, which lead to unexpected and unpredictable byproducts and particle counts in a given production run, rendering the particle count from PWP highly stochastic which may result in missing of the time for necessary wet cleaning of the chamber. In this work, we analyze the daily PWP results from an inductively coupled plasma etching (ICP) chamber for an eight-month period. The behavior of the particle count can be modeled as a stochastic function of the accumulated gaseous recipes flowing though the chamber. The particle count is found to follow a Negative Binomial (NB) distribution with varied parameters. The model is useful in determining the optimal time for wet clean","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80023592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a new structure of LED(Light-emitting diode) driver for obtaining a low mismatch output current between different channels and even reduces the chip area. It's fabricated with TSMC 0.35µm DDD process. The chip contains 16 channels and the maximum/minimum output current is 3mA/45mA, respectively. The value of each channel's output current is the same and controlled by a programmable 6-bits digital input signals. The circuit uses constant gate voltage of the power MOS working in the linear region whose (Vgs — Vth) is 10 to 50 times of Vds. The advantage is no DAC(Digital-to-Analog Converter) and no complex gate voltage generating circuit. Simple gate voltage generating circuit can also adapt to a wide range of external resistance changes. Because of the lower mismatch caused by threshold voltage mismatch, it can achieve a highly matched output current. The chip has only ±1.1% mismatch between different channels. The area of each channel's power MOS is only 200µm× 100µm. The area of analog part including current bias, bandgap reference, current mirror, and other control circuits is only 400µm×200µm.
{"title":"A small-area low-mismatch multi-channel constant current LED driver","authors":"Ze Huang, Wengao Lu, Lilan Yu, Guannan Wang, Xiangyun Meng, Yacong Zhang, Zhongjian Chen","doi":"10.1109/EDSSC.2011.6117624","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117624","url":null,"abstract":"This paper proposes a new structure of LED(Light-emitting diode) driver for obtaining a low mismatch output current between different channels and even reduces the chip area. It's fabricated with TSMC 0.35µm DDD process. The chip contains 16 channels and the maximum/minimum output current is 3mA/45mA, respectively. The value of each channel's output current is the same and controlled by a programmable 6-bits digital input signals. The circuit uses constant gate voltage of the power MOS working in the linear region whose (Vgs — Vth) is 10 to 50 times of Vds. The advantage is no DAC(Digital-to-Analog Converter) and no complex gate voltage generating circuit. Simple gate voltage generating circuit can also adapt to a wide range of external resistance changes. Because of the lower mismatch caused by threshold voltage mismatch, it can achieve a highly matched output current. The chip has only ±1.1% mismatch between different channels. The area of each channel's power MOS is only 200µm× 100µm. The area of analog part including current bias, bandgap reference, current mirror, and other control circuits is only 400µm×200µm.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"11 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81778021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a low-cost VLSI implementation for Block Matching (BM) in BM3D image denoising with novel architectures of the slip window and SSD tree are presented. The experimental results show that the proposed technique preserves the BM3D denoising performance and obtains excellent performances in terms of less logic gate count and better visual quality. The design requires only low computational complexity and less SRAM for slip window. Its hardware cost is quite low, about 350k gates. Synthesis results show that the proposed design at a throughput about 177MB/s by using UMC 0.18um technology.
{"title":"Analysis and architecture design of block matching in BM3D image denoising","authors":"Hongming Chen, Wenjiang Liu, Taizhi Liu, Yuhua Cheng","doi":"10.1109/EDSSC.2011.6117574","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117574","url":null,"abstract":"In this paper, a low-cost VLSI implementation for Block Matching (BM) in BM3D image denoising with novel architectures of the slip window and SSD tree are presented. The experimental results show that the proposed technique preserves the BM3D denoising performance and obtains excellent performances in terms of less logic gate count and better visual quality. The design requires only low computational complexity and less SRAM for slip window. Its hardware cost is quite low, about 350k gates. Synthesis results show that the proposed design at a throughput about 177MB/s by using UMC 0.18um technology.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79563703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117644
M. Nagarajan, Kaixue Ma, K. Yeo, Shouxian Mou, T. B. Kumar
A fully integrated fundamental and push-push voltage controlled oscillators (VCOs) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 µm SiGe BiCMOS technology is presented. To achieve a wide tuning range while maintaining a low VCO tuning sensitivity (Kvco), the coupled LC tanks and digital tuning capacitors are used. The VCOs achieve a frequency tuning range (FTR) of 17% with a low phase noise consuming 7 mW from 1.8V voltage supply.
{"title":"A low power 17% tuning range low phase noise VCOs using coupled LC tanks","authors":"M. Nagarajan, Kaixue Ma, K. Yeo, Shouxian Mou, T. B. Kumar","doi":"10.1109/EDSSC.2011.6117644","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117644","url":null,"abstract":"A fully integrated fundamental and push-push voltage controlled oscillators (VCOs) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 µm SiGe BiCMOS technology is presented. To achieve a wide tuning range while maintaining a low VCO tuning sensitivity (Kvco), the coupled LC tanks and digital tuning capacitors are used. The VCOs achieve a frequency tuning range (FTR) of 17% with a low phase noise consuming 7 mW from 1.8V voltage supply.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"83 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78215685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The growth and crystallization processes of Co20Fe50B30/MgO/Co20Fe50B30 magnetic tunnel junction structures is investigated with 2θ x-ray diffraction. A MgO layer with thickness of 1.5nm was grown on an amorphous CoFeB layer, and then was crystallized. By proper annealing, the crystal structure of MgO has been improved. The results show important information for preparation of magnetic tunnel junction.
{"title":"Crystallization study for MgO in magnetic tunnel junction structure","authors":"Yongle Lou, Yu-Ming Zhang, Daqing Xu, Hui Guo, Yimen Zhang, Renxu Jia, Yang Zhao","doi":"10.1109/EDSSC.2011.6117679","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117679","url":null,"abstract":"The growth and crystallization processes of Co<inf>20</inf>Fe<inf>50</inf>B<inf>30</inf>/MgO/Co<inf>20</inf>Fe<inf>50</inf>B<inf>30</inf> magnetic tunnel junction structures is investigated with 2θ x-ray diffraction. A MgO layer with thickness of 1.5nm was grown on an amorphous CoFeB layer, and then was crystallized. By proper annealing, the crystal structure of MgO has been improved. The results show important information for preparation of magnetic tunnel junction.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73394834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117676
Yuanqing Wu, Su-Ying Yao
As the silicon mold has rough edges, microchip is not conducive to fluid movement. In this paper, mold was produced by SU-8, and a set of production process was given. Then this paper made anti-stick layer on the mold, in order to improve mold re-use rate. Author discussed the impact of curing temperature and the ratio of PDMS and curing agent on the device, and does modification on casting PDMS, then seal to complete the microarray.
{"title":"Preparation of micro fluidic chip based on SU-8 mold","authors":"Yuanqing Wu, Su-Ying Yao","doi":"10.1109/EDSSC.2011.6117676","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117676","url":null,"abstract":"As the silicon mold has rough edges, microchip is not conducive to fluid movement. In this paper, mold was produced by SU-8, and a set of production process was given. Then this paper made anti-stick layer on the mold, in order to improve mold re-use rate. Author discussed the impact of curing temperature and the ratio of PDMS and curing agent on the device, and does modification on casting PDMS, then seal to complete the microarray.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"27 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75445190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117569
Fan Ye, Peng Zhang, Bei Yu, Chixiao Chen, Y. Zhu, Junyan Ren
A digital background calibration for time-interleaved ADC is presented. By using LMS-FIR and interpolation filter, mismatches of offset, gain, bandwidth, and sample-time error are calibrated. Adaptively controlled by correlation evaluation, the calibration is applicable for most input cases. A 14-bit 200-MS/s two-channel time-interleaved ADC is prototyped in a 0.18-µm CMOS process with core area of 15.2 mm2. The ADC achieves an SFDR of 88.9 dBc and an SNDR of 69.5 dBc after calibration, consuming 460 mW at 1.8 V.
{"title":"A 14-bit 200-MS/s time-interleaved ADC calibrated with LMS-FIR and interpolation filter","authors":"Fan Ye, Peng Zhang, Bei Yu, Chixiao Chen, Y. Zhu, Junyan Ren","doi":"10.1109/EDSSC.2011.6117569","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117569","url":null,"abstract":"A digital background calibration for time-interleaved ADC is presented. By using LMS-FIR and interpolation filter, mismatches of offset, gain, bandwidth, and sample-time error are calibrated. Adaptively controlled by correlation evaluation, the calibration is applicable for most input cases. A 14-bit 200-MS/s two-channel time-interleaved ADC is prototyped in a 0.18-µm CMOS process with core area of 15.2 mm2. The ADC achieves an SFDR of 88.9 dBc and an SNDR of 69.5 dBc after calibration, consuming 460 mW at 1.8 V.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"33 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74727474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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