Pub Date : 2011-12-29DOI: 10.1142/S0218126613400239
Shufang Zhu, K. Wei, G. Du, Xiaoyan Liu
Gate-All-Around mosfets have been investigated as promising new device structures, and Germanium is used for its high carrier mobility. In this paper, a 3D parallel Monte Carlo simulation of GAA Ge Nanowire nMOSFET with Effective Potential Method is implemented. Compared the simulation results with classical results, we can see that the quantum effects have an affect on the distribution of density, velocity and energy, and they make a decrease on the drain current as well.
{"title":"3D Monte Carlo simulation of Gate-All-Around Germanium nMOSFET","authors":"Shufang Zhu, K. Wei, G. Du, Xiaoyan Liu","doi":"10.1142/S0218126613400239","DOIUrl":"https://doi.org/10.1142/S0218126613400239","url":null,"abstract":"Gate-All-Around mosfets have been investigated as promising new device structures, and Germanium is used for its high carrier mobility. In this paper, a 3D parallel Monte Carlo simulation of GAA Ge Nanowire nMOSFET with Effective Potential Method is implemented. Compared the simulation results with classical results, we can see that the quantum effects have an affect on the distribution of density, velocity and energy, and they make a decrease on the drain current as well.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"74 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85504324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/ICEPT-HDP.2012.6474776
M. Miao, Xiaoqing Zhang, Yang Zhang, Shufang Xu, Lei Liang, Zhensong Li
THz (Terahertz) technology has made great strides; however, publications on millimeter wave and THz passives, such as filters, are somewhat few by now. This paper proposes design of THz filters based on substrate integrated waveguide (SIW) and cavities implemented by micromachining of low-temperature co-fired ceramic (LTCC) multilayer substrate and utilizes SIW rectangular coupling cavity filter and cylindrical cavity coupling filter mechanism. The filters are embedded in a multi-layer LTCC substrate, and are validated with a finite element full-wave simulation tool. With mid-band frequency set to frequencies in THz bands, both filters demonstrate excellent return loss in stopband and insertion loss in passband; furthermore they are shown promising in combining vacuum microelectronics into highly integrated 3D Microsystem-in-packages.
{"title":"Design and simulation of THz filters embedded in LTCC multi-layer substrate","authors":"M. Miao, Xiaoqing Zhang, Yang Zhang, Shufang Xu, Lei Liang, Zhensong Li","doi":"10.1109/ICEPT-HDP.2012.6474776","DOIUrl":"https://doi.org/10.1109/ICEPT-HDP.2012.6474776","url":null,"abstract":"THz (Terahertz) technology has made great strides; however, publications on millimeter wave and THz passives, such as filters, are somewhat few by now. This paper proposes design of THz filters based on substrate integrated waveguide (SIW) and cavities implemented by micromachining of low-temperature co-fired ceramic (LTCC) multilayer substrate and utilizes SIW rectangular coupling cavity filter and cylindrical cavity coupling filter mechanism. The filters are embedded in a multi-layer LTCC substrate, and are validated with a finite element full-wave simulation tool. With mid-band frequency set to frequencies in THz bands, both filters demonstrate excellent return loss in stopband and insertion loss in passband; furthermore they are shown promising in combining vacuum microelectronics into highly integrated 3D Microsystem-in-packages.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"14 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78326569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117684
Siyang Liu, Weifeng Sun, Weijun Wan, Qinsong Qian, Hu Sun
Hot-carrier-induced degradation in the p-type double diffusion drain MOS (p-DDDMOS) transistor with different p-drift dosage is investigated. Basing on the experimental data and T-CAD simulations, hot-electron injection into the oxide of the p-drift region near the channel has been found, leading to the on-resistance (Ron) decrease, however, no hot-carrier degradation is observed in the channel region. The experimental results also show that higher p-drift dosage will result in much more serious degradation due to much more hot electron injection and trapping.
{"title":"The hot-carrier degradation mechanism of p-DDDMOS transistor with different p-drift dosage","authors":"Siyang Liu, Weifeng Sun, Weijun Wan, Qinsong Qian, Hu Sun","doi":"10.1109/EDSSC.2011.6117684","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117684","url":null,"abstract":"Hot-carrier-induced degradation in the p-type double diffusion drain MOS (p-DDDMOS) transistor with different p-drift dosage is investigated. Basing on the experimental data and T-CAD simulations, hot-electron injection into the oxide of the p-drift region near the channel has been found, leading to the on-resistance (Ron) decrease, however, no hot-carrier degradation is observed in the channel region. The experimental results also show that higher p-drift dosage will result in much more serious degradation due to much more hot electron injection and trapping.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80100859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117705
Jianping Ding, Y. Wang, S. Jia, G. Du, Xing Zhang
A new charge pump schematic, using swing enhanced clock to increase the output voltage, are proposed. Simulation result presents that the proposed circuit can reach higher output voltage than traditional Dickson charge pump. Under 5V power voltage, proposed 8-stage circuit can reach 52.2V, while traditional 39.6V.
{"title":"Clock swing enhanced charge pump","authors":"Jianping Ding, Y. Wang, S. Jia, G. Du, Xing Zhang","doi":"10.1109/EDSSC.2011.6117705","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117705","url":null,"abstract":"A new charge pump schematic, using swing enhanced clock to increase the output voltage, are proposed. Simulation result presents that the proposed circuit can reach higher output voltage than traditional Dickson charge pump. Under 5V power voltage, proposed 8-stage circuit can reach 52.2V, while traditional 39.6V.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76694639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117589
Chen Liang, Zhang Wan-rong, Jin Dong-yue, Ding Chun-bao, Zhang Yu-jie, Lu Zhi-yi
The effect of bandgap engineering on IC-VBE flyback characteristic of power SiGe heterojunction bipolar transistor is studied through theoretical analysis, computer simulations, and experimental measurements. It is found that because of the existence of Ge composition, SiGe Heterojunction Bipolar Transistors have better thermal stability compared with homojunction bipolar transistors under the same operating condition which will be beneficial to decrease the emitter ballast resistance of HBT and improve the performance of transistor. And the greater Ge composition is, the more stable the HBT is.
{"title":"The effect of bandgap engineering on IC-VBE fly-back characteristic of power SiGe heterojunction bipolar transistor","authors":"Chen Liang, Zhang Wan-rong, Jin Dong-yue, Ding Chun-bao, Zhang Yu-jie, Lu Zhi-yi","doi":"10.1109/EDSSC.2011.6117589","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117589","url":null,"abstract":"The effect of bandgap engineering on IC-VBE flyback characteristic of power SiGe heterojunction bipolar transistor is studied through theoretical analysis, computer simulations, and experimental measurements. It is found that because of the existence of Ge composition, SiGe Heterojunction Bipolar Transistors have better thermal stability compared with homojunction bipolar transistors under the same operating condition which will be beneficial to decrease the emitter ballast resistance of HBT and improve the performance of transistor. And the greater Ge composition is, the more stable the HBT is.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"73 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86816770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117615
Bin Lu, Jun Luo, Ruifeng Yue, Yan Wang
In recent years, WPAN (Wireless Personal Area Network) based on 60-GHz wireless communications has been highlighted in academia and the field of industry. At present, we are developing a 60-GHz CMOS transceiver prototype which includes a phased array. It is expected to be used for short range (5 meters) communication with several Gbps. This paper centers on the study of antennas in the transceiver. The antenna elements and arrays are designed and manufactured. First, the background of 60-GHz wireless communications is briefly introduced. After a detailed discussion, we decided to choose the antenna-in-package (AiP) solution and the Yagi antenna as elements, which based on the substrate of Scott glass. The phase array consists of two or four Yagi antenna elements. By simulation using Ansoft HFSS, the resulting gain of 4-elements array is 13.85dBi. A bandwidth of 8.2GHz and the efficiency of 95.4% are also obtained from the simulation.
{"title":"A Yagi antenna array for 60-GHz WPAN","authors":"Bin Lu, Jun Luo, Ruifeng Yue, Yan Wang","doi":"10.1109/EDSSC.2011.6117615","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117615","url":null,"abstract":"In recent years, WPAN (Wireless Personal Area Network) based on 60-GHz wireless communications has been highlighted in academia and the field of industry. At present, we are developing a 60-GHz CMOS transceiver prototype which includes a phased array. It is expected to be used for short range (5 meters) communication with several Gbps. This paper centers on the study of antennas in the transceiver. The antenna elements and arrays are designed and manufactured. First, the background of 60-GHz wireless communications is briefly introduced. After a detailed discussion, we decided to choose the antenna-in-package (AiP) solution and the Yagi antenna as elements, which based on the substrate of Scott glass. The phase array consists of two or four Yagi antenna elements. By simulation using Ansoft HFSS, the resulting gain of 4-elements array is 13.85dBi. A bandwidth of 8.2GHz and the efficiency of 95.4% are also obtained from the simulation.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82946951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117680
Xie Sheng, Feng Zhi-hong, Zhan Shi-lin, Liu Bo, Mao Lu-hong
A lattice-matched InAlN/GaN heterostructure was grown on sapphire substrate by using low-pressure metal organic chemical vapor deposition (MOCVD), and Hall effect measurements shown that the sheet charge density and electron mobility were 2.6×1013 cm−3 and 1210cm2/V•s, respectively. Large gate periphery (2.5mm) high electron mobility transistors (HEMTs) with a gate length of 250nm and a source-drain spacing of 4 µ m were fabricated. The measurement results revealed that the drain current density was 248mA/mm at a gate-source voltage of •1V with a maximum extrinsic transconductance of 271.1mS/mm, and the extrapolated threshold voltage was •1.95V. The measurement of the gate leakage current indicated that the tunneling current is likely the primary mechanism.
{"title":"DC characteristics of large gate periphery InAlN/GaN HEMT on sapphire substrate","authors":"Xie Sheng, Feng Zhi-hong, Zhan Shi-lin, Liu Bo, Mao Lu-hong","doi":"10.1109/EDSSC.2011.6117680","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117680","url":null,"abstract":"A lattice-matched InAlN/GaN heterostructure was grown on sapphire substrate by using low-pressure metal organic chemical vapor deposition (MOCVD), and Hall effect measurements shown that the sheet charge density and electron mobility were 2.6×1013 cm−3 and 1210cm2/V•s, respectively. Large gate periphery (2.5mm) high electron mobility transistors (HEMTs) with a gate length of 250nm and a source-drain spacing of 4 µ m were fabricated. The measurement results revealed that the drain current density was 248mA/mm at a gate-source voltage of •1V with a maximum extrinsic transconductance of 271.1mS/mm, and the extrapolated threshold voltage was •1.95V. The measurement of the gate leakage current indicated that the tunneling current is likely the primary mechanism.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"17 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82755385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117742
X. Tian, Szu-Ling Liu, Kuan-Han Chen, Y. Hao
This paper investigates the optimization method for two low-power circuit techniques in low-power LC-VCO designs: Transformer feedback and forward body-bias. In addition to theoretical analysis, a low-power, low-voltage X-band VCO using these two techniques has also been implemented in a standard 0.18µm CMOS technology. This VCO exhibits good FOM and of •191.4dBc/Hz while the core circuit draws a DC current of 2.73mA from 0.55V low supply voltage. The excellent performance can be compared with the best reported X-band CMOS VCOs.
{"title":"Investigation and optimization of low-power techniques in X-band CMOS LC-VCO design","authors":"X. Tian, Szu-Ling Liu, Kuan-Han Chen, Y. Hao","doi":"10.1109/EDSSC.2011.6117742","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117742","url":null,"abstract":"This paper investigates the optimization method for two low-power circuit techniques in low-power LC-VCO designs: Transformer feedback and forward body-bias. In addition to theoretical analysis, a low-power, low-voltage X-band VCO using these two techniques has also been implemented in a standard 0.18µm CMOS technology. This VCO exhibits good FOM and of •191.4dBc/Hz while the core circuit draws a DC current of 2.73mA from 0.55V low supply voltage. The excellent performance can be compared with the best reported X-band CMOS VCOs.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"2017 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82835231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117627
Huang Xiaozong, Zhang Jing, Gao Weiqi, Shi Jiangang, W. Hui
This paper presents a 16-bit 250ksps successive approximation register analog-to-digital converter (SAR-ADC) based on the charge-redistribution technique. The ADC contains a charge-redistribution DAC, a high precision internal voltage reference, a low offset comparator and a serial data interface. The split capacitor array was used to save the area of the chip and improve the speed and accuracy of the ADC. The electrical programming fuse (Efuse) which can be demonstrated after package without any extra pads or special equipments required is employed to optimize the performance of reference voltage and internal DAC. Measured at +5V supply and 250ksps, and consumes current of less than 17mA. The experimental measurement results indicate that an SNR of 88.8 dB, typical DNL of 0.6LSB and INL of 2.5LSB were achieved. The prototype was fabricated in a commercial 2P3M CMOS technology with the feature size of 0.6µm and occupies an active area of 4.2mm∗5.2 mm.
{"title":"A 16-bit, 250ksps successive approximation register ADC based on the charge-redistribution technique","authors":"Huang Xiaozong, Zhang Jing, Gao Weiqi, Shi Jiangang, W. Hui","doi":"10.1109/EDSSC.2011.6117627","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117627","url":null,"abstract":"This paper presents a 16-bit 250ksps successive approximation register analog-to-digital converter (SAR-ADC) based on the charge-redistribution technique. The ADC contains a charge-redistribution DAC, a high precision internal voltage reference, a low offset comparator and a serial data interface. The split capacitor array was used to save the area of the chip and improve the speed and accuracy of the ADC. The electrical programming fuse (Efuse) which can be demonstrated after package without any extra pads or special equipments required is employed to optimize the performance of reference voltage and internal DAC. Measured at +5V supply and 250ksps, and consumes current of less than 17mA. The experimental measurement results indicate that an SNR of 88.8 dB, typical DNL of 0.6LSB and INL of 2.5LSB were achieved. The prototype was fabricated in a commercial 2P3M CMOS technology with the feature size of 0.6µm and occupies an active area of 4.2mm∗5.2 mm.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"20 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91530123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117647
Longmei Nan, Z. Dai, Xuan S. Yang
By analyzing the operation characteristic of LFSRs in many public stream cipher algorithms and its bottleneck realized by general processor, several configurable specific instructions are proposed in this paper, which can neatly execute LFSR computing operation in parallel with high performance. The LFSR instructions brought out can sustain different operation data widths, different operating model. Instruction level parallelism based on VLIW system structure and instruction inner parallelism by operating several steps at one time are exploited too. The configurable instructions can be used as an important accelerated way in special processing for stream cipher.
{"title":"Design of configurable LFSR instructions targeted at stream cipher processing","authors":"Longmei Nan, Z. Dai, Xuan S. Yang","doi":"10.1109/EDSSC.2011.6117647","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117647","url":null,"abstract":"By analyzing the operation characteristic of LFSRs in many public stream cipher algorithms and its bottleneck realized by general processor, several configurable specific instructions are proposed in this paper, which can neatly execute LFSR computing operation in parallel with high performance. The LFSR instructions brought out can sustain different operation data widths, different operating model. Instruction level parallelism based on VLIW system structure and instruction inner parallelism by operating several steps at one time are exploited too. The configurable instructions can be used as an important accelerated way in special processing for stream cipher.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"146 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86646311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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