Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117706
Weiyang Liu, N. Wu
A novel parallel random number generator (RNG) based on two dimensions feedback shift register (2-DFSR), genetic algorithm (GA) and cellular automaton (CA) algorithms is proposed for wireless medical security applications. The measurement results demonstrated that the RNG can successfully pass the NIST 800-22 statistical test suite. The highest bit rate is 16 Mbps. The typical power consumption is 61.81 µW. Its energy efficiency is 3.86 pJ/bit.
{"title":"A novel parallel random number generator for wireless medical security applications","authors":"Weiyang Liu, N. Wu","doi":"10.1109/EDSSC.2011.6117706","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117706","url":null,"abstract":"A novel parallel random number generator (RNG) based on two dimensions feedback shift register (2-DFSR), genetic algorithm (GA) and cellular automaton (CA) algorithms is proposed for wireless medical security applications. The measurement results demonstrated that the RNG can successfully pass the NIST 800-22 statistical test suite. The highest bit rate is 16 Mbps. The typical power consumption is 61.81 µW. Its energy efficiency is 3.86 pJ/bit.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"29 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80161309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117697
T. Yan, X. Shen, P. Jiang, J. J. Zhou
A high linear fully differential RF CMOS amplifier covering UHF band is presented in this paper. A novel structure with both NMOS and PMOS differential pairs is proposed to cancel IM3 induced by 1st order derivative of transconductance (gm') and 2nd order derivative of transconductance (gm"). With appropriate DC operating points and aspect ratios, the RF CMOS amplifier achieves 12.5dB noise figure (NF), 10.5dB voltage gain and 17.5dBm input third order intercept point (IIP3) with total current consumption of 2mA from 1.8V voltage supply. The proposed amplifier is designed in TSMC 0.18µm CMOS process.
{"title":"A 17.5dBm IIP3 high linear fully differential RF CMOS amplifier","authors":"T. Yan, X. Shen, P. Jiang, J. J. Zhou","doi":"10.1109/EDSSC.2011.6117697","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117697","url":null,"abstract":"A high linear fully differential RF CMOS amplifier covering UHF band is presented in this paper. A novel structure with both NMOS and PMOS differential pairs is proposed to cancel IM3 induced by 1st order derivative of transconductance (gm') and 2nd order derivative of transconductance (gm\"). With appropriate DC operating points and aspect ratios, the RF CMOS amplifier achieves 12.5dB noise figure (NF), 10.5dB voltage gain and 17.5dBm input third order intercept point (IIP3) with total current consumption of 2mA from 1.8V voltage supply. The proposed amplifier is designed in TSMC 0.18µm CMOS process.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74449200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117630
Jiangtao Xu, C. Saavedra, Guican Chen
In this paper, noise analysis for a low noise transconductance amplifier (LNTA) is performed. LNTA becomes popular and necessary as the high linearity requirement and low supply voltage trend make the RF front-end design go into current domain. Common-gate common-source (CG-CS) topology is examined for noise analysis. Via theoretical analysis and specific equations derived, this paper not only studies how to arrange the topology and how to choose the design parameters, but also discusses the tradeoffs existing in LNTA design between noise figure, input matching and linearity.
{"title":"Noise analysis of the CG-CS low noise transconductance amplifier","authors":"Jiangtao Xu, C. Saavedra, Guican Chen","doi":"10.1109/EDSSC.2011.6117630","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117630","url":null,"abstract":"In this paper, noise analysis for a low noise transconductance amplifier (LNTA) is performed. LNTA becomes popular and necessary as the high linearity requirement and low supply voltage trend make the RF front-end design go into current domain. Common-gate common-source (CG-CS) topology is examined for noise analysis. Via theoretical analysis and specific equations derived, this paper not only studies how to arrange the topology and how to choose the design parameters, but also discusses the tradeoffs existing in LNTA design between noise figure, input matching and linearity.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90345357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117633
X. B. Li, M. Zhao, Z. H. Wu, B. Li
Mixer is an essential component for a communication system. Kinds of resolutions aiming at the improvement of mixer performance have been studied so far. In this paper, a fully differential structure is introduced and used in the design of a mixer with high linearity in a 0.18 µm CMOS RF process. Simulation results show that the input referred PldB (IPldB)of the mixer is 2.9 dBm, the input referred IP3 (IIP3) is 16 dBm and the power gain is 0.4 dB with a power consumption of 7.2 mW.
{"title":"A high-linearity fully-differential mixer","authors":"X. B. Li, M. Zhao, Z. H. Wu, B. Li","doi":"10.1109/EDSSC.2011.6117633","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117633","url":null,"abstract":"Mixer is an essential component for a communication system. Kinds of resolutions aiming at the improvement of mixer performance have been studied so far. In this paper, a fully differential structure is introduced and used in the design of a mixer with high linearity in a 0.18 µm CMOS RF process. Simulation results show that the input referred PldB (IPldB)of the mixer is 2.9 dBm, the input referred IP3 (IIP3) is 16 dBm and the power gain is 0.4 dB with a power consumption of 7.2 mW.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"73 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76676800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117657
L. Qian, X. Huang, P. Lai
In this work, the effects of fluorine incorporation by using plasma on the electrical properties of Si MOS capacitor with La2O3 gate dielectric are investigated. From the capacitance-voltage (C-V) curve and gate leakage current, it is demonstrated that the F-plasma treatment can effectively suppress the growth of interfacial layer, and thus improve the electrical properties of the device in terms of accumulation capacitance, interface-state density and breakdown voltage.
{"title":"Effects of fluorine incorporation on the electrical properties of silicon MOS capacitor with La2O3 gate dielectric","authors":"L. Qian, X. Huang, P. Lai","doi":"10.1109/EDSSC.2011.6117657","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117657","url":null,"abstract":"In this work, the effects of fluorine incorporation by using plasma on the electrical properties of Si MOS capacitor with La2O3 gate dielectric are investigated. From the capacitance-voltage (C-V) curve and gate leakage current, it is demonstrated that the F-plasma treatment can effectively suppress the growth of interfacial layer, and thus improve the electrical properties of the device in terms of accumulation capacitance, interface-state density and breakdown voltage.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"44 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76767318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117702
W. Jigang, Xiaogang Han
Reconfiguring a VLSI array with faults is to construct a maximum logical sub-array (target array). A large target array implies a good harvest of the corresponding reconfiguration algorithm. Thus, a tight upper bound of the harvest can be directly used to evaluate the performance of the reconfiguration algorithm. This paper presents a new approach to calculate the upper bound of the harvest for the VLSI arrays with clustered faults. Simulation results show that the upper bound is reduced up to 20% on 256 × 256 array with clustered faults.
{"title":"New upper bound of target array for reconfigurable VLSI arrays","authors":"W. Jigang, Xiaogang Han","doi":"10.1109/EDSSC.2011.6117702","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117702","url":null,"abstract":"Reconfiguring a VLSI array with faults is to construct a maximum logical sub-array (target array). A large target array implies a good harvest of the corresponding reconfiguration algorithm. Thus, a tight upper bound of the harvest can be directly used to evaluate the performance of the reconfiguration algorithm. This paper presents a new approach to calculate the upper bound of the harvest for the VLSI arrays with clustered faults. Simulation results show that the upper bound is reduced up to 20% on 256 × 256 array with clustered faults.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85423551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D device simulation in this paper. The proposed flash memory cell shows improved program/erase speed, increased programming efficiency and super punch-through immunity as the cell gate length scaled from 180nm to 45nm, which indicates that this new structure is with strong scalability. Furthermore, cell design consideration i.e. ambipolar suppression for the TFET-based flash cell are also investigated and discussed.
{"title":"A novel flash memory cell and design optimization for high density and low power application","authors":"Huiwei Wu, Shiqiang Qin, Yimao Cai, Poren Tang, Zhan Zhan, Qianqian Huang, Ru Huang","doi":"10.1109/EDSSC.2011.6117733","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117733","url":null,"abstract":"A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D device simulation in this paper. The proposed flash memory cell shows improved program/erase speed, increased programming efficiency and super punch-through immunity as the cell gate length scaled from 180nm to 45nm, which indicates that this new structure is with strong scalability. Furthermore, cell design consideration i.e. ambipolar suppression for the TFET-based flash cell are also investigated and discussed.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"56 6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85433680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117738
Hongyi Li, Y. Wang, S. Jia, Xing Zhang
Using an auxiliary quantizer before unity-STF SDM, a novel 3rd-order dual-quantizer SDM with extended dynamic range is presented. With hybrid distributed feedback & feedforward paths and an internal feedforward path, a novel low-distortion 3rd-order SDM with simple adder before quantizer is proposed as the unity-STF SDM. Simulations show their perfect immunity to non-idealities.
{"title":"Novel single-loop sigma-delta modulator with extended dynamic range","authors":"Hongyi Li, Y. Wang, S. Jia, Xing Zhang","doi":"10.1109/EDSSC.2011.6117738","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117738","url":null,"abstract":"Using an auxiliary quantizer before unity-STF SDM, a novel 3rd-order dual-quantizer SDM with extended dynamic range is presented. With hybrid distributed feedback & feedforward paths and an internal feedforward path, a novel low-distortion 3rd-order SDM with simple adder before quantizer is proposed as the unity-STF SDM. Simulations show their perfect immunity to non-idealities.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88612465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A curvature-compensation bandgap voltage reference employing current proportional to absolute temperature (PTAT) is presented in this paper. In-package trim for the initial accuracy and temperature coefficient is used to get better performance without extra cost. And the principles and realization of the programmable electrical fuse are discussed in detail, which can be widely used. With the curvature compensation method, simulation temperature coefficient of 15ppm/°C over a wide range of •55°C to +125°C and high initial accuracy of better than 0.1% are achieved. Additionally, this bandgap reference has been embedded in a 16-bit ADC implementation.
{"title":"A curvature-compensation bandgap voltage reference with programmable trimming technique","authors":"Luncai Liu, Xiaozong Huang, Jing Zhang, Wengang Huang","doi":"10.1109/EDSSC.2011.6117744","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117744","url":null,"abstract":"A curvature-compensation bandgap voltage reference employing current proportional to absolute temperature (PTAT) is presented in this paper. In-package trim for the initial accuracy and temperature coefficient is used to get better performance without extra cost. And the principles and realization of the programmable electrical fuse are discussed in detail, which can be widely used. With the curvature compensation method, simulation temperature coefficient of 15ppm/°C over a wide range of •55°C to +125°C and high initial accuracy of better than 0.1% are achieved. Additionally, this bandgap reference has been embedded in a 16-bit ADC implementation.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"46 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87686080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117619
To-Po Wang, Shih-Hua Chiang
A 3.1–10.6 GHz ultra-wideband (UWB) 0.18-µm CMOS low-noise amplifier using micromachined inductors is proposed in this paper. This LNA consists of two stages, the first stage is the cascode topology with shunt-series feedback for bandwidth enhancement, and the second stage is the common-source topology with shunt-series feedback for further bandwidth extended. To improve LNA performance in terms of gain and NF, the CMOS compatible micromachined inductors are adopted in this work. By using these techniques, this LNA achieves the 3-dB bandwidth from 3.1–10.6 GHz, and the peak gain is 19 dB. The dc power consumption and lowest noise figure of this LNA is 14.3 mW and 2.4 dB, respectively.
{"title":"A 3.1–10.6 GHz ultra-wideband 0.18-µm CMOS low-noise amplifier with micromachined inductors","authors":"To-Po Wang, Shih-Hua Chiang","doi":"10.1109/EDSSC.2011.6117619","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117619","url":null,"abstract":"A 3.1–10.6 GHz ultra-wideband (UWB) 0.18-µm CMOS low-noise amplifier using micromachined inductors is proposed in this paper. This LNA consists of two stages, the first stage is the cascode topology with shunt-series feedback for bandwidth enhancement, and the second stage is the common-source topology with shunt-series feedback for further bandwidth extended. To improve LNA performance in terms of gain and NF, the CMOS compatible micromachined inductors are adopted in this work. By using these techniques, this LNA achieves the 3-dB bandwidth from 3.1–10.6 GHz, and the peak gain is 19 dB. The dc power consumption and lowest noise figure of this LNA is 14.3 mW and 2.4 dB, respectively.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"65 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83537996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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