Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117692
Xiao Han, Jie Jiang, Bin Zhou, Jia Sun, Wei Dou, Huixuan Liu, Qing Wan
We fabricated indium-zinc-oxide (IZO) thin film transistors (TFT) gated by chitosan (CS) on ITO/glass substrate. Chitosan is demonstrated to be a new kind of solution-processed organic polymer electrolyte, which has nice film-forming characteristic. The chitosan thin film shows a large specific gate capacitance of 8.06 (µF/cm2 due to the mobile-ions induced electric-double-layer effect. These devices exhibited a good performance with a small subthreshold swing of 0.3 V/dec, a large on-off current ratio of ∼106, a high field-effect mobility of 1.24 cm2V−1 s−1 and a low operate voltage of 2 V. The solution-processed chitosan-based TFTs may have many potential applications for large-area, mechanically flexible, lightweight, and inexpensive electronic logic circuits.
{"title":"Low-voltage indium-zinc-oxide thin film transistors gated by solution-processed chitosan-based proton conductors","authors":"Xiao Han, Jie Jiang, Bin Zhou, Jia Sun, Wei Dou, Huixuan Liu, Qing Wan","doi":"10.1109/EDSSC.2011.6117692","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117692","url":null,"abstract":"We fabricated indium-zinc-oxide (IZO) thin film transistors (TFT) gated by chitosan (CS) on ITO/glass substrate. Chitosan is demonstrated to be a new kind of solution-processed organic polymer electrolyte, which has nice film-forming characteristic. The chitosan thin film shows a large specific gate capacitance of 8.06 (µF/cm2 due to the mobile-ions induced electric-double-layer effect. These devices exhibited a good performance with a small subthreshold swing of 0.3 V/dec, a large on-off current ratio of ∼106, a high field-effect mobility of 1.24 cm2V−1 s−1 and a low operate voltage of 2 V. The solution-processed chitosan-based TFTs may have many potential applications for large-area, mechanically flexible, lightweight, and inexpensive electronic logic circuits.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"73 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86609928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117653
Li Miao, Yang Xiaohui, D. Zibin, Chen Tao, He Liangsheng
With the characteristics of computing compression, Elliptic Curve Cryptography (ECC) can be exploited parallel processing function by adopting VLIW architecture. Based on VLIW, the micro-architecture composition, pipeline structure and clustered architecture of ECC processor have been researched, and a microarchitecture design method for ECC processor has been presented. Using FPGA and under 0.18µm CMOS technology, a prototype has also been implemented. The results prove that the proposed micro-architecture for ECC processor can not only guarantee high flexibility for arbitrary ECC algorithms, but also achieve high performance.
{"title":"Research and implementation of micro-architecture for Elliptic Curve Cryptography processor","authors":"Li Miao, Yang Xiaohui, D. Zibin, Chen Tao, He Liangsheng","doi":"10.1109/EDSSC.2011.6117653","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117653","url":null,"abstract":"With the characteristics of computing compression, Elliptic Curve Cryptography (ECC) can be exploited parallel processing function by adopting VLIW architecture. Based on VLIW, the micro-architecture composition, pipeline structure and clustered architecture of ECC processor have been researched, and a microarchitecture design method for ECC processor has been presented. Using FPGA and under 0.18µm CMOS technology, a prototype has also been implemented. The results prove that the proposed micro-architecture for ECC processor can not only guarantee high flexibility for arbitrary ECC algorithms, but also achieve high performance.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"69 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87416105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117691
Mei Jiang, Xing Zhang, Shan Liu, Hongqiang Zong, Fanyu Meng, Xin'an Wang
In this paper, a double-balanced folded-switching mixer with ultra low current consumption for DCR of wireless communication applications is presented. This mixer is with improved RF Gm stage adopting the current-reuse and ac-coupling technologies. With the TSMC 0.18-µm 1- Poly 6-Metal RF CMOS process, the proposed mixer topology can achieve 0.85dBm IIP3, 4.8dB conversion gain under 1.2V supply voltage with 1.2mA current consumption. When the supply voltage decreases to 1V, the mixer can achieve •0.53dBm IIP3, 1 dB conversion gain with 1.3mA current consumption.
{"title":"Low voltage, low power, downconversion folded-switching mixer with current-reuse technology","authors":"Mei Jiang, Xing Zhang, Shan Liu, Hongqiang Zong, Fanyu Meng, Xin'an Wang","doi":"10.1109/EDSSC.2011.6117691","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117691","url":null,"abstract":"In this paper, a double-balanced folded-switching mixer with ultra low current consumption for DCR of wireless communication applications is presented. This mixer is with improved RF Gm stage adopting the current-reuse and ac-coupling technologies. With the TSMC 0.18-µm 1- Poly 6-Metal RF CMOS process, the proposed mixer topology can achieve 0.85dBm IIP3, 4.8dB conversion gain under 1.2V supply voltage with 1.2mA current consumption. When the supply voltage decreases to 1V, the mixer can achieve •0.53dBm IIP3, 1 dB conversion gain with 1.3mA current consumption.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"7 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76020883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117666
Lixia Zheng, Jin Wu, Xia Zhao
A CMOS voltage reference based on subthreshold operation is proposed. The current mirror mismatch error resulting from the channel length modulation effect is improved by using a self-cascode operational amplifer. The reference generates a constant reference voltage of 639 mV at supply voltage of 1.2V with power consumption of 18uW at room temperature fabricated in CSMC 0.18um CMOS technology. It achieves a temperature coefficient of 8.4ppm/°C for the temperature range from •20 °C to 120 °C
{"title":"A low voltage 8.4 ppm/°C voltage reference based on subthreshold MOSFETs","authors":"Lixia Zheng, Jin Wu, Xia Zhao","doi":"10.1109/EDSSC.2011.6117666","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117666","url":null,"abstract":"A CMOS voltage reference based on subthreshold operation is proposed. The current mirror mismatch error resulting from the channel length modulation effect is improved by using a self-cascode operational amplifer. The reference generates a constant reference voltage of 639 mV at supply voltage of 1.2V with power consumption of 18uW at room temperature fabricated in CSMC 0.18um CMOS technology. It achieves a temperature coefficient of 8.4ppm/°C for the temperature range from •20 °C to 120 °C","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81075750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117575
Yiqi Wang, Ying Li, F. Zhao, Mengxin Liu, Zhengsheng Han
A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35µm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.
{"title":"A radiation hardened SRAM cell design in PD-SOI CMOS technology","authors":"Yiqi Wang, Ying Li, F. Zhao, Mengxin Liu, Zhengsheng Han","doi":"10.1109/EDSSC.2011.6117575","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117575","url":null,"abstract":"A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35µm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"96 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77327611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117674
Wei Zhang, Shiqiang Wu, Yujing Feng, Yanyan Liu
This paper presents a simple yet practical self-adaptive synchronizing algorithm for ultra-high frequency radio frequency identification (UHF RFID) tags. The proposed algorithm is compatible with the ISO/IEC 18000-6 Type B protocol. It can generate proper sample points along the command, and is less dependent on the stability of the on-chip clock. The behavior model for the proposed algorithm has been created with Verilog HDL and verified. Based on Chartered 0.35µm 3.3V process, UHF RFID tag chips have been implemented successfully.
提出了一种简单实用的超高频射频识别(UHF RFID)标签自适应同步算法。该算法兼容ISO/IEC 18000-6 Type B协议。它可以沿着指令生成适当的采样点，并且对片上时钟的稳定性依赖较小。用Verilog HDL建立了该算法的行为模型并进行了验证。基于Chartered 0.35µm 3.3V工艺的超高频RFID标签芯片已成功实现。
{"title":"A self-adaptive synchronizing algorithm for UHF RFID tag","authors":"Wei Zhang, Shiqiang Wu, Yujing Feng, Yanyan Liu","doi":"10.1109/EDSSC.2011.6117674","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117674","url":null,"abstract":"This paper presents a simple yet practical self-adaptive synchronizing algorithm for ultra-high frequency radio frequency identification (UHF RFID) tags. The proposed algorithm is compatible with the ISO/IEC 18000-6 Type B protocol. It can generate proper sample points along the command, and is less dependent on the stability of the on-chip clock. The behavior model for the proposed algorithm has been created with Verilog HDL and verified. Based on Chartered 0.35µm 3.3V process, UHF RFID tag chips have been implemented successfully.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"381 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77340897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117661
Chen Yan, Mao Luhong, Zhang Shilin, Xie Sheng, Xiao Xindong, Tian Ye, Yang Chunpu
An optical receiver circuit with automatic gain control (AGC) for radio-over-fiber (RoF) system is presented. The AGC optical receiver is designed on the standard 0.18µm CMOS technology. The proposed circuit uses a differential variable gain amplifier (VGA), implemented by a Gilbert cell and provides an exponential function circuit for the dB linearity of the gain voltage. A large dynamic range of the receiver is from 13dB to 75dB. The AGC loop bandwidth is 3.3GHz, with a power consumption of 101mW and a low noise current of 1.45µA, and the eye diagram of the receiver is also good.
{"title":"An optical receiver with automatic gain control for radio-over-fiber system","authors":"Chen Yan, Mao Luhong, Zhang Shilin, Xie Sheng, Xiao Xindong, Tian Ye, Yang Chunpu","doi":"10.1109/EDSSC.2011.6117661","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117661","url":null,"abstract":"An optical receiver circuit with automatic gain control (AGC) for radio-over-fiber (RoF) system is presented. The AGC optical receiver is designed on the standard 0.18µm CMOS technology. The proposed circuit uses a differential variable gain amplifier (VGA), implemented by a Gilbert cell and provides an exponential function circuit for the dB linearity of the gain voltage. A large dynamic range of the receiver is from 13dB to 75dB. The AGC loop bandwidth is 3.3GHz, with a power consumption of 101mW and a low noise current of 1.45µA, and the eye diagram of the receiver is also good.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"46 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87359526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117563
A. Matsuzawa, K. Okada
A 60 GHz direct conversion transceiver was developed using 65 nm CMOS and demonstrates 7 Gbps using 16 QAM. A quadrature VCO attained very low phase noise of •94 dBc/Hz @1 MHz.
{"title":"60GHz direct conversion CMOS transceiver design","authors":"A. Matsuzawa, K. Okada","doi":"10.1109/EDSSC.2011.6117563","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117563","url":null,"abstract":"A 60 GHz direct conversion transceiver was developed using 65 nm CMOS and demonstrates 7 Gbps using 16 QAM. A quadrature VCO attained very low phase noise of •94 dBc/Hz @1 MHz.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"26 3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90424386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117709
To-Po Wang
A low-power low-phase-noise wide-tuning-range 60-GHz push-push voltage-controlled oscillator (VCO) is presented in this paper. To eliminate the required λ/4 micropstrip or coplanar waveguide (CPW) line of the conventional push-push VCO, the enhanced second-harmonic output signal (2fo) is extracted at middle of the varactors, leading to a minimized chip area. By employing MOS varactors deposited between the drain and source terminations of the cross-coupled pair, the tuning range is effectively boosted, and the phase noise is improved. According to these techniques, the fabricated 0.18-µm CMOS VCO exhibits a measured 8.3% tuning range. Operating at 1.2-V supply voltage, the VCO dissipates 7.7-mW dc power excluding the testing buffers. The measured phase noise at 1-MHz offset from 61.5-GHz oscillation frequency is •91.5 dBc/Hz. Compared to recently published 60-GHz VCOs in 0.13-µm CMOS, this work can simultaneously achieve low phase noise, wide tuning range, and low dc power, resulting in the better figure of merit (FOM) and figure of merit considering the tuning range (FOMT).
{"title":"A low-power low-phase-noise wide-tuning-range 60-GHz voltage-controlled oscillator in 0.18-µm CMOS","authors":"To-Po Wang","doi":"10.1109/EDSSC.2011.6117709","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117709","url":null,"abstract":"A low-power low-phase-noise wide-tuning-range 60-GHz push-push voltage-controlled oscillator (VCO) is presented in this paper. To eliminate the required λ/4 micropstrip or coplanar waveguide (CPW) line of the conventional push-push VCO, the enhanced second-harmonic output signal (2fo) is extracted at middle of the varactors, leading to a minimized chip area. By employing MOS varactors deposited between the drain and source terminations of the cross-coupled pair, the tuning range is effectively boosted, and the phase noise is improved. According to these techniques, the fabricated 0.18-µm CMOS VCO exhibits a measured 8.3% tuning range. Operating at 1.2-V supply voltage, the VCO dissipates 7.7-mW dc power excluding the testing buffers. The measured phase noise at 1-MHz offset from 61.5-GHz oscillation frequency is •91.5 dBc/Hz. Compared to recently published 60-GHz VCOs in 0.13-µm CMOS, this work can simultaneously achieve low phase noise, wide tuning range, and low dc power, resulting in the better figure of merit (FOM) and figure of merit considering the tuning range (FOMT).","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"19 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88922178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117578
Xinming Duan, Jigang Wu
Fault tolerance is one of the most important issues for the design of cost-effective and high performance interconnection networks. In this paper, a new fault tolerance routing algorithm for n-dimensional meshes is presented. The presented algorithm is based on a planer fault model which only disables minimum fault-free nodes to form rectangular fault regions. The algorithm uses three virtual channels per physical channel and only employs a very simple deadlock avoidance scheme. In spit the variety fault regions in n-dimensional mesh, the presented algorithm is always connected as long as fault regions do not disconnect the network.
{"title":"A deadlock-free fault-tolerant routing algorithm for N-dimesional meshes","authors":"Xinming Duan, Jigang Wu","doi":"10.1109/EDSSC.2011.6117578","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117578","url":null,"abstract":"Fault tolerance is one of the most important issues for the design of cost-effective and high performance interconnection networks. In this paper, a new fault tolerance routing algorithm for n-dimensional meshes is presented. The presented algorithm is based on a planer fault model which only disables minimum fault-free nodes to form rectangular fault regions. The algorithm uses three virtual channels per physical channel and only employs a very simple deadlock avoidance scheme. In spit the variety fault regions in n-dimensional mesh, the presented algorithm is always connected as long as fault regions do not disconnect the network.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89034353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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