Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117645
Yisheng Wang, Kaixue Ma, N. Mahalingam, K. Yeo
A design and optimization flow for digital delta-sigma fractional-N frequency divider of Phase Lock Loop (PLL) is introduced in this paper. The low power design is used for the 60 GHz RF transceiver using 0.18um SiGe BiCMOS technology. With full consideration of the low complexity and unconditional stability, MASH111 delta-sigma modulator is chosen as control module for the PLL. The input frequency is 6.48Ghz, and the integer division rate is from 36 to 64 with step of 2.
{"title":"A delta-sigma fractional-N frequency divider for a Phase Lock Loop in 60GHz transceiver","authors":"Yisheng Wang, Kaixue Ma, N. Mahalingam, K. Yeo","doi":"10.1109/EDSSC.2011.6117645","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117645","url":null,"abstract":"A design and optimization flow for digital delta-sigma fractional-N frequency divider of Phase Lock Loop (PLL) is introduced in this paper. The low power design is used for the 60 GHz RF transceiver using 0.18um SiGe BiCMOS technology. With full consideration of the low complexity and unconditional stability, MASH111 delta-sigma modulator is chosen as control module for the PLL. The input frequency is 6.48Ghz, and the integer division rate is from 36 to 64 with step of 2.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"42 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90752736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117658
Gong Xin, D. Zibin, Li Wei, Feng Lulu
NAND Flash is widely used in modern digital products and it has become a trend to integrate NAND Flash controller into SoC. This paper discussed the implementation scheme of the NAND Flash controller in detial, including the design of state machine, ECC module and so on. In order to improve the data access speed of NAND Flash Controller, this paper proposed two technologies which increase little area but improve the performance of the controller effectively. The test results based on FPGA showed that this design had high practical value. Based on SMIC 0.18µm standard CMOS technology, this design can work at the frequency of 121MHz.
{"title":"Design and implementation of a NAND Flash controller in SoC","authors":"Gong Xin, D. Zibin, Li Wei, Feng Lulu","doi":"10.1109/EDSSC.2011.6117658","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117658","url":null,"abstract":"NAND Flash is widely used in modern digital products and it has become a trend to integrate NAND Flash controller into SoC. This paper discussed the implementation scheme of the NAND Flash controller in detial, including the design of state machine, ECC module and so on. In order to improve the data access speed of NAND Flash Controller, this paper proposed two technologies which increase little area but improve the performance of the controller effectively. The test results based on FPGA showed that this design had high practical value. Based on SMIC 0.18µm standard CMOS technology, this design can work at the frequency of 121MHz.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"31 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80645382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117667
L. Xuemei, Wang Zhigong, Wang Keping
The implementation of a high-speed wide band low phase noise multi-mode frequency divider (MMFD) for a DRM/DAB frequency synthesizer is described. According to the characteristics of each part, novel SCL and CMOS static flip-flop DFF are applied. Realized in a 0.18-µm RF CMOS technology, the core area of the MMFD is 745 µm×705 µm, including buffer and pads. Post simulated results show that its operation frequency ranging is from 2.2GHz to 3.1 GHz, and phase noise of the MMFD is •134dBc/Hz at 10 kHz offset. The maximum core power consumption is 24.6 mA at a 1.8V power supply.
{"title":"A high speed wide band low phase noise multi-mode frequency divider for DRM/DAB/AM/FM frequency synthesizer","authors":"L. Xuemei, Wang Zhigong, Wang Keping","doi":"10.1109/EDSSC.2011.6117667","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117667","url":null,"abstract":"The implementation of a high-speed wide band low phase noise multi-mode frequency divider (MMFD) for a DRM/DAB frequency synthesizer is described. According to the characteristics of each part, novel SCL and CMOS static flip-flop DFF are applied. Realized in a 0.18-µm RF CMOS technology, the core area of the MMFD is 745 µm×705 µm, including buffer and pads. Post simulated results show that its operation frequency ranging is from 2.2GHz to 3.1 GHz, and phase noise of the MMFD is •134dBc/Hz at 10 kHz offset. The maximum core power consumption is 24.6 mA at a 1.8V power supply.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"8 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81797736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117631
Yanzhao Ma, Hongyi Wang, Guican Chen
A step-up/step-down DC-DC converter with high efficiency and small output voltage ripple is proposed in this paper. To reduce the switching loss and improve the efficiency, the converter operates in buck or boost mode when the input voltage is much higher or lower than the output voltage. However, a large output voltage ripple appears at the boundary of buck mode and boost mode due to the speed limitation of standard analog circuit. A transition mode using a digital dither technique is adopted and the output voltage ripple is reduced when the input voltage is close to the output voltage. Furthermore, the average inductor current is also reduced in the proposed transition mode. The converter has been designed with a standard a 0.5 µm CMOS process. The peak efficiency is 96% and the output voltage ripple is reduced to less than 10 mV in the transition mode.
{"title":"A digital dither controlled step-up/step-down DC-DC converter with smooth transition","authors":"Yanzhao Ma, Hongyi Wang, Guican Chen","doi":"10.1109/EDSSC.2011.6117631","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117631","url":null,"abstract":"A step-up/step-down DC-DC converter with high efficiency and small output voltage ripple is proposed in this paper. To reduce the switching loss and improve the efficiency, the converter operates in buck or boost mode when the input voltage is much higher or lower than the output voltage. However, a large output voltage ripple appears at the boundary of buck mode and boost mode due to the speed limitation of standard analog circuit. A transition mode using a digital dither technique is adopted and the output voltage ripple is reduced when the input voltage is close to the output voltage. Furthermore, the average inductor current is also reduced in the proposed transition mode. The converter has been designed with a standard a 0.5 µm CMOS process. The peak efficiency is 96% and the output voltage ripple is reduced to less than 10 mV in the transition mode.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"94 6 Pt 1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89494982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, TaN bottom electrode thermal sensing resistor for MEMs based bolometer was fabricated by 200mm Cu-BEOL compatible process. Thermal sensing material was B-doped alpha-Si deposited by PECVD in-situ doping process. PVD TaN film was used as bottom electrode. Dedicated process on modified tool was introduced to achieve a good contact between TaN and sensing material. There are both CVD and ETCH chamber installed on this modified tool. Wafer with bottom electrode pattern was pre-cleaned firstly by low-power Ar/CF4 gas to remove oxide and possible surface residue on TaN in etch chamber. Then the wafer was transferred to CVD chamber through transfer chamber in vacuum condition. With vacuum transfer condition and tightly Q-time control, ohmic contact can be achieved for the TaN bottom electrode and B-doped alpha-Si. Through the IV curve and TCR data it can be seen that bottom electrode device can well meet the MEMs-based bolometer requirements.
{"title":"Design and fabrication of TaN bottom electrode thermal sensing resistor for MEMs based bolometer application","authors":"Xiaoxu Kang, Jiaqing Li, Chao Yuan, Shoumian Chen, Yuhang Zhao","doi":"10.1142/S0218126613400215","DOIUrl":"https://doi.org/10.1142/S0218126613400215","url":null,"abstract":"In this work, TaN bottom electrode thermal sensing resistor for MEMs based bolometer was fabricated by 200mm Cu-BEOL compatible process. Thermal sensing material was B-doped alpha-Si deposited by PECVD in-situ doping process. PVD TaN film was used as bottom electrode. Dedicated process on modified tool was introduced to achieve a good contact between TaN and sensing material. There are both CVD and ETCH chamber installed on this modified tool. Wafer with bottom electrode pattern was pre-cleaned firstly by low-power Ar/CF4 gas to remove oxide and possible surface residue on TaN in etch chamber. Then the wafer was transferred to CVD chamber through transfer chamber in vacuum condition. With vacuum transfer condition and tightly Q-time control, ohmic contact can be achieved for the TaN bottom electrode and B-doped alpha-Si. Through the IV curve and TCR data it can be seen that bottom electrode device can well meet the MEMs-based bolometer requirements.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"16 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88490104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117648
T. Feng, D. Xie, Yongyuan Zang, Xaio Wu, Yafeng Luo, T. Ren, M. Bosund, Shuo Li, V. Airaksinen, H. Lipsanen, S. Honkanen
Ferroelectric field effect transistor (FeFET) is a promising candidate in nonvolatile memory application due to its fast read/write speed, nondestructive readout, and low power consumption. Since the poor retention characteristic can be improved by introducing insulator buffer layers between gate layer and FET channel region, more and more attentions are devoted to the realization and optimization of this novel memory device [1]. Traditional ferroelectric materials, such as PZT [2, 3] and SBT [4] based FeFETs are extensively studied and reported in the past decades. Recently, Nd-doped Bismuth Titanate B3.15Nd0.85Ti3O12 (BNdT) with a large remnant polarization (2Pr=103µC/cm2) and outstanding fatigue endurance was reported by Chon et al. [5], and many ferroelectric applications are being processed based on this brand new ferroelectric material [6, 7]. In this letter, we fabricated a BNdT based FeFET for the first time. The fundamental structural and electrical properties are investigated correspondingly.
{"title":"Nd-doped Bismuth Titanate based ferroelectric field effect transistor: Design, fabrication, and optimization","authors":"T. Feng, D. Xie, Yongyuan Zang, Xaio Wu, Yafeng Luo, T. Ren, M. Bosund, Shuo Li, V. Airaksinen, H. Lipsanen, S. Honkanen","doi":"10.1109/EDSSC.2011.6117648","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117648","url":null,"abstract":"Ferroelectric field effect transistor (FeFET) is a promising candidate in nonvolatile memory application due to its fast read/write speed, nondestructive readout, and low power consumption. Since the poor retention characteristic can be improved by introducing insulator buffer layers between gate layer and FET channel region, more and more attentions are devoted to the realization and optimization of this novel memory device [1]. Traditional ferroelectric materials, such as PZT [2, 3] and SBT [4] based FeFETs are extensively studied and reported in the past decades. Recently, Nd-doped Bismuth Titanate B3.15Nd0.85Ti3O12 (BNdT) with a large remnant polarization (2Pr=103µC/cm2) and outstanding fatigue endurance was reported by Chon et al. [5], and many ferroelectric applications are being processed based on this brand new ferroelectric material [6, 7]. In this letter, we fabricated a BNdT based FeFET for the first time. The fundamental structural and electrical properties are investigated correspondingly.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"48 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72793726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117741
Xinguo Chen, Xiaofei Yang, Jieyun Wang, Weiwei Han
Chaotic system is sensitive to weak signals with the same frequency as the driving force, and is also immune to noise. Ever since Brow first proposed Duffing oscillator being used to detect weak signal[1], a great deal of research have been done in this field, including selection of the driving threshold value, impact of noise on phase orbit, identification of large-scale periodic state and chaotic state[2–4] and so on, but a few studies have been done about the effect of initial conditions on detection reliability of the chaotic system. The initial condition of Duffing oscillator selected by some researchers is random and uncertainty. This paper concluded from stimulation results that different initial conditions lead to different transitional process and different immunity to noise, and recommended a proper selection method of initial conditions and input time of weak signals with background noise, which can effectively improve the detection reliability of chaotic system.
{"title":"Reliability analysis of weak signal detection based on Duffing oscillator","authors":"Xinguo Chen, Xiaofei Yang, Jieyun Wang, Weiwei Han","doi":"10.1109/EDSSC.2011.6117741","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117741","url":null,"abstract":"Chaotic system is sensitive to weak signals with the same frequency as the driving force, and is also immune to noise. Ever since Brow first proposed Duffing oscillator being used to detect weak signal[1], a great deal of research have been done in this field, including selection of the driving threshold value, impact of noise on phase orbit, identification of large-scale periodic state and chaotic state[2–4] and so on, but a few studies have been done about the effect of initial conditions on detection reliability of the chaotic system. The initial condition of Duffing oscillator selected by some researchers is random and uncertainty. This paper concluded from stimulation results that different initial conditions lead to different transitional process and different immunity to noise, and recommended a proper selection method of initial conditions and input time of weak signals with background noise, which can effectively improve the detection reliability of chaotic system.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"240 2 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72801541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117724
Cen Gao, S. Yao, Jiangtao Xu, Jing Gao, Kaiming Nie
The noise of the current accumulator is analyzed. And a model of Time-Delay-Integration (TDI) CMOS image sensor is presented, which is used to analyze the noise performance. In this model, input signals are accumulated 4 times by the type of current and then converted to digital signals to accomplish the other accumulation by 32 times, i.e., 4×32 accumulation mode. The noise, which includes switch charge injection, sample noise and KT/C noise, is considered in this model. The major source of the noise and the relationship between noise and sample capacitance are evaluated through the model simulation. The results indicate that the total noise can be restrained by increasing sample capacitance. When the input signal is arranging from 0µA to 100µA, the accuracy of the current accumulator can be 11bits by using 1pF sample capacitor. And the SNR of the output signal can be increased by 20.38dB which is close to the ideal result.
{"title":"Analysis of noise of current accumulator in Time-Delay-Integration CMOS image sensor","authors":"Cen Gao, S. Yao, Jiangtao Xu, Jing Gao, Kaiming Nie","doi":"10.1109/EDSSC.2011.6117724","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117724","url":null,"abstract":"The noise of the current accumulator is analyzed. And a model of Time-Delay-Integration (TDI) CMOS image sensor is presented, which is used to analyze the noise performance. In this model, input signals are accumulated 4 times by the type of current and then converted to digital signals to accomplish the other accumulation by 32 times, i.e., 4×32 accumulation mode. The noise, which includes switch charge injection, sample noise and KT/C noise, is considered in this model. The major source of the noise and the relationship between noise and sample capacitance are evaluated through the model simulation. The results indicate that the total noise can be restrained by increasing sample capacitance. When the input signal is arranging from 0µA to 100µA, the accuracy of the current accumulator can be 11bits by using 1pF sample capacitor. And the SNR of the output signal can be increased by 20.38dB which is close to the ideal result.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"86 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75207413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117681
Xie Sheng, C. Zhiming, Yu Xin, Zhang Shilin, Li Xianjie, Chen Yan, Guo Weilian, Qi Lifang, Mao Luhong, Yu Jinlong
Dry etching of InP-based epitaxial structure was performed by using inductively coupled plasma (ICP) system with different chemistries. The surface topographies shown that the waveguide profiles etched using the Cl2/CH4/Ar recipe have better surface and sidewall quality than that of the Cl2/BCl3 chemistry. To verify the practical influence of ICP etching, InP/AlGaInAs multiple quantum wells microring lasers were fabricated, and the electrical and optical properties were compared. The experimental results revealed that the Cl2/CH4/Ar recipe is preferable to the fabrication of InP-based optoelectronic devices in our experimental system.
{"title":"Effect of ICP etching on InP-based multiple quantum wells microring lasers","authors":"Xie Sheng, C. Zhiming, Yu Xin, Zhang Shilin, Li Xianjie, Chen Yan, Guo Weilian, Qi Lifang, Mao Luhong, Yu Jinlong","doi":"10.1109/EDSSC.2011.6117681","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117681","url":null,"abstract":"Dry etching of InP-based epitaxial structure was performed by using inductively coupled plasma (ICP) system with different chemistries. The surface topographies shown that the waveguide profiles etched using the Cl2/CH4/Ar recipe have better surface and sidewall quality than that of the Cl2/BCl3 chemistry. To verify the practical influence of ICP etching, InP/AlGaInAs multiple quantum wells microring lasers were fabricated, and the electrical and optical properties were compared. The experimental results revealed that the Cl2/CH4/Ar recipe is preferable to the fabrication of InP-based optoelectronic devices in our experimental system.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"48 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77546197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117650
Yong-Qi Li, Lei Sun, Xiaoyan Liu, Yi Wang, Dedong Han
Bottom gate ZnO-TFTs are fabricated and the devices' characteristics are reported. Before contact patterning, ZnO films were annealed in high vacuum environment under lower temperatures compared with in forming gas treatments. The characteristics of the ZnO-TFTs which have been annealed, especially at 300°C, have significant enhancement compared with those have not been annealed. The on/off current ratio is more than 103 and the off current is less than 2×10−8A at VDS=40V.
{"title":"Studies on I-V performance enhancements of ZnO thin film transistors by vacuum treatments below 300°C","authors":"Yong-Qi Li, Lei Sun, Xiaoyan Liu, Yi Wang, Dedong Han","doi":"10.1109/EDSSC.2011.6117650","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117650","url":null,"abstract":"Bottom gate ZnO-TFTs are fabricated and the devices' characteristics are reported. Before contact patterning, ZnO films were annealed in high vacuum environment under lower temperatures compared with in forming gas treatments. The characteristics of the ZnO-TFTs which have been annealed, especially at 300°C, have significant enhancement compared with those have not been annealed. The on/off current ratio is more than 10<sup>3</sup> and the off current is less than 2×10<sup>−8</sup>A at V<inf>DS</inf>=40V.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"123 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85652699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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