Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117668
J. Zhan, C. Yang, X. Wang, T. Ren, A. Wang, Y. Yang, L. T. Liu, L. Yang
This paper reports a novel concept of vertically stacked-spiral RF inductor with integrated nano-powder-magnetic-core in standard CMOS. Prototype inductors in a foundry 0.18µm 6-metal CMOS and a post-CMOS backend process module (i.e., CMOS+) are fabricated and measured. Result shows the proof-of-concept designs greatly increase the inductance, L, by up to 34% and the factor, Q, by 62% over a multi-GHz frequency range.
{"title":"Nano-powder-magnetic-core vertically stacked-spiral RF inductor in CMOS","authors":"J. Zhan, C. Yang, X. Wang, T. Ren, A. Wang, Y. Yang, L. T. Liu, L. Yang","doi":"10.1109/EDSSC.2011.6117668","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117668","url":null,"abstract":"This paper reports a novel concept of vertically stacked-spiral RF inductor with integrated nano-powder-magnetic-core in standard CMOS. Prototype inductors in a foundry 0.18µm 6-metal CMOS and a post-CMOS backend process module (i.e., CMOS+) are fabricated and measured. Result shows the proof-of-concept designs greatly increase the inductance, L, by up to 34% and the factor, Q, by 62% over a multi-GHz frequency range.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82003108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117693
Y. Peng, Y. Liu, F. Yang, X. L. Zhang, X. P. Yu, Z. Lu, W. M. Lim, C. H. Hu
Software-defined radio (SDR), one of solutions to realize multi-mode terminal for mobile communication standards, has attracted intensive studies. A wideband wireless receiver is designed in a 40-nm CMOS process for SDR, which can cover the frequency range from 100MHz to 2GHz. The wideband RF front-end includes a low noise amplifier (LNA), a mixer, intermediate frequency amplifier (IF AMP) and a variable gain amplifier (VGA). The focal point of the design lies in the wideband LNA. The wideband inductorless LNA with 1.1-V supply is a two-stage amplifier that can operates from 100MHz to 2GHz. The noise figure (NF) of the LNA is 2.2–2.4 dB while it can achieve gains of 24-12 dB and 0– •12 dB when working under the active mode and passive mode, respectively. The whole system provides a NF of 3.2–3.5 dB with 5.02mw power consumption.
{"title":"A 100MHz — 2GHz wireless receiver in 40-nm CMOS for software-defined radio","authors":"Y. Peng, Y. Liu, F. Yang, X. L. Zhang, X. P. Yu, Z. Lu, W. M. Lim, C. H. Hu","doi":"10.1109/EDSSC.2011.6117693","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117693","url":null,"abstract":"Software-defined radio (SDR), one of solutions to realize multi-mode terminal for mobile communication standards, has attracted intensive studies. A wideband wireless receiver is designed in a 40-nm CMOS process for SDR, which can cover the frequency range from 100MHz to 2GHz. The wideband RF front-end includes a low noise amplifier (LNA), a mixer, intermediate frequency amplifier (IF AMP) and a variable gain amplifier (VGA). The focal point of the design lies in the wideband LNA. The wideband inductorless LNA with 1.1-V supply is a two-stage amplifier that can operates from 100MHz to 2GHz. The noise figure (NF) of the LNA is 2.2–2.4 dB while it can achieve gains of 24-12 dB and 0– •12 dB when working under the active mode and passive mode, respectively. The whole system provides a NF of 3.2–3.5 dB with 5.02mw power consumption.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"16 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91013110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A capacitor mismatch auto-compensation circuit has been designed and implemented for MEMS gyroscope differential capacitive sensing circuit. An in-chip capacitor array that controlled by the 7-bit SAR is selected to be connected in parallel with one of the gyroscope capacitor, making the two differential capacitors of the gyroscope equal. The compensation progress only takes eight periods of the clock at the start and will be turned off afterward automatically. The chip is fabricated in a 0.35um CMOS process. The test of the chip is performed with a vibratory gyroscope on the condition of a closed-loop control in the drive mode, and the measurement shows that the minimum capacitive compensation is 3.5fF.
{"title":"Capacitor mismatch auto-compensation for MEMS gyroscope differential capacitive sensing circuit","authors":"Ran Fang, Wengao Lu, Guannan Wang, Tingting Tao, Yacong Zhang, Zhongjian Chen, Dunshan Yu","doi":"10.1109/EDSSC.2011.6117623","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117623","url":null,"abstract":"A capacitor mismatch auto-compensation circuit has been designed and implemented for MEMS gyroscope differential capacitive sensing circuit. An in-chip capacitor array that controlled by the 7-bit SAR is selected to be connected in parallel with one of the gyroscope capacitor, making the two differential capacitors of the gyroscope equal. The compensation progress only takes eight periods of the clock at the start and will be turned off afterward automatically. The chip is fabricated in a 0.35um CMOS process. The test of the chip is performed with a vibratory gyroscope on the condition of a closed-loop control in the drive mode, and the measurement shows that the minimum capacitive compensation is 3.5fF.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"57 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89480132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multiple poly-silicon nanowires (PS-NW's) coated with different high-k dielectric materials, HfO2, Al2O3, and TiO2, were fabricated and their pH sensing characteristics were compared. Sidewall spacer formation technique was used for the PS-NW's fabrication and all the high-k materials were deposited by atomic-layer-deposition (ALD). Following the high-k dielectric deposition, a 3-aminopropyltriethoxysilane (y-APTES) layer was coated as sensing membrane. It is found that the multiple PS-NW sensor coated with HfO2 exhibits the highest sensitivity and best reproducibility for pH sensing.
{"title":"Comparison of multiple-polysilicon-nanowire pH-sensors coated with different ALD-deposited high-k dielectric materials","authors":"Po-Yen Hsu, Chun-Yu Wu, Huang-Chung Cheng, You-Lin Wu, W.T. Chang, Yuan-Lin Shen, Che-Ming Chang, Chia-Chung Wang, Jing-Jenn Lin","doi":"10.1109/EDSSC.2011.6117700","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117700","url":null,"abstract":"Multiple poly-silicon nanowires (PS-NW's) coated with different high-k dielectric materials, HfO2, Al2O3, and TiO2, were fabricated and their pH sensing characteristics were compared. Sidewall spacer formation technique was used for the PS-NW's fabrication and all the high-k materials were deposited by atomic-layer-deposition (ALD). Following the high-k dielectric deposition, a 3-aminopropyltriethoxysilane (y-APTES) layer was coated as sensing membrane. It is found that the multiple PS-NW sensor coated with HfO2 exhibits the highest sensitivity and best reproducibility for pH sensing.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"15 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82284634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117725
Junhong Feng, Z. Gan, Lifu Chang
This paper presents the nitrogen implant effects on ultra-thin gate oxide time dependent dielectric breakdown (TDDB) with the underlying mechanism studied. It is found that the nitrogen implant can improve TDDB reliability on NMOS while the corresponding gate leakage during TDDB stressing is much reduced. A deeper implantation with higher implant energy has a larger impact. In literature, the dielectric breakdown is explained by anode hydrogen release (AHR) [1] or the anode hole injection (AHI) [2] models. In this study, the experimental observation is mainly attributed to the nitrogen penetration into the gate dielectric, which then enhances the capability of electron negative trap. Detailed study shows that the nitrogen-assisted interface traps increase with nitrogen implant energy, leading to a reduced leakage current during TDDB stressing and longer time to breakdown (Tbd).
{"title":"Effects of nitrogen implant on ultra-thin gate dielectric breakdown","authors":"Junhong Feng, Z. Gan, Lifu Chang","doi":"10.1109/EDSSC.2011.6117725","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117725","url":null,"abstract":"This paper presents the nitrogen implant effects on ultra-thin gate oxide time dependent dielectric breakdown (TDDB) with the underlying mechanism studied. It is found that the nitrogen implant can improve TDDB reliability on NMOS while the corresponding gate leakage during TDDB stressing is much reduced. A deeper implantation with higher implant energy has a larger impact. In literature, the dielectric breakdown is explained by anode hydrogen release (AHR) [1] or the anode hole injection (AHI) [2] models. In this study, the experimental observation is mainly attributed to the nitrogen penetration into the gate dielectric, which then enhances the capability of electron negative trap. Detailed study shows that the nitrogen-assisted interface traps increase with nitrogen implant energy, leading to a reduced leakage current during TDDB stressing and longer time to breakdown (Tbd).","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"55 7 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80699437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117641
Hongliang Zhao, Yiqiang Zhao, Yiwei Song, Jun Liao, Junfeng Geng
A low power cryogenic readout integrated circuit (ROIC) for mid- and far-wave infrared focal plane array (FPA) is presented as a prototype for 512×512 image system. By applying capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CSD) structure, a high performance readout interface circuit for the infrared FPA is realized with a pixel size of 30×30 µm2. Optimized column readout timing and two operating modes in column amplifiers are used to reduce the power consumption. The readout chip designed by Chartered 0.35 µm 2P4M process shows more than 10 MHz readout rate and less than 70 mW power consumption under 3.3 V supply voltage at 77 K to 150 K operating temperature. And it occupies an area of 18.4×17.5 mm2.
{"title":"A low power cryogenic CMOS ROIC for 512×512 infrared focal plane array","authors":"Hongliang Zhao, Yiqiang Zhao, Yiwei Song, Jun Liao, Junfeng Geng","doi":"10.1109/EDSSC.2011.6117641","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117641","url":null,"abstract":"A low power cryogenic readout integrated circuit (ROIC) for mid- and far-wave infrared focal plane array (FPA) is presented as a prototype for 512×512 image system. By applying capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CSD) structure, a high performance readout interface circuit for the infrared FPA is realized with a pixel size of 30×30 µm2. Optimized column readout timing and two operating modes in column amplifiers are used to reduce the power consumption. The readout chip designed by Chartered 0.35 µm 2P4M process shows more than 10 MHz readout rate and less than 70 mW power consumption under 3.3 V supply voltage at 77 K to 150 K operating temperature. And it occupies an area of 18.4×17.5 mm2.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83085564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117640
Abhisek Dey, T. K. Bhattacharyya
A high precision temperature compensated CMOS bandgap reference is implemented in UMC 0.18µm RF/CMOS process. The proposed circuit employs current-mode architecture that removes the supply as well as reference voltage limitations. Using only first order compensation the new architecture can generate an output reference voltage of 600mV with a variation of 400µV over a wide temperature range from +20°C to +100°C which corresponds to a temperature coefficient of 5.5ppm/°C. The output reference voltage exhibits a variation of 2mV for supply voltage ranging from 1.6V to 2.0V. Simulation result shows that the power supply rejection ratio of the proposed circuit is 79dB from DC up to 1kHz of frequency. The presented bandgap reference occupies only 0.09 mm2 layout area.
{"title":"A CMOS bandgap reference with high PSRR and improved temperature stability for system-on-chip applications","authors":"Abhisek Dey, T. K. Bhattacharyya","doi":"10.1109/EDSSC.2011.6117640","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117640","url":null,"abstract":"A high precision temperature compensated CMOS bandgap reference is implemented in UMC 0.18µm RF/CMOS process. The proposed circuit employs current-mode architecture that removes the supply as well as reference voltage limitations. Using only first order compensation the new architecture can generate an output reference voltage of 600mV with a variation of 400µV over a wide temperature range from +20°C to +100°C which corresponds to a temperature coefficient of 5.5ppm/°C. The output reference voltage exhibits a variation of 2mV for supply voltage ranging from 1.6V to 2.0V. Simulation result shows that the power supply rejection ratio of the proposed circuit is 79dB from DC up to 1kHz of frequency. The presented bandgap reference occupies only 0.09 mm2 layout area.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"79 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77734860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The effects of gamma irradiation on Gallium-Arsenide (GaAs) Heterojunction Bipolar Transistor (HBT) is reported. DC and Radio Frequency (RF) performance are investigated for gamma doses up to 7 Mrad(Si). After 7Mrad(Si) gamma irradiation, an increase of base current (lb) is observed, the change is thought to be mainly due to the reduction of the effective minority carrier lifetime (τ) in the n-type emitter. Besides, the cutoff frequency (fT) decreases, which is caused by the decrease of the electron mobility (µn) in the base and the collector-base space charge region.
{"title":"The effects of gamma irradiation on GaAs HBT","authors":"Yang Shi, Lü Hong-Liang, Zhang Yu-ming, Zhang Yi-men, Zhang Jin-Can, Zhang Hai-Peng","doi":"10.1109/EDSSC.2011.6117663","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117663","url":null,"abstract":"The effects of gamma irradiation on Gallium-Arsenide (GaAs) Heterojunction Bipolar Transistor (HBT) is reported. DC and Radio Frequency (RF) performance are investigated for gamma doses up to 7 Mrad(Si). After 7Mrad(Si) gamma irradiation, an increase of base current (lb) is observed, the change is thought to be mainly due to the reduction of the effective minority carrier lifetime (τ) in the n-type emitter. Besides, the cutoff frequency (fT) decreases, which is caused by the decrease of the electron mobility (µn) in the base and the collector-base space charge region.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"29 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81440348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117567
M. Ker
Circuit solution for system-level electrostatic discharge (ESD) protection is presented in this invited talk. To prevent the microelectronic system frozen at the malfunction or upset states after system-level ESD test, on-chip ESD-aware circuit in CMOS ICs should be built to rescue itself from the unknown states for returning normal system operation. A novel concept of transient-to-digital converter is innovatively provided to detect the fast electrical transients during the system-level ESD events. The output digital thermometer codes of the transient-to-digital converter can correspond to the different ESD voltages during system-level ESD tests. The proposed solution has been applied in some display panels to automatically recover the system operations after system-level ESD test.
{"title":"ESD-aware circuit design in CMOS integrated circuits to meet system-level ESD specification in microelectronic systems","authors":"M. Ker","doi":"10.1109/EDSSC.2011.6117567","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117567","url":null,"abstract":"Circuit solution for system-level electrostatic discharge (ESD) protection is presented in this invited talk. To prevent the microelectronic system frozen at the malfunction or upset states after system-level ESD test, on-chip ESD-aware circuit in CMOS ICs should be built to rescue itself from the unknown states for returning normal system operation. A novel concept of transient-to-digital converter is innovatively provided to detect the fast electrical transients during the system-level ESD events. The output digital thermometer codes of the transient-to-digital converter can correspond to the different ESD voltages during system-level ESD tests. The proposed solution has been applied in some display panels to automatically recover the system operations after system-level ESD test.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"21 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82877315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117698
J. Tsai, Jia-Cing Jhou, J. Ou-Yang
The comparison of DC performance on InGaP/InGaAs pseudomorphic field-effect transistors with triple doped-channel profiles is demonstrated. As compared to the uniform and high-medium-low doped-channel devices, the low-medium-high doped-channel device exhibits the broadest gate voltage swing and the best device linearity. Experimentally, the transconductance within 50% of its maximum value for gate voltage swing is 4.62 V in the low-medium-high doped-channel device, which is greater than 3.58 (3.30) V in the uniform (high-medium-low) doped-channel device.
{"title":"Investigation of InGaP/InGaAs pseudomorphic triple doped-channel field-effect transistors","authors":"J. Tsai, Jia-Cing Jhou, J. Ou-Yang","doi":"10.1109/EDSSC.2011.6117698","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117698","url":null,"abstract":"The comparison of DC performance on InGaP/InGaAs pseudomorphic field-effect transistors with triple doped-channel profiles is demonstrated. As compared to the uniform and high-medium-low doped-channel devices, the low-medium-high doped-channel device exhibits the broadest gate voltage swing and the best device linearity. Experimentally, the transconductance within 50% of its maximum value for gate voltage swing is 4.62 V in the low-medium-high doped-channel device, which is greater than 3.58 (3.30) V in the uniform (high-medium-low) doped-channel device.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83668163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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