Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117634
M. Zhao, B. Li, Z. H. Wu
In this paper, a novel UWB transmitter chip is proposed, based on the 0.18 µm CMOS technology. A novel transmitting solution is adopted to realize a low-power and low-complexity physical implementation for future high data rate wireless component interconnect and implantable electronic applications. A UWB PA with standby, a digital ring on-off VCO, a subtractor for eliminating base-band component from the output of the VCO, and a narrow pulse generator are employed to achieve the chip with the maximum data-rate of 200Mbps, tunable-band of licensed 3∼7GHz, low-power of 8pJ/bit, and a small circuit area of 0.2mm2, of which the proposed subtractor, VCO, and PA play the important roles in reducing power dissipation. The simulation results verify that the proposed design is suitable for future potential applications.
{"title":"A novel low-power low-complexity chip solution for tunable UWB transmitter in CMOS 0.18µm technology","authors":"M. Zhao, B. Li, Z. H. Wu","doi":"10.1109/EDSSC.2011.6117634","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117634","url":null,"abstract":"In this paper, a novel UWB transmitter chip is proposed, based on the 0.18 µm CMOS technology. A novel transmitting solution is adopted to realize a low-power and low-complexity physical implementation for future high data rate wireless component interconnect and implantable electronic applications. A UWB PA with standby, a digital ring on-off VCO, a subtractor for eliminating base-band component from the output of the VCO, and a narrow pulse generator are employed to achieve the chip with the maximum data-rate of 200Mbps, tunable-band of licensed 3∼7GHz, low-power of 8pJ/bit, and a small circuit area of 0.2mm2, of which the proposed subtractor, VCO, and PA play the important roles in reducing power dissipation. The simulation results verify that the proposed design is suitable for future potential applications.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"445 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75806559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117701
Jianing Su, Zhenghao Lu, Xiaopeng Yu, Changhui Hu
This paper provides an efficient low complexity soft-decision demapper algorithm for computing the log-likelihood-ratios (LLRs) of the 8PSK demodulations in the DVB-S2 standard. The proposed method has linear complexity, avoids the multiple square operations in the classical method and reduces the number of compare-select operations by half compared to traditional LLR computation algorithms. The demapper using the proposed method has been verified on Altera FPGA.
{"title":"A novel low complexity soft-decision demapper for QPSK 8PSK demodulation of DVB-S2 systems","authors":"Jianing Su, Zhenghao Lu, Xiaopeng Yu, Changhui Hu","doi":"10.1109/EDSSC.2011.6117701","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117701","url":null,"abstract":"This paper provides an efficient low complexity soft-decision demapper algorithm for computing the log-likelihood-ratios (LLRs) of the 8PSK demodulations in the DVB-S2 standard. The proposed method has linear complexity, avoids the multiple square operations in the classical method and reduces the number of compare-select operations by half compared to traditional LLR computation algorithms. The demapper using the proposed method has been verified on Altera FPGA.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"36 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75314550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117571
H. Jin, S. Dong, M. Miao, J. Wu, F. Ma, J. K. Luo, J. Liou
Whole chip electrostatic discharge (ESD) protection for 2.4 GHz low noise amplifier (LNA) under 0.18 µm radio frequency (RF) CMOS process is proposed in this paper. Complementary silicon controlled rectifier (SCR) with different layouts for I/O pad ESD protection is evaluated and compared with traditional SCR and diode. Results show that the island complementary SCR (MSCRIsland) structure has highest figure of merit (FOM) and its ESD protection for RF I/O passes 6 kV human body model (HBM), while extra 0.28 dB noise figure (NF) and 178 fF capacitance is introduced into LNA by this ESD protection. LNA power clamp ESD protection is also designed as RC triggered various devices, such as NMOS, SCR and their mixture. Results show that RC trigger NMOS-SCR has high robustness and turn-on speed and its power clamp protection passes 5 kV HBM.
{"title":"Whole chip ESD protection for 2.4 GHz LNA","authors":"H. Jin, S. Dong, M. Miao, J. Wu, F. Ma, J. K. Luo, J. Liou","doi":"10.1109/EDSSC.2011.6117571","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117571","url":null,"abstract":"Whole chip electrostatic discharge (ESD) protection for 2.4 GHz low noise amplifier (LNA) under 0.18 µm radio frequency (RF) CMOS process is proposed in this paper. Complementary silicon controlled rectifier (SCR) with different layouts for I/O pad ESD protection is evaluated and compared with traditional SCR and diode. Results show that the island complementary SCR (MSCRIsland) structure has highest figure of merit (FOM) and its ESD protection for RF I/O passes 6 kV human body model (HBM), while extra 0.28 dB noise figure (NF) and 178 fF capacitance is introduced into LNA by this ESD protection. LNA power clamp ESD protection is also designed as RC triggered various devices, such as NMOS, SCR and their mixture. Results show that RC trigger NMOS-SCR has high robustness and turn-on speed and its power clamp protection passes 5 kV HBM.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"64 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73581094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117735
H. Chiu, K. Cho, Sheng-Wen Peng
This study presents the development of a novel ESD protection clamp by using dual-gate GaN HEMT technology for electric vehicle application. The proposed novel clamp possesses a low on-state resistance, uniform parasitic capacitance, and 500V trigger voltage for high voltage supply ESD applications. Implementation of the GaN ESD clamp demonstrates a human body mode (HBM) ESD test voltage more than 13kV stress voltage. In addition, the incorporated clamps use a fewer number of diodes than the conventional diode stacks at the trigger terminal, thereby making it size efficient and low effort impedance matching co-design which allow this approach to be an attractive solution for ESD protection.
{"title":"A high protection voltage dual-gate GaN HEMT clamp for electric vehicle application","authors":"H. Chiu, K. Cho, Sheng-Wen Peng","doi":"10.1109/EDSSC.2011.6117735","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117735","url":null,"abstract":"This study presents the development of a novel ESD protection clamp by using dual-gate GaN HEMT technology for electric vehicle application. The proposed novel clamp possesses a low on-state resistance, uniform parasitic capacitance, and 500V trigger voltage for high voltage supply ESD applications. Implementation of the GaN ESD clamp demonstrates a human body mode (HBM) ESD test voltage more than 13kV stress voltage. In addition, the incorporated clamps use a fewer number of diodes than the conventional diode stacks at the trigger terminal, thereby making it size efficient and low effort impedance matching co-design which allow this approach to be an attractive solution for ESD protection.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"14 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74867080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117572
Xiao Zhao, Huajun Fang, Jun Xu
A modification to the conventional constant-gm rail-to-rail operational transconductance amplifier is presented. The proposed amplifier has the benefit of delivering the same performance while consuming a fraction of the power compared to the conventional rail-to-rail amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in SMIC standard 65nm CMOS process. Simulation results show that the proposed amplifier achieves 168.1MHz unity-gain bandwidth, 63.8dB DC gain, 23.4V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional rail-to-rail amplifier with the same design specifications.
{"title":"A low power constant-Gm rail-to-rail operational transconductance amplifier by recycling current","authors":"Xiao Zhao, Huajun Fang, Jun Xu","doi":"10.1109/EDSSC.2011.6117572","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117572","url":null,"abstract":"A modification to the conventional constant-gm rail-to-rail operational transconductance amplifier is presented. The proposed amplifier has the benefit of delivering the same performance while consuming a fraction of the power compared to the conventional rail-to-rail amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in SMIC standard 65nm CMOS process. Simulation results show that the proposed amplifier achieves 168.1MHz unity-gain bandwidth, 63.8dB DC gain, 23.4V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional rail-to-rail amplifier with the same design specifications.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75932965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117665
S. Xie, W. Ng
In this paper, a fully digital delay line based temperature sensor is presented for on-chip thermal monitoring. Unlike previous delay line temperature sensors, the proposed design employs a 2N to N tab decoding along with counter and in this way dynamic power is saved by a factor of 2N. Post-layout simulation for a 65nm CMOS design shows that the proposed sensor consumes 0.02 nJ energy per conversion and it has a resolution of 1.0 °C with errors less than ±3.0 °C over a temperature range from 0 to 100 °C.
{"title":"A 65nm CMOS low power delay line based temperature sensor","authors":"S. Xie, W. Ng","doi":"10.1109/EDSSC.2011.6117665","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117665","url":null,"abstract":"In this paper, a fully digital delay line based temperature sensor is presented for on-chip thermal monitoring. Unlike previous delay line temperature sensors, the proposed design employs a 2N to N tab decoding along with counter and in this way dynamic power is saved by a factor of 2N. Post-layout simulation for a 65nm CMOS design shows that the proposed sensor consumes 0.02 nJ energy per conversion and it has a resolution of 1.0 °C with errors less than ±3.0 °C over a temperature range from 0 to 100 °C.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"27 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82169352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117622
Y. Kwon, Chang-Ju Lee, Do-kywn Kim, Heon-Bok Lee, S. Hahm
We studied a vertical type GaN schottky barrier diode (SBD) on the laser-lift-off (LLO) GaN layer with top schottky contact metals such as nickel and aluminium. The I-V characteristic was not strongly dependent on the schottky metals and the forward voltage drop was higher than the theoretical value. The C-V characteristic of metal-oxide-semiconductor (MOS) capacitor exhibits from the accumulation to inversion around •10 V. These results suggest that the wide band gap thin film layer remains at the surface of the N-face GaN layer.
{"title":"Vertical GaN schottky barrier diode on an N-face GaN layer formed by ELOG and laser-lift-off technique for high-power application","authors":"Y. Kwon, Chang-Ju Lee, Do-kywn Kim, Heon-Bok Lee, S. Hahm","doi":"10.1109/EDSSC.2011.6117622","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117622","url":null,"abstract":"We studied a vertical type GaN schottky barrier diode (SBD) on the laser-lift-off (LLO) GaN layer with top schottky contact metals such as nickel and aluminium. The I-V characteristic was not strongly dependent on the schottky metals and the forward voltage drop was higher than the theoretical value. The C-V characteristic of metal-oxide-semiconductor (MOS) capacitor exhibits from the accumulation to inversion around •10 V. These results suggest that the wide band gap thin film layer remains at the surface of the N-face GaN layer.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"8 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82504102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117695
Liu Hui-gang, Li Yanyan, Geng Weidong
In this paper, an adjustable gamma correction reference voltage source for Liquid Crystal on Silicon (LCoS) is proposed. The reference voltage source is taped out by Chartered 0.35µm CMOS 2P4M Mixed-mode process, and the chip was tested. The test results indicate that the output of the chip can completely meet requirements of the common electronic field-inversion field sequential LCoS display system, and the setup time and accuracy of output voltage achieve the expected target.
{"title":"Adjustable gamma correction reference voltage source for LCoS","authors":"Liu Hui-gang, Li Yanyan, Geng Weidong","doi":"10.1109/EDSSC.2011.6117695","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117695","url":null,"abstract":"In this paper, an adjustable gamma correction reference voltage source for Liquid Crystal on Silicon (LCoS) is proposed. The reference voltage source is taped out by Chartered 0.35µm CMOS 2P4M Mixed-mode process, and the chip was tested. The test results indicate that the output of the chip can completely meet requirements of the common electronic field-inversion field sequential LCoS display system, and the setup time and accuracy of output voltage achieve the expected target.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"21 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78423908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117708
W. Tang, M. Greiner, M. Helander, Z. Lu, W. Ng
CuPc-based TFTs with high-k dielectric ZrO2 as gate dielectric prepared by RF magnetron sputtering with various Ar/O2 ratios have been fabricated. The effects of oxygen concentration in the sputtering ambient on the electrical performance of the devices are investigated. This work finds that increasing oxygen concentration in the sputtering ambient up to a Ar/O2 ratio of 4:1 can improve the OTFT performance including the mobility, sub-threshold slope and on/off ratio. On the other hand, further increasing the Ar/O2 ratio to 4:3 is found to degrade the device performance. This demonstrates that the electrical characteristics of the devices depend strongly on the oxygen concentration in the sputtering ambient. The origin of this phenomenon is discussed.
{"title":"Effects of different Ar/O2 ratios on the electrical properties of CuPc-based TFTs with ZrO2 gate dielectric","authors":"W. Tang, M. Greiner, M. Helander, Z. Lu, W. Ng","doi":"10.1109/EDSSC.2011.6117708","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117708","url":null,"abstract":"CuPc-based TFTs with high-k dielectric ZrO2 as gate dielectric prepared by RF magnetron sputtering with various Ar/O2 ratios have been fabricated. The effects of oxygen concentration in the sputtering ambient on the electrical performance of the devices are investigated. This work finds that increasing oxygen concentration in the sputtering ambient up to a Ar/O2 ratio of 4:1 can improve the OTFT performance including the mobility, sub-threshold slope and on/off ratio. On the other hand, further increasing the Ar/O2 ratio to 4:3 is found to degrade the device performance. This demonstrates that the electrical characteristics of the devices depend strongly on the oxygen concentration in the sputtering ambient. The origin of this phenomenon is discussed.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90549227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117626
Yan Feng, Guican Chen
A fractional-N frequency synthesizer with constant loop bandwidth is presented. This synthesizer can be applied to the multi-mode positioning receiver with seven modes in three positioning systems. In all seven modes it has constant loop bandwidth and can work stably by using the improved adjusting method in charge pump biasing current and the linear varactor in VCO (voltage-controlled oscillator). Simulations show that this synthesizer meets the requirements of high performance receiver. For each mode, the in-band and out-of-band phase noises are not lager than •95dBC/Hz and •119dBC/Hz@1MHz, respectively. The variation of normalized IcpKvco/wvco in seven modes is in the range of •8% and 7%. The setting time is less than 21µs. The total power consumption is 15.34mW at 1.8V voltage supply.
{"title":"A fractional-N synthesizer for multi-mode positioning system with constant loop bandwidth","authors":"Yan Feng, Guican Chen","doi":"10.1109/EDSSC.2011.6117626","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117626","url":null,"abstract":"A fractional-N frequency synthesizer with constant loop bandwidth is presented. This synthesizer can be applied to the multi-mode positioning receiver with seven modes in three positioning systems. In all seven modes it has constant loop bandwidth and can work stably by using the improved adjusting method in charge pump biasing current and the linear varactor in VCO (voltage-controlled oscillator). Simulations show that this synthesizer meets the requirements of high performance receiver. For each mode, the in-band and out-of-band phase noises are not lager than •95dBC/Hz and •119dBC/Hz@1MHz, respectively. The variation of normalized IcpKvco/wvco in seven modes is in the range of •8% and 7%. The setting time is less than 21µs. The total power consumption is 15.34mW at 1.8V voltage supply.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"53 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86936406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：