Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117643
Renjing Pan, J. Gu, K. M. Lim, K. Yeo, Kaixue Ma, Keping Wang
This paper presents the design and analysis of a RF CMOS power amplifier for 3.5GHz mobile WiMAX subscriber station applications. By using four-stage power combination technique at output stage, this new amplifier is able to deliver +32dBm power at input power of •2.7dBm. A PAE (power-added-efficiency) of 48.24% and 15.2% can be obtained at its PO1dB (output 1dB compression point) and +25dBm output power, respectively. A saturated power of +33.5 dBm can be achieved. Powered by a 3.3 Volt DC supply, this proposed power amplifier offers a power gain of 35.8dB. The simulation results show that this design can be fully adopted in 3.5GHz mobile WiMAX subscriber applications. The presented power amplifier is based on Globalfoundries' 0.18µm IC process.
{"title":"A CMOS power amplifier using power combination for 3.5GHz mobile WiMAX subscriber applications","authors":"Renjing Pan, J. Gu, K. M. Lim, K. Yeo, Kaixue Ma, Keping Wang","doi":"10.1109/EDSSC.2011.6117643","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117643","url":null,"abstract":"This paper presents the design and analysis of a RF CMOS power amplifier for 3.5GHz mobile WiMAX subscriber station applications. By using four-stage power combination technique at output stage, this new amplifier is able to deliver +32dBm power at input power of •2.7dBm. A PAE (power-added-efficiency) of 48.24% and 15.2% can be obtained at its PO1dB (output 1dB compression point) and +25dBm output power, respectively. A saturated power of +33.5 dBm can be achieved. Powered by a 3.3 Volt DC supply, this proposed power amplifier offers a power gain of 35.8dB. The simulation results show that this design can be fully adopted in 3.5GHz mobile WiMAX subscriber applications. The presented power amplifier is based on Globalfoundries' 0.18µm IC process.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"5 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89684780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117699
Teng Wang, Lei Zhao, Ziyi Hu, Zheng Xie, Xin'an Wang
In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.
{"title":"A hardware efficient implementation of chroma interpolator for H.264 encoders","authors":"Teng Wang, Lei Zhao, Ziyi Hu, Zheng Xie, Xin'an Wang","doi":"10.1109/EDSSC.2011.6117699","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117699","url":null,"abstract":"In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"33 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90925002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117562
Jeong-Soo Lee, Sungho Kim, Kihyun Kim, T. Rim, Y. Jeong, M. Meyyappan
Introduction: Increased demand for point-of-care diagnostics has provided a strong motivation for the development of lab-on-a chip systems. The most important part to develop the system is to realize sensing components with high sensitivity, high reliability, low power consumption, low noise and small size in a cost-effective way. The Si-nanowire (Si-NW) ion-sensitive field effect transistor (ISFET) has been considered as one of the most promising devices because of the well-established fabrication techniques taking advantage of the low-cost wafer-scale top down methods [1–2]. In this work, the Si-NW ISFETs with embedded Ag/AgCI electrode have been demonstrated. The DC characteristics and the pH response of the Si-NW ISFET were measured and analysed. In addition, the low-frequency noise measurement was performed in order to investigate noise characteristics of the Si-NW ISFETs.
{"title":"Nanoscale silicon ion-sensitive field-effect transistors for pH sensor and biosensor applications","authors":"Jeong-Soo Lee, Sungho Kim, Kihyun Kim, T. Rim, Y. Jeong, M. Meyyappan","doi":"10.1109/EDSSC.2011.6117562","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117562","url":null,"abstract":"Introduction: Increased demand for point-of-care diagnostics has provided a strong motivation for the development of lab-on-a chip systems. The most important part to develop the system is to realize sensing components with high sensitivity, high reliability, low power consumption, low noise and small size in a cost-effective way. The Si-nanowire (Si-NW) ion-sensitive field effect transistor (ISFET) has been considered as one of the most promising devices because of the well-established fabrication techniques taking advantage of the low-cost wafer-scale top down methods [1–2]. In this work, the Si-NW ISFETs with embedded Ag/AgCI electrode have been demonstrated. The DC characteristics and the pH response of the Si-NW ISFET were measured and analysed. In addition, the low-frequency noise measurement was performed in order to investigate noise characteristics of the Si-NW ISFETs.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81002220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117670
Shengxi Huang, Zhe Wang, Ze Yuan, Jinyu Zhang, Zhiping Yu
A radial-heterojunction (HJ), as opposed to axial-HJ, tunneling-FET (tFET) is proposed to increase the driving current as much as 4 times while maintaining steep subthreshold swing (SS) and non-ambipolarity (i.e., unipolar transfer characteristics). The core/shell nanowire is adopted for the bulk of the device, with source region in the core of the wire and shell for the channel. The tunneling thus occurs in the radial direction, increasing the junction area substantially and leading to large on current. The core-shell junction is made of Ge-Si, and a lightly-doped drain-extension is used to suppress ambipolarity, which impedes the application of many types of tunneling devices in digital circuits. Comparison with unipolar axial-HJ GAA NW-tFET is made to show the advantage of the radial structure.
{"title":"Core-shell type of tunneling nanowire FETs for large driving current with unipolarity","authors":"Shengxi Huang, Zhe Wang, Ze Yuan, Jinyu Zhang, Zhiping Yu","doi":"10.1109/EDSSC.2011.6117670","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117670","url":null,"abstract":"A radial-heterojunction (HJ), as opposed to axial-HJ, tunneling-FET (tFET) is proposed to increase the driving current as much as 4 times while maintaining steep subthreshold swing (SS) and non-ambipolarity (i.e., unipolar transfer characteristics). The core/shell nanowire is adopted for the bulk of the device, with source region in the core of the wire and shell for the channel. The tunneling thus occurs in the radial direction, increasing the junction area substantially and leading to large on current. The core-shell junction is made of Ge-Si, and a lightly-doped drain-extension is used to suppress ambipolarity, which impedes the application of many types of tunneling devices in digital circuits. Comparison with unipolar axial-HJ GAA NW-tFET is made to show the advantage of the radial structure.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76627504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117718
M. Zhu, G. Du, Xiaoyan Liu
In this paper, the effects of oxide charges at different locations on on-state and off-state performance of SOI LDMOS devices are investigated through simulation. According to the results, the channel end region and channel side of STI have great effect on device on-state performance while the drain side of STI greatly affect off-state performance.
{"title":"Degradation effects of gate oxide and STI charge in SOI LDMOS","authors":"M. Zhu, G. Du, Xiaoyan Liu","doi":"10.1109/EDSSC.2011.6117718","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117718","url":null,"abstract":"In this paper, the effects of oxide charges at different locations on on-state and off-state performance of SOI LDMOS devices are investigated through simulation. According to the results, the channel end region and channel side of STI have great effect on device on-state performance while the drain side of STI greatly affect off-state performance.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82650954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117609
Shih-Wei Wang, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Chia-Hsien Lin, Hsuan-Hsu Chen, Po-Hsieh Lin, Chih-Hsuan Tai, C. Pai
In this work, a qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs is carefully investigated. According to numerical simulations, we find out that both gm and gD of junction poly-Si TFT are higher than the junctionless poly-Si TFT at a fixed IDS. Based on the same S/D doping concentration the junctionless poly-Si TFT can have a better short-channel behavior than its counterpart. Thus, it can be proved that a junctionless poly-Si TFT is a good option for AMLCD and AMOLED Applications.
{"title":"A qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs","authors":"Shih-Wei Wang, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Chia-Hsien Lin, Hsuan-Hsu Chen, Po-Hsieh Lin, Chih-Hsuan Tai, C. Pai","doi":"10.1109/EDSSC.2011.6117609","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117609","url":null,"abstract":"In this work, a qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs is carefully investigated. According to numerical simulations, we find out that both gm and gD of junction poly-Si TFT are higher than the junctionless poly-Si TFT at a fixed IDS. Based on the same S/D doping concentration the junctionless poly-Si TFT can have a better short-channel behavior than its counterpart. Thus, it can be proved that a junctionless poly-Si TFT is a good option for AMLCD and AMOLED Applications.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84799519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117577
G. C. Patil, S. Qureshi
In this paper, it has been shown that employing an underlap channel in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only improves the scalability but also reduces the process induced threshold voltage variability of this device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off a novel Si3N4: HfO2 dual-k spacer underlap channel DSSB SOI MOSFET has also been proposed. Although the presence of HfO2 inner spacer layer increases the gate capacitance, the reduction in off-state leakage current and the improvement in on-state drive current over the conventional Si3N4: SiO2 spacer overlap/underlap channel DSSB SOI MOSFETs makes the proposed device suitable for low-power digital logic circuits.
本文表明，在掺杂隔离肖特基势垒(DSSB) SOI MOSFET中采用下迭通道不仅可以提高可扩展性，还可以降低该器件的工艺诱导阈值电压变异性。然而，由于跨搭接长度的电压下降而降低的有效栅极电压也降低了器件的导通状态驱动电流。为了减轻这种权衡，还提出了一种新的Si3N4: HfO2双k间隔层下迭通道DSSB SOI MOSFET。虽然HfO2内间隔层的存在增加了栅极电容，但与传统的Si3N4: SiO2间隔层重叠/underlap通道DSSB SOI mosfet相比，关闭状态泄漏电流的减少和导通状态驱动电流的提高使所提出的器件适用于低功耗数字逻辑电路。
{"title":"Si3N4: HfO2 dual-k spacer dopant-segregated Schottky barrier SOI MOSFET for low-power applications","authors":"G. C. Patil, S. Qureshi","doi":"10.1109/EDSSC.2011.6117577","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117577","url":null,"abstract":"In this paper, it has been shown that employing an underlap channel in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only improves the scalability but also reduces the process induced threshold voltage variability of this device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off a novel Si3N4: HfO2 dual-k spacer underlap channel DSSB SOI MOSFET has also been proposed. Although the presence of HfO2 inner spacer layer increases the gate capacitance, the reduction in off-state leakage current and the improvement in on-state drive current over the conventional Si3N4: SiO2 spacer overlap/underlap channel DSSB SOI MOSFETs makes the proposed device suitable for low-power digital logic circuits.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"71 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83373482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117727
L. Changlong, Z. Yiqiang, Shi Yafeng, Gao Xingbo
Hardware Trojan, similar to the computer viruses, is a new threat in modern System-On-Chips (SOCs) such as security chips and trusted computer systems. Despite the risks that such an attack entails, little attention has been given to the methods of run-time Trojan detection. In this paper, the defects in existing security chips are analyzed and an improved bus architecture for hardware Trojan protection is presented, which can prevent data from runtime Trojan attacking in the digital circuits. A novel bus controller and random number generator (RNG) are used to implement the mechanism and the experimental results shows that the structure is efficient at thwarting the leaking of confidential information and signals.
{"title":"A System-On-Chip bus architecture for hardware Trojan protection in security chips","authors":"L. Changlong, Z. Yiqiang, Shi Yafeng, Gao Xingbo","doi":"10.1109/EDSSC.2011.6117727","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117727","url":null,"abstract":"Hardware Trojan, similar to the computer viruses, is a new threat in modern System-On-Chips (SOCs) such as security chips and trusted computer systems. Despite the risks that such an attack entails, little attention has been given to the methods of run-time Trojan detection. In this paper, the defects in existing security chips are analyzed and an improved bus architecture for hardware Trojan protection is presented, which can prevent data from runtime Trojan attacking in the digital circuits. A novel bus controller and random number generator (RNG) are used to implement the mechanism and the experimental results shows that the structure is efficient at thwarting the leaking of confidential information and signals.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85690181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117732
Z. M. S. Li, Y. G. Xiao, K. Uehara, M. Lestrade, S. Gao, Y. Fu, Z. Q. Li, Y. Zhou
Three-dimensional (3D) modeling of CMOS active pixel image sensor from process to opto-electronic response is reported in this work. Process simulation is performed by Crosslight CSuprem while the optical effect is simulated by finite difference time domain technique and the electronic response by 3D drift-diffusion software APSYS. The electronic responses are presented versus various power intensity and illumination wavelength. The presented results demonstrate a methodological and technical capability for 3D modeling optimization of complex CMOS image sensor.
{"title":"3D modeling of CMOS image sensor: From process to opto-electronic response","authors":"Z. M. S. Li, Y. G. Xiao, K. Uehara, M. Lestrade, S. Gao, Y. Fu, Z. Q. Li, Y. Zhou","doi":"10.1109/EDSSC.2011.6117732","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117732","url":null,"abstract":"Three-dimensional (3D) modeling of CMOS active pixel image sensor from process to opto-electronic response is reported in this work. Process simulation is performed by Crosslight CSuprem while the optical effect is simulated by finite difference time domain technique and the electronic response by 3D drift-diffusion software APSYS. The electronic responses are presented versus various power intensity and illumination wavelength. The presented results demonstrate a methodological and technical capability for 3D modeling optimization of complex CMOS image sensor.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"19 5","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72610545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117737
Yajie Qin, Qihui Chen, S. Signed, Zhiliang Hong
A workload-balanced multiplying digital-to-analog converter (WB-MDAC) is proposed to improve the settling efficiency of multi-bit pipeline stages, and demonstrated in a 14-bit 50-MS/s digital calibrated pipelined ADC. The presented ADC occupies an active area of 1.3 mm2 in 0.13-µm 1P8M CMOS technology, including internal reference buffers. It dissipates 76mW from a 1.2-V supply, and achieves 64.4 dB SNDR and over 80 dB SFDR.
提出了一种工作负载平衡乘法数模转换器(WB-MDAC)，以提高多位流水线级的求解效率，并在一个14位50 ms /s数字校准流水线ADC中进行了验证。该ADC采用0.13µm 1P8M CMOS技术，包括内部参考缓冲器，其有效面积为1.3 mm2。它从1.2 v电源消耗76mW，实现64.4 dB SNDR和超过80 dB SFDR。
{"title":"A 50MS/s 80dB SFDR digital calibrated pipelined ADC with workload-balanced MDAC","authors":"Yajie Qin, Qihui Chen, S. Signed, Zhiliang Hong","doi":"10.1109/EDSSC.2011.6117737","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117737","url":null,"abstract":"A workload-balanced multiplying digital-to-analog converter (WB-MDAC) is proposed to improve the settling efficiency of multi-bit pipeline stages, and demonstrated in a 14-bit 50-MS/s digital calibrated pipelined ADC. The presented ADC occupies an active area of 1.3 mm2 in 0.13-µm 1P8M CMOS technology, including internal reference buffers. It dissipates 76mW from a 1.2-V supply, and achieves 64.4 dB SNDR and over 80 dB SFDR.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"70 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76259481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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