Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117721
D. Yu, L. Liu, B. Chen, F. Zhang, B. Gao, Y. Fu, X. Liu, J. Kang, X. Zhang
Ag/SiO2/Pt-based resistive random access memory (RRAM) devices were fabricated and investigated. Multilevel resistive switching (RS) phenomenon was observed in Ag/SiO2/Pt devices under different operation modes. Good endurance and retention characteristics of RRAM device with four resistance states were achieved. The possible mechanism of multilevel RS was discussed.
{"title":"Multilevel resistive switching characteristics in Ag/SiO2/Pt RRAM devices","authors":"D. Yu, L. Liu, B. Chen, F. Zhang, B. Gao, Y. Fu, X. Liu, J. Kang, X. Zhang","doi":"10.1109/EDSSC.2011.6117721","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117721","url":null,"abstract":"Ag/SiO2/Pt-based resistive random access memory (RRAM) devices were fabricated and investigated. Multilevel resistive switching (RS) phenomenon was observed in Ag/SiO2/Pt devices under different operation modes. Good endurance and retention characteristics of RRAM device with four resistance states were achieved. The possible mechanism of multilevel RS was discussed.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"329 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80453681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1142/S0218126613400318
Zaifeng Shi, Tao Luo, Yuanqing Li, Yan Xu, S. Yao
It is necessary to estimate the system parameters such as bus utilization and buffer capacity In SoC architecture design. With the increase of complexity of system structure and communication protocol, the estimation becomes harder. The cycle-accurate modeling and simulation for the structure and data stream of On-Chip Bus is an efficient method to obtain the estimate value of above parameters. In this paper, this method is implemented by analyzing a Wishbone bus used in a Video Format Conversion chip, using Simulink. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method are verified. This method is suitable for analyzing various interconnecting architectures such as user-defined bus, industrial standard bus, multi-core and multi-bus system.
{"title":"An On-Chip Bus modeling and parameter simulation method based on utilization analysis","authors":"Zaifeng Shi, Tao Luo, Yuanqing Li, Yan Xu, S. Yao","doi":"10.1142/S0218126613400318","DOIUrl":"https://doi.org/10.1142/S0218126613400318","url":null,"abstract":"It is necessary to estimate the system parameters such as bus utilization and buffer capacity In SoC architecture design. With the increase of complexity of system structure and communication protocol, the estimation becomes harder. The cycle-accurate modeling and simulation for the structure and data stream of On-Chip Bus is an efficient method to obtain the estimate value of above parameters. In this paper, this method is implemented by analyzing a Wishbone bus used in a Video Format Conversion chip, using Simulink. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method are verified. This method is suitable for analyzing various interconnecting architectures such as user-defined bus, industrial standard bus, multi-core and multi-bus system.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79161422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117610
Guannan Wang, Wengao Lu, Ran Fang, Li You, Yacong Zhang, Zhongjian Chen, L. Ji
A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffer's power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSA's feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 × 320 ROIC with pixel size of 30 × 30 µm2 has been designed and fabricated with a 0.35 µm DPTM CMOS process under 5v supply voltage.
{"title":"A low power high speed readout circuit for 320×320 IRFPA","authors":"Guannan Wang, Wengao Lu, Ran Fang, Li You, Yacong Zhang, Zhongjian Chen, L. Ji","doi":"10.1109/EDSSC.2011.6117610","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117610","url":null,"abstract":"A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffer's power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSA's feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 × 320 ROIC with pixel size of 30 × 30 µm2 has been designed and fabricated with a 0.35 µm DPTM CMOS process under 5v supply voltage.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"10 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78993658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work proposes the nano-scale leakage characterizations for post-UV irradiated membrane of a polydimethylsiloxane (PDMS)-treated hydrophobic fumed silica nanoparticles (NPs) and 3-aminopropyltriethoxysilane mixture (γ-APTES+NPs+UV) by conductive atomic-force-microscopy (C-AFM). We found the leakage characterizations of the γ-APTES+NPs+UV are similar to those of dielectric material. Our results show that prolonged UV illumination (120s) and 100: 1 γ-APTES/ silica NPs mixing ratio result in the lowest leakage current and highest breakdown voltage.
{"title":"Nano-scale leakage characterizations of the γ-APTES/ silica nanoparticles bionanocomposite","authors":"Po-Yen Hsu, Jing-Jenn Lin, Jheng-Jia Jhuang, You-Lin Wu","doi":"10.1109/EDSSC.2011.6117608","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117608","url":null,"abstract":"This work proposes the nano-scale leakage characterizations for post-UV irradiated membrane of a polydimethylsiloxane (PDMS)-treated hydrophobic fumed silica nanoparticles (NPs) and 3-aminopropyltriethoxysilane mixture (γ-APTES+NPs+UV) by conductive atomic-force-microscopy (C-AFM). We found the leakage characterizations of the γ-APTES+NPs+UV are similar to those of dielectric material. Our results show that prolonged UV illumination (120s) and 100: 1 γ-APTES/ silica NPs mixing ratio result in the lowest leakage current and highest breakdown voltage.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73107075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117566
T. Chiang, D. H. Chang
Based on two-dimensional solution of Poisson equation and perimeter-weighted-sum approach, a short-channel threshold voltage model for the tri-gate (TG) MOSFETs with localized trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model shows that threshold voltage behavior is strongly affected by the positive/negative trapped charges, silicon thickness, oxide thickness, and normalized damaged zone affect. The three-dimensional device simulator model verifies the model by the good match with each other. The model can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced TG charge-trapped memory device.
{"title":"A two-dimensional short-channel model for threshold voltage of tri-gate (TG) MOSFETs with localized trapped charges","authors":"T. Chiang, D. H. Chang","doi":"10.1109/EDSSC.2011.6117566","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117566","url":null,"abstract":"Based on two-dimensional solution of Poisson equation and perimeter-weighted-sum approach, a short-channel threshold voltage model for the tri-gate (TG) MOSFETs with localized trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model shows that threshold voltage behavior is strongly affected by the positive/negative trapped charges, silicon thickness, oxide thickness, and normalized damaged zone affect. The three-dimensional device simulator model verifies the model by the good match with each other. The model can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced TG charge-trapped memory device.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80999309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117712
J. Hou, Xiangyuan Xiao, Zhao Wang
As the rapid development of technology and global economy, the problem of energy crunch is becoming more and more aggravating because of world's increasing demand for energy consumption. Recently, solar energy has been explored as an alternative renewable source of energy of great importance because of its characteristics of inexhaustible. As a traditional rechargeable battery, the valve regulated lead-acid (VRLA) battery is widely used in stand-alone photovoltaic (PV) systems because of its low cost and maintenance-free operation characteristics. Many researches and efforts in stand-alone photovoltaic systems have been concentrated on the maximum power point tracking of the solar arrays and the improvement of the efficiency of charging to increase the lifetime of battery.
{"title":"Simulation of dual-stage charge management circuit used in stand-alone photovoltaic (PV) systems","authors":"J. Hou, Xiangyuan Xiao, Zhao Wang","doi":"10.1109/EDSSC.2011.6117712","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117712","url":null,"abstract":"As the rapid development of technology and global economy, the problem of energy crunch is becoming more and more aggravating because of world's increasing demand for energy consumption. Recently, solar energy has been explored as an alternative renewable source of energy of great importance because of its characteristics of inexhaustible. As a traditional rechargeable battery, the valve regulated lead-acid (VRLA) battery is widely used in stand-alone photovoltaic (PV) systems because of its low cost and maintenance-free operation characteristics. Many researches and efforts in stand-alone photovoltaic systems have been concentrated on the maximum power point tracking of the solar arrays and the improvement of the efficiency of charging to increase the lifetime of battery.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"93 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84222862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117728
Yang Gu, Yuming Zhang, Yimen Zhang, Hongliang Lu, Renxu Jia
The effect of the diode reverse recovery on the performance of inverters is analyzed. The PSpice simulation of the SPWM full bridge inverter has been performed with the Si p-i-n ultra fast diode and the SiC Schottky diode respectively used as the free wheeling diode under the same condition. With their comparison, the results show that the SiC Schottky diode can greatly reduce the power loss of inverters. Further more, the effects of diode parameter CJO on reverse recovery characteristics have been discussed.
{"title":"Analysis and simulation of inverter employing SiC Schottky diode","authors":"Yang Gu, Yuming Zhang, Yimen Zhang, Hongliang Lu, Renxu Jia","doi":"10.1109/EDSSC.2011.6117728","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117728","url":null,"abstract":"The effect of the diode reverse recovery on the performance of inverters is analyzed. The PSpice simulation of the SPWM full bridge inverter has been performed with the Si p-i-n ultra fast diode and the SiC Schottky diode respectively used as the free wheeling diode under the same condition. With their comparison, the results show that the SiC Schottky diode can greatly reduce the power loss of inverters. Further more, the effects of diode parameter CJO on reverse recovery characteristics have been discussed.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"19 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85797856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117685
Xiaopeng Liu, Yan Han, G. Liang, Mingyu Wang, Lu Liao
This paper presents a modified cascaded integral comb (CIC) interpolation filter in order to improve filter characteristics and reduce power consumption at the same time. The modified CIC interpolation filter is a two-stage multiplier-less CIC-based interpolator. The first stage is a cascaded CIC filter whereas the second stage is a cascaded CIC filter and a second-order compensator. In an effort to reduce power consumption, the poly-phase decomposition and no-recursive algorithm is used when the modified filter is implemented. Simulation and synthesis results indicate that the stop-band attenuation is up to 137.7 dB and the pass-band drop is only 0.0003 dB with the filter interpolation factor 16. Working at 50 MHz clock frequency, the filter can reduce the power consumption of 16.78%. This new interpolator is implemented on Altera Cyclone III EP3C10E144C8 FPGA.
本文提出了一种改进的级联积分梳状(CIC)插值滤波器，以改善滤波器的特性，同时降低功耗。改进的CIC插值滤波器是一种基于两级无乘法器的CIC插值器。第一级是级联CIC滤波器，而第二级是级联CIC滤波器和二阶补偿器。为了降低功耗，在实现改进滤波器时采用了多相分解和无递归算法。仿真和综合结果表明，当滤波器插补系数为16时，阻带衰减可达137.7 dB，通带降仅为0.0003 dB。该滤波器工作在50 MHz时钟频率下，功耗可降低16.78%。该插补器在Altera Cyclone III EP3C10E144C8 FPGA上实现。
{"title":"Design and implementation of a modified high performance and low power CIC interpolation filter","authors":"Xiaopeng Liu, Yan Han, G. Liang, Mingyu Wang, Lu Liao","doi":"10.1109/EDSSC.2011.6117685","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117685","url":null,"abstract":"This paper presents a modified cascaded integral comb (CIC) interpolation filter in order to improve filter characteristics and reduce power consumption at the same time. The modified CIC interpolation filter is a two-stage multiplier-less CIC-based interpolator. The first stage is a cascaded CIC filter whereas the second stage is a cascaded CIC filter and a second-order compensator. In an effort to reduce power consumption, the poly-phase decomposition and no-recursive algorithm is used when the modified filter is implemented. Simulation and synthesis results indicate that the stop-band attenuation is up to 137.7 dB and the pass-band drop is only 0.0003 dB with the filter interpolation factor 16. Working at 50 MHz clock frequency, the filter can reduce the power consumption of 16.78%. This new interpolator is implemented on Altera Cyclone III EP3C10E144C8 FPGA.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85512002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117740
To-Po Wang, Ji-Hong Ke, Cheng-Yu Chiang
A 5.8-GHz 0.18-µm CMOS fully integrated power amplifier (PA) with high saturated output power (Psat), high output 1-dB compressed point (OP1dB), and high power-added efficiency (PAE) is presented in this paper. This PA consists of two stages, the first stage is the single-ended cascode stage for PAE boosting, and the second stage is the cascode power stage for output power enhancement. To further accurately predict the PA performance in terms of power gain, Psat, and PAE, the on-chip passive components including inductors, capacitor, and interconnections are considered by using full-wave electronic-magnetic (EM) tool. From the measured results, the fabricated 5.8-GHz PA delivers 21.4-dBm saturated output power (Psat), 23.6-dB power gain, and 39.7% PAE. Compared to previously published 5.8-GHz 0.18-µm CMOS PAs, this work demonstrated the superior performance in terms of Psat, OP1dB, and PAE.
{"title":"A high-Psat high-PAE fully-integrated 5.8-GHz power amplifier in 0.18-µm CMOS","authors":"To-Po Wang, Ji-Hong Ke, Cheng-Yu Chiang","doi":"10.1109/EDSSC.2011.6117740","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117740","url":null,"abstract":"A 5.8-GHz 0.18-µm CMOS fully integrated power amplifier (PA) with high saturated output power (Psat), high output 1-dB compressed point (OP1dB), and high power-added efficiency (PAE) is presented in this paper. This PA consists of two stages, the first stage is the single-ended cascode stage for PAE boosting, and the second stage is the cascode power stage for output power enhancement. To further accurately predict the PA performance in terms of power gain, Psat, and PAE, the on-chip passive components including inductors, capacitor, and interconnections are considered by using full-wave electronic-magnetic (EM) tool. From the measured results, the fabricated 5.8-GHz PA delivers 21.4-dBm saturated output power (Psat), 23.6-dB power gain, and 39.7% PAE. Compared to previously published 5.8-GHz 0.18-µm CMOS PAs, this work demonstrated the superior performance in terms of Psat, OP1dB, and PAE.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"4 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85036052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/EDSSC.2011.6117625
B. Wang, H. Liu, M. Zhao, B. Li
A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-µm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 µw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.
{"title":"A novel low-power high-date-rate BPSK demodulator","authors":"B. Wang, H. Liu, M. Zhao, B. Li","doi":"10.1109/EDSSC.2011.6117625","DOIUrl":"https://doi.org/10.1109/EDSSC.2011.6117625","url":null,"abstract":"A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-µm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 µw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"30 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87809699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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