Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479086
Cheng‐Ming Lin, Hung-Chih Chang, Yen‐Ting Chen, I-Hsieh Wong, H. Lan, S. Luo, Jing-Yi Lin, Y.-J. Tseng, Cheewee Liu, C. Hu, Fu-Liang Yang
0.39-nm ultrathin EOT ZrO2 having κ value as high as ~43 without an interfacial layer (IL) is demonstrated on Ge substrates. The EOT and gate leakage are much lower than the recent reported data [1]. In situ NH3/H2 remote plasma treatment (RPT) after RTO-grown ultrathin (<;1nm) GeO2/Ge and prior to PEALD ZrO2 leads to the formation of tetragonal phase ZrO2 and the inhibition of GeOx IL regrowth. As the number of RPT cycles increases, it is observed that not only higher [N] but more GeO2 component formed on Ge surface. GeO diffuses into ZrO2 layer via the interface reaction (Ge+GeO2 → 2GeO) and stabilize the tetragonal phase ZrO2. The gate dielectric has a leakage current ~104X lower than other reported dielectrics in this EOT region. Ge (001) pMOSFET has low SS of 85 mV/dec and high Ion/Ioff of ~6×105 at Vd= -1V, while nMOSFET has SS of 90 mV/dec and Ion/Ioff of ~1×105 at Vd=1V. The peak electron mobility is determined by the remote phonon scattering stemming from the high-κ value. The biaxial tensile strain of ~0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the <;110> channel.
{"title":"Interfacial layer-free ZrO2 on Ge with 0.39-nm EOT, κ∼43, ∼2×10−3 A/cm2 gate leakage, SS =85 mV/dec, Ion/Ioff =6×105, and high strain response","authors":"Cheng‐Ming Lin, Hung-Chih Chang, Yen‐Ting Chen, I-Hsieh Wong, H. Lan, S. Luo, Jing-Yi Lin, Y.-J. Tseng, Cheewee Liu, C. Hu, Fu-Liang Yang","doi":"10.1109/IEDM.2012.6479086","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479086","url":null,"abstract":"0.39-nm ultrathin EOT ZrO<sub>2</sub> having κ value as high as ~43 without an interfacial layer (IL) is demonstrated on Ge substrates. The EOT and gate leakage are much lower than the recent reported data [1]. In situ NH<sub>3</sub>/H<sub>2</sub> remote plasma treatment (RPT) after RTO-grown ultrathin (<;1nm) GeO<sub>2</sub>/Ge and prior to PEALD ZrO<sub>2</sub> leads to the formation of tetragonal phase ZrO<sub>2</sub> and the inhibition of GeO<sub>x</sub> IL regrowth. As the number of RPT cycles increases, it is observed that not only higher [N] but more GeO<sub>2</sub> component formed on Ge surface. GeO diffuses into ZrO<sub>2</sub> layer via the interface reaction (Ge+GeO<sub>2</sub> → 2GeO) and stabilize the tetragonal phase ZrO<sub>2</sub>. The gate dielectric has a leakage current ~10<sup>4</sup>X lower than other reported dielectrics in this EOT region. Ge (001) pMOSFET has low SS of 85 mV/dec and high I<sub>on</sub>/I<sub>off</sub> of ~6×10<sup>5</sup> at V<sub>d</sub>= -1V, while nMOSFET has SS of 90 mV/dec and I<sub>on</sub>/I<sub>off</sub> of ~1×10<sup>5</sup> at V<sub>d</sub>=1V. The peak electron mobility is determined by the remote phonon scattering stemming from the high-κ value. The biaxial tensile strain of ~0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the <;110> channel.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"23.2.1-23.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78279273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479010
M. Jeong, S. Joe, B. Jo, Ho-Jung Kang, J. Bae, Kyoung-Rok Han, Eun-seok Choi, G. Cho, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee
Trap density (Dit) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted Dit with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the Dit extracted by conductance method was 1~2×1012 cm-2eV-1 in Ec-ET of 0.15~0.35 eV. The simulation results of IBL-VCG and C-VCG based on the Dit were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.
{"title":"Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure","authors":"M. Jeong, S. Joe, B. Jo, Ho-Jung Kang, J. Bae, Kyoung-Rok Han, Eun-seok Choi, G. Cho, Sung-Kye Park, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/IEDM.2012.6479010","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479010","url":null,"abstract":"Trap density (D<sub>it</sub>) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted D<sub>it</sub> with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the D<sub>it</sub> extracted by conductance method was 1~2×10<sup>12</sup> cm<sup>-2</sup>eV<sup>-1</sup> in E<sub>c</sub>-E<sub>T</sub> of 0.15~0.35 eV. The simulation results of I<sub>BL</sub>-V<sub>CG</sub> and C-V<sub>CG</sub> based on the D<sub>it</sub> were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"34 1","pages":"9.3.1-9.3.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80180082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479019
K. Abe, H. Noguchi, E. Kitagawa, N. Shimomura, J. Ito, S. Fujita
This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).
{"title":"Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU","authors":"K. Abe, H. Noguchi, E. Kitagawa, N. Shimomura, J. Ito, S. Fujita","doi":"10.1109/IEDM.2012.6479019","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479019","url":null,"abstract":"This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"7 1","pages":"10.5.1-10.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82129886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6478999
T. Iwasaki, Y. Hoshino, K. Tsuzuki, H. Kato, T. Makino, M. Ogura, D. Takeuchi, T. Matsumoto, H. Okushi, S. Yamasaki, M. Hatano
Diamond semiconductor is an attractive material for next-generation power devices due to its wide band-gap, high breakdown field, and high thermal conductivity. By selective n+-type diamond growth, diamond junction field effect transistors (JFETs) were fabricated and operated from 223 to 573 K. JFETs show very low leakage currents in the 10-15 A range and a steep subthreshold slope (SS) of 81 mV/decade at room temperature. We confirm that the devices possess steep SS and low leakage current in the 10-14-10-15 A r a n ge s up to 423 K.
{"title":"Diamond semiconductor JFETs by selectively grown n+-diamond side gates for next generation power devices","authors":"T. Iwasaki, Y. Hoshino, K. Tsuzuki, H. Kato, T. Makino, M. Ogura, D. Takeuchi, T. Matsumoto, H. Okushi, S. Yamasaki, M. Hatano","doi":"10.1109/IEDM.2012.6478999","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478999","url":null,"abstract":"Diamond semiconductor is an attractive material for next-generation power devices due to its wide band-gap, high breakdown field, and high thermal conductivity. By selective n+-type diamond growth, diamond junction field effect transistors (JFETs) were fabricated and operated from 223 to 573 K. JFETs show very low leakage currents in the 10-15 A range and a steep subthreshold slope (SS) of 81 mV/decade at room temperature. We confirm that the devices possess steep SS and low leakage current in the 10-14-10-15 A r a n ge s up to 423 K.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"21 1","pages":"7.5.1-7.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86466064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479154
Guangle Zhou, R. Li, T. Vasen, M. Qi, S. Chae, Y. Lu, Q. Zhang, H. Zhu, J. Kuo, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, H. Xing
Vertical tunnel field-effect transistors (TFETs) in which the gate field is aligned with the tunneling direction have been fabricated using a novel gate-recess process, resulting in record on-current. The tunnel junction consists of InAs/GaSb with a broken band alignment. The gate-recess process results in low drain contact and access resistances; together with the favorable broken gap heterojunction, this leads to a record high ION of 180 μA/μm at VDS = VGS = 0.5 V with an ION/IOFF ratio of 6 ×103. Both SiNx passivation and forming gas anneal (FGA) were found to improve the device subthreshold swing (SS), resulting in a SSMIN of 200 mV/dec at 300 K and 50 mV/dec at 77 K. Capacitance-voltage (C-V) measurements indicate that the device SS performance is limited by interfacial trap density (Dit).
{"title":"Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180 μA/μm at VDS = 0.5 V","authors":"Guangle Zhou, R. Li, T. Vasen, M. Qi, S. Chae, Y. Lu, Q. Zhang, H. Zhu, J. Kuo, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, H. Xing","doi":"10.1109/IEDM.2012.6479154","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479154","url":null,"abstract":"Vertical tunnel field-effect transistors (TFETs) in which the gate field is aligned with the tunneling direction have been fabricated using a novel gate-recess process, resulting in record on-current. The tunnel junction consists of InAs/GaSb with a broken band alignment. The gate-recess process results in low drain contact and access resistances; together with the favorable broken gap heterojunction, this leads to a record high I<sub>ON</sub> of 180 μA/μm at V<sub>DS</sub> = V<sub>GS</sub> = 0.5 V with an I<sub>ON</sub>/I<sub>OFF</sub> ratio of 6 ×10<sup>3</sup>. Both SiN<sub>x</sub> passivation and forming gas anneal (FGA) were found to improve the device subthreshold swing (SS), resulting in a SS<sub>MIN</sub> of 200 mV/dec at 300 K and 50 mV/dec at 77 K. Capacitance-voltage (C-V) measurements indicate that the device SS performance is limited by interfacial trap density (D<sub>it</sub>).","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"63 1","pages":"32.6.1-32.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86502701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479148
D. Ha, K. W. Lee, K. Sim, J. H. Yu, S. Ahn, S. Y. Kim, T. An, S. H. Hong, S. Kim, J. Lee, B. C. Kim, G. Koh, S. Nam, G. Jeong, C. Chung
This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current, ΔIPGM, is reduced from 17.8% to 0.82%, and that of a write energy, ΔEPGM, from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current, IRESET, for sub-40 nm PRAM technology and so on.
{"title":"Active Width Modulation (AWM) for cost-effective and highly reliable PRAM","authors":"D. Ha, K. W. Lee, K. Sim, J. H. Yu, S. Ahn, S. Y. Kim, T. An, S. H. Hong, S. Kim, J. Lee, B. C. Kim, G. Koh, S. Nam, G. Jeong, C. Chung","doi":"10.1109/IEDM.2012.6479148","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479148","url":null,"abstract":"This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current, ΔIPGM, is reduced from 17.8% to 0.82%, and that of a write energy, ΔEPGM, from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current, IRESET, for sub-40 nm PRAM technology and so on.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"64 1","pages":"31.8.1-31.8.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83908906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479085
S. Takagi, R. Zhang, S. Kim, N. Taoka, M. Yokoyama, Junkyo Suh, R. Suzuki, M. Takenaka
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for improving the channel mobility and the MOS interface properties with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. HfO2/Al2O3/GeOx/Ge gate stacks exhibit record high electron and hole mobility under EOT of 0.76 nm. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm. The results of low Dit HfO2/Al2O3/InGaAs stacks with CET of 1.08 nm are also presented. A strategy to enhance electron mobility in InGaAs MOSFETs on a basis of physical understanding of the MOS interface properties including high Dit inside the conduction band is also addressed.
{"title":"MOS interface and channel engineering for high-mobility Ge/III-V CMOS","authors":"S. Takagi, R. Zhang, S. Kim, N. Taoka, M. Yokoyama, Junkyo Suh, R. Suzuki, M. Takenaka","doi":"10.1109/IEDM.2012.6479085","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479085","url":null,"abstract":"CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for improving the channel mobility and the MOS interface properties with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. HfO2/Al2O3/GeOx/Ge gate stacks exhibit record high electron and hole mobility under EOT of 0.76 nm. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm. The results of low Dit HfO2/Al2O3/InGaAs stacks with CET of 1.08 nm are also presented. A strategy to enhance electron mobility in InGaAs MOSFETs on a basis of physical understanding of the MOS interface properties including high Dit inside the conduction band is also addressed.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"322 1","pages":"23.1.1-23.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86721003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479051
Rui Zhang, Po-Chin Huang, Ju-Chin Lin, M. Takenaka, S. Takagi
Hall measurements have been carried out for the Ge p-and n-MOSFETs with different substrate orientations and GeOx/Ge interface qualities. It is found that the significant reduction of effective mobility in high surface carrier concentration (Ns) or high normal field in Ge MOSFETs is attributed partly to the Ns loss due to large amounts of interface states inside the valence and conduction bands of Ge. The GeOx/Ge interface roughness is another reason limiting the high Ns mobility. It has been revealed that room temperature plasma post oxidation can realize Al2O3/GeOx/Ge gate stacks with atomically-flat GeOx/Ge interfaces. Ge MOSFETs with these interfaces have provided record high effective hole and electron mobility, which overcome the Si universal mobility in both low and high Ns regions.
{"title":"Physical mechanism determining Ge p- and n-MOSFETs mobility in high Ns region and mobility improvement by atomically flat GeOx/Ge interfaces","authors":"Rui Zhang, Po-Chin Huang, Ju-Chin Lin, M. Takenaka, S. Takagi","doi":"10.1109/IEDM.2012.6479051","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479051","url":null,"abstract":"Hall measurements have been carried out for the Ge p-and n-MOSFETs with different substrate orientations and GeO<sub>x</sub>/Ge interface qualities. It is found that the significant reduction of effective mobility in high surface carrier concentration (N<sub>s</sub>) or high normal field in Ge MOSFETs is attributed partly to the N<sub>s</sub> loss due to large amounts of interface states inside the valence and conduction bands of Ge. The GeO<sub>x</sub>/Ge interface roughness is another reason limiting the high N<sub>s</sub> mobility. It has been revealed that room temperature plasma post oxidation can realize Al<sub>2</sub>O<sub>3</sub>/GeO<sub>x</sub>/Ge gate stacks with atomically-flat GeO<sub>x</sub>/Ge interfaces. Ge MOSFETs with these interfaces have provided record high effective hole and electron mobility, which overcome the Si universal mobility in both low and high N<sub>s</sub> regions.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"104 1","pages":"16.1.1-16.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80677997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/IEDM.2012.6479033
P. Lagger, C. Ostermaier, G. Pobegen, D. Pogany
GaN-power HEMTs with insulated gate structure suffer from threshold voltage drifts (ΔVth) under forward gate bias stress. We present a systematical approach to characterize the phenomenon and understand the dominant physical mechanisms causing this effect. We found out that ΔVth is caused by traps with a broad distribution of trapping and emission time constants. This distribution is analyzed using so called Capture Emission Time (CET) maps known from the study of bias temperature instability (BTI) in CMOS devices. Physical models, which could explain the broad distribution of time constants, are discussed.
{"title":"Towards understanding the origin of threshold voltage instability of AlGaN/GaN MIS-HEMTs","authors":"P. Lagger, C. Ostermaier, G. Pobegen, D. Pogany","doi":"10.1109/IEDM.2012.6479033","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479033","url":null,"abstract":"GaN-power HEMTs with insulated gate structure suffer from threshold voltage drifts (ΔVth) under forward gate bias stress. We present a systematical approach to characterize the phenomenon and understand the dominant physical mechanisms causing this effect. We found out that ΔVth is caused by traps with a broad distribution of trapping and emission time constants. This distribution is analyzed using so called Capture Emission Time (CET) maps known from the study of bias temperature instability (BTI) in CMOS devices. Physical models, which could explain the broad distribution of time constants, are discussed.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"31 1","pages":"13.1.1-13.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83256836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/iedm.2012.6478982
N. Munzenrieder, L. Petti, C. Zysset, G. Salvatore, T. Kinkeldei, C. Perumal, C. Carta, F. Ellinger, G. Troster
We present flexible common source and cascode amplifiers fabricated on a free-standing plastic foil, using amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) TFTs with minimum channel lengths of 2.5 μm. Amplifiers are operated at a supply voltage VDD of 5 V, and exhibit maximum cutoff frequencies fC of 1.2 MHz. The circuits stay fully operational while bent to a tensile radius of 5 mm, and after 1000 cycles of repeated bending and re-flattening. To our knowledge, these are the fastest flexible oxide semiconductor based amplifiers.
{"title":"Flexible a-IGZO TFT amplifier fabricated on a free standing polyimide foil operating at 1.2 MHz while bent to a radius of 5 mm","authors":"N. Munzenrieder, L. Petti, C. Zysset, G. Salvatore, T. Kinkeldei, C. Perumal, C. Carta, F. Ellinger, G. Troster","doi":"10.1109/iedm.2012.6478982","DOIUrl":"https://doi.org/10.1109/iedm.2012.6478982","url":null,"abstract":"We present flexible common source and cascode amplifiers fabricated on a free-standing plastic foil, using amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) TFTs with minimum channel lengths of 2.5 μm. Amplifiers are operated at a supply voltage VDD of 5 V, and exhibit maximum cutoff frequencies fC of 1.2 MHz. The circuits stay fully operational while bent to a tensile radius of 5 mm, and after 1000 cycles of repeated bending and re-flattening. To our knowledge, these are the fastest flexible oxide semiconductor based amplifiers.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"22 1","pages":"5.2.1-5.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88139373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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