Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843939
K. Banerjee, A. Mehrotra, W. Hunter, K. Saraswat, K. Goodson, S.S. Wong
This paper presents a methodology for quantitative analysis of the role of electromigration (EM) reliability and interconnect performance in determining the optimal interconnect design in low-k/Cu interconnect systems. It is demonstrated that EM design limits for signal lines are satisfied once interconnect performance is optimized.
{"title":"Quantitative projections of reliability and performance for low-k/Cu interconnect systems","authors":"K. Banerjee, A. Mehrotra, W. Hunter, K. Saraswat, K. Goodson, S.S. Wong","doi":"10.1109/RELPHY.2000.843939","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843939","url":null,"abstract":"This paper presents a methodology for quantitative analysis of the role of electromigration (EM) reliability and interconnect performance in determining the optimal interconnect design in low-k/Cu interconnect systems. It is demonstrated that EM design limits for signal lines are satisfied once interconnect performance is optimized.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"24 1","pages":"354-358"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82111352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843922
E. Zanoni, G. Meneghesso, D. Buttari, M. Maretto, G. Massari
We measured the on-state breakdown of HEMTs in a nondestructive way using the Transmission Line Pulse technique reaching very high values of gate current density (30 mA/mm). On the basis of the experimental observations, we developed a new model for on-state breakdown of HEMTs, suitable for SPICE simulations, which is capable of predicting the breakdown curves. We have shown that a parasitic bipolar action can give rise in HEMTs to a new form of breakdown, which is accurately modeled by the SPICE equivalent circuit. The model not only predicts I/sub G/, but consistently describes I/sub D/ up to breakdown levels.
{"title":"Pulsed measurements and circuit modeling of a new breakdown mechanism of MESFETs and HEMTs","authors":"E. Zanoni, G. Meneghesso, D. Buttari, M. Maretto, G. Massari","doi":"10.1109/RELPHY.2000.843922","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843922","url":null,"abstract":"We measured the on-state breakdown of HEMTs in a nondestructive way using the Transmission Line Pulse technique reaching very high values of gate current density (30 mA/mm). On the basis of the experimental observations, we developed a new model for on-state breakdown of HEMTs, suitable for SPICE simulations, which is capable of predicting the breakdown curves. We have shown that a parasitic bipolar action can give rise in HEMTs to a new form of breakdown, which is accurately modeled by the SPICE equivalent circuit. The model not only predicts I/sub G/, but consistently describes I/sub D/ up to breakdown levels.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"108 1","pages":"243-249"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81847716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843947
Kuang-Peng Lin, K. Ching, Kwo-Shu Huang, S. Hsu
A bubble-like, protrusion defect is found at the p/sup +/ and n/sup +/ source/drain areas after the photoresist stripping process of source/drain implant mask. We can find it easily at active areas of wafer's flat or round site. Only one wafer suffered this issue each lot. This defect size range from 0.2 to 8 microns. The root cause is the expansion (by gas outlet) of a thin oxide film on the silicon surface. In deep submicron process, it will cause a severe reliability failure issue because of stress voiding caused by the formation of a vacancy beside metal interconnections. This study focuses on the root cause and the protrusion's formation mechanism. Various methods used to prevent and eliminate this problem are discussed.
{"title":"A study of implant damage induced thin oxide film expansion during photoresist dry etching","authors":"Kuang-Peng Lin, K. Ching, Kwo-Shu Huang, S. Hsu","doi":"10.1109/RELPHY.2000.843947","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843947","url":null,"abstract":"A bubble-like, protrusion defect is found at the p/sup +/ and n/sup +/ source/drain areas after the photoresist stripping process of source/drain implant mask. We can find it easily at active areas of wafer's flat or round site. Only one wafer suffered this issue each lot. This defect size range from 0.2 to 8 microns. The root cause is the expansion (by gas outlet) of a thin oxide film on the silicon surface. In deep submicron process, it will cause a severe reliability failure issue because of stress voiding caused by the formation of a vacancy beside metal interconnections. This study focuses on the root cause and the protrusion's formation mechanism. Various methods used to prevent and eliminate this problem are discussed.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"6 1","pages":"404-406"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73259490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843943
T. Hook, D. Harmon, Chuan Lin
It is shown that the primary manifestation of charging damage in thin (<4 nm) oxides is a degradation of dielectric integrity, while the primary manifestation of damage in thick (>6 nm) oxides is a shift in threshold voltage or the degradation of hot-carrier immunity. It is therefore necessary to effectively monitor both dielectric integrity and the parametric shifts to measure all of the consequences of charging damage on a technology with gate oxide less than 4 nm. We demonstrate the efficacy of a ramp breakdown methodology for this purpose, showing that a simple measurement of current is not sufficiently sensitive, and that results equivalent to a lengthy time-to-breakdown test may be achieved. Furthermore, we show ramp data on some thousands of chips from a manufacturing line, which demonstrates robust charging behavior for realistic gate and wiring antennas.
{"title":"Detection of thin oxide (3.5 nm) dielectric degradation due to charging damage by rapid-ramp breakdown","authors":"T. Hook, D. Harmon, Chuan Lin","doi":"10.1109/RELPHY.2000.843943","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843943","url":null,"abstract":"It is shown that the primary manifestation of charging damage in thin (<4 nm) oxides is a degradation of dielectric integrity, while the primary manifestation of damage in thick (>6 nm) oxides is a shift in threshold voltage or the degradation of hot-carrier immunity. It is therefore necessary to effectively monitor both dielectric integrity and the parametric shifts to measure all of the consequences of charging damage on a technology with gate oxide less than 4 nm. We demonstrate the efficacy of a ramp breakdown methodology for this purpose, showing that a simple measurement of current is not sufficiently sensitive, and that results equivalent to a lengthy time-to-breakdown test may be achieved. Furthermore, we show ramp data on some thousands of chips from a manufacturing line, which demonstrates robust charging behavior for realistic gate and wiring antennas.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"293 1","pages":"377-388"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79542440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843944
S. Chung, S. J. Chen, H. Kao, S. Luo, H. Lin
Plasma etching of polysilicon in an MOS device during the gate definition induces the plasma edge damage at the corner of the gate. In this paper, we address the interaction between edge damage, antenna effect and hot carrier degradation and their impact on device reliability. An accurate charge pumping profiling technique has been proposed to characterize the resulting damage. A three-phase edge damage process has been proposed. It is shown that interface trap degradation is the dominant impact of the plasma induced edge damage. The edge damage will enhance the short channel device HC degradation under long-term circuit operation.
{"title":"Charge pumping technique for the evaluation of plasma induced edge damage in shallow S/D extension thin gate oxide NMOSFETs","authors":"S. Chung, S. J. Chen, H. Kao, S. Luo, H. Lin","doi":"10.1109/RELPHY.2000.843944","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843944","url":null,"abstract":"Plasma etching of polysilicon in an MOS device during the gate definition induces the plasma edge damage at the corner of the gate. In this paper, we address the interaction between edge damage, antenna effect and hot carrier degradation and their impact on device reliability. An accurate charge pumping profiling technique has been proposed to characterize the resulting damage. A three-phase edge damage process has been proposed. It is shown that interface trap degradation is the dominant impact of the plasma induced edge damage. The edge damage will enhance the short channel device HC degradation under long-term circuit operation.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"115 18 1","pages":"389-393"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84194864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843930
X.Y. Zhang, K. Banerjee, A. Amerasekera, V. Gupta, Zhiping Yu, R. Dutton
This paper demonstrates a new methodology for bringing accurate substrate resistance modeling into circuit level ESD simulation. The impact of layout and process variations on the effective substrate resistance of deep sub-micron ESD devices is analyzed and modeled using a quasi mixed-mode approach. The substrate resistance simulated by this method shows good agreement with the values extracted from experimental data. This technique can be employed to simulate turn-on characteristics of ESD protection devices and determine the impact of process and layout variations on their reliability before fabrication of the actual devices.
{"title":"Process and layout dependent substrate resistance modeling for deep sub-micron ESD protection devices","authors":"X.Y. Zhang, K. Banerjee, A. Amerasekera, V. Gupta, Zhiping Yu, R. Dutton","doi":"10.1109/RELPHY.2000.843930","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843930","url":null,"abstract":"This paper demonstrates a new methodology for bringing accurate substrate resistance modeling into circuit level ESD simulation. The impact of layout and process variations on the effective substrate resistance of deep sub-micron ESD devices is analyzed and modeled using a quasi mixed-mode approach. The substrate resistance simulated by this method shows good agreement with the values extracted from experimental data. This technique can be employed to simulate turn-on characteristics of ESD protection devices and determine the impact of process and layout variations on their reliability before fabrication of the actual devices.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"49 1","pages":"295-303"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84700238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843912
Y. Lee, R. Nachman, K. Seshan, D. Kau, N. Mielke
This work investigated the impact of H/sub 2/ gas in the final annealing cycle of a 5-metal-layer CMOS process and its effect on MOS device behavior in the presence of Al/Ti metallization. The role of H/sub 2/ was evaluated with transistor electrical testing and with gate-oxide stressing, namely, bias-temperature and hot-carrier injection. Both electrical testing and stressing data showed no difference in device behavior when different external H/sub 2/% was used. However, some differences in PMOSFET bias-temp were observed when the annealing cycle was totally eliminated. Moreover, some differences were observed for devices with different metal coverage. This paper details the results and proposes a model to explain the observations.
{"title":"Role of hydrogen anneal in thin gate oxide for multi-metal-layer CMOS process","authors":"Y. Lee, R. Nachman, K. Seshan, D. Kau, N. Mielke","doi":"10.1109/RELPHY.2000.843912","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843912","url":null,"abstract":"This work investigated the impact of H/sub 2/ gas in the final annealing cycle of a 5-metal-layer CMOS process and its effect on MOS device behavior in the presence of Al/Ti metallization. The role of H/sub 2/ was evaluated with transistor electrical testing and with gate-oxide stressing, namely, bias-temperature and hot-carrier injection. Both electrical testing and stressing data showed no difference in device behavior when different external H/sub 2/% was used. However, some differences in PMOSFET bias-temp were observed when the annealing cycle was totally eliminated. Moreover, some differences were observed for devices with different metal coverage. This paper details the results and proposes a model to explain the observations.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"33 1","pages":"186-190"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80117617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843916
M. Makabe, T. Kubota, T. Kitano
We investigated pMOSFET Bias-Temperature (BT) degradation by using carrier separation analysis. Electrons tunneling from gate electrode to substrate were found to cause impact ionization at the SiO/sub 2//Si interface and result in the creation of trapped charges and interface states. A higher-concentration boron incorporation into the SiO/sub 2/ film was found to suppress BT degradation. This is considered to be a result of tunneling electron current suppression. Degradation due to BT can also be suppressed by reducing the electric field in the oxide between the gate electrode and drain. In other words, BT degradation is lower for the ON-state than the OFF-state. The electric field between the gate electrode and drain can also be reduced by changing the side wall formation process.
{"title":"Bias-temperature degradation of pMOSFETs: mechanism and suppression","authors":"M. Makabe, T. Kubota, T. Kitano","doi":"10.1109/RELPHY.2000.843916","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843916","url":null,"abstract":"We investigated pMOSFET Bias-Temperature (BT) degradation by using carrier separation analysis. Electrons tunneling from gate electrode to substrate were found to cause impact ionization at the SiO/sub 2//Si interface and result in the creation of trapped charges and interface states. A higher-concentration boron incorporation into the SiO/sub 2/ film was found to suppress BT degradation. This is considered to be a result of tunneling electron current suppression. Degradation due to BT can also be suppressed by reducing the electric field in the oxide between the gate electrode and drain. In other words, BT degradation is lower for the ON-state than the OFF-state. The electric field between the gate electrode and drain can also be reduced by changing the side wall formation process.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"391 1","pages":"205-209"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75802183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843894
Y. Lee, K. Wu, T. Linton, N. Mielke, S. Hu, B. Wallace
Channel width dependent pMOSFET hot-carrier degradation has been observed for a 0.25 /spl mu/m CMOS technology. A detailed characterization revealed two distinct trapping mechanisms that are unique to both narrow and wide width devices. Device simulations indicate that the electric field difference between the STI edge and channel area is responsible for the channel-width dependent degradation. In addition to data from discrete devices, product burn-in data will also be presented to support the channel-width dependent pMOST degradation mechanism.
{"title":"Channel-width dependent hot-carrier degradation of thin-gate pMOSFETs","authors":"Y. Lee, K. Wu, T. Linton, N. Mielke, S. Hu, B. Wallace","doi":"10.1109/RELPHY.2000.843894","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843894","url":null,"abstract":"Channel width dependent pMOSFET hot-carrier degradation has been observed for a 0.25 /spl mu/m CMOS technology. A detailed characterization revealed two distinct trapping mechanisms that are unique to both narrow and wide width devices. Device simulations indicate that the electric field difference between the STI edge and channel area is responsible for the channel-width dependent degradation. In addition to data from discrete devices, product burn-in data will also be presented to support the channel-width dependent pMOST degradation mechanism.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"10 1","pages":"77-82"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75548275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843936
J. Noguchi, N. Ohashi, J. Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, K. Takeda, K. Hinode
Time-dependent dielectric breakdown (TDDB) between Cu interconnects is investigated. TDDB lifetime strongly depends on the surface condition of the Cu interconnect and surrounding pTEOS. A NH/sub 3/-plamsa treatment prior to cap-pSiN deposition on Cu interconnect improved the dielectric breakdown lifetime (/spl tau//sub BD/) over cap-pSiN deposition only. The plasma treatment also has the beneficial effect of suppressing wiring resistance increase during pSiN deposition. These results suggest that CuO reduction to Cu, and CuN formation at the Cu interconnect surface prevents Cu silicidation during pSiN deposition. Furthermore, SiN formation and bond termination by hydrogen radicals at the pTEOS surface diminish surface defects, such as dangling bonds. TDDB lifetime also strongly depends on the Cu CMP process, in which mechanical damage of the SiO/sub 2/ surface during CMP process degrades TDDB. Adoption of a mechanical damage free slurry or a post-CMP HF treatment to remove the damaged layer from the surface improves TDDB.
{"title":"TDDB improvement in Cu metallization under bias stress","authors":"J. Noguchi, N. Ohashi, J. Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, K. Takeda, K. Hinode","doi":"10.1109/RELPHY.2000.843936","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843936","url":null,"abstract":"Time-dependent dielectric breakdown (TDDB) between Cu interconnects is investigated. TDDB lifetime strongly depends on the surface condition of the Cu interconnect and surrounding pTEOS. A NH/sub 3/-plamsa treatment prior to cap-pSiN deposition on Cu interconnect improved the dielectric breakdown lifetime (/spl tau//sub BD/) over cap-pSiN deposition only. The plasma treatment also has the beneficial effect of suppressing wiring resistance increase during pSiN deposition. These results suggest that CuO reduction to Cu, and CuN formation at the Cu interconnect surface prevents Cu silicidation during pSiN deposition. Furthermore, SiN formation and bond termination by hydrogen radicals at the pTEOS surface diminish surface defects, such as dangling bonds. TDDB lifetime also strongly depends on the Cu CMP process, in which mechanical damage of the SiO/sub 2/ surface during CMP process degrades TDDB. Adoption of a mechanical damage free slurry or a post-CMP HF treatment to remove the damaged layer from the surface improves TDDB.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"60 1","pages":"339-343"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91233943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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