Pub Date : 2000-01-01DOI: 10.1109/RELPHY.2000.843887
J. Wu, E. Rosenbaum, B. MacDonald, E. Li, J. Tao, B. Tracy, P. Fang
Recent studies have shown that post-metallization anneal in deuterium can improve transistor lifetime by one order of magnitude or more. In this paper, we show that the gate oxide reliability of devices annealed in deuterium is similar to that of devices annealed in hydrogen. This finding suggests that a model for gate oxide breakdown which involves release of interfacial hydrogen may not be accurate.
{"title":"Anode hole injection versus hydrogen release: the mechanism for gate oxide breakdown","authors":"J. Wu, E. Rosenbaum, B. MacDonald, E. Li, J. Tao, B. Tracy, P. Fang","doi":"10.1109/RELPHY.2000.843887","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843887","url":null,"abstract":"Recent studies have shown that post-metallization anneal in deuterium can improve transistor lifetime by one order of magnitude or more. In this paper, we show that the gate oxide reliability of devices annealed in deuterium is similar to that of devices annealed in hydrogen. This finding suggests that a model for gate oxide breakdown which involves release of interfacial hydrogen may not be accurate.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"222 1","pages":"27-32"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75179849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-01-01DOI: 10.1109/RELPHY.2000.843897
C.T. Hsu, M. Lau, Y. Yeow, Z. Yao
In this paper we describe and demonstrate the use of gate-to-drain capacitance (C/sub gd/) measurements at cryogenic temperature as a tool to characterize hot-carrier-induced charge centers. Also a new method based on gate-to-substrate capacitance (C/sub gb/), validated by means of two-dimensional numerical simulation, is proposed to extract the spatial distribution of oxide interface charges with reasonable accuracy.
{"title":"Analysis of hot-carrier-induced degradation in MOSFETs by gate-to-drain and gate-to-substrate capacitance measurements","authors":"C.T. Hsu, M. Lau, Y. Yeow, Z. Yao","doi":"10.1109/RELPHY.2000.843897","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843897","url":null,"abstract":"In this paper we describe and demonstrate the use of gate-to-drain capacitance (C/sub gd/) measurements at cryogenic temperature as a tool to characterize hot-carrier-induced charge centers. Also a new method based on gate-to-substrate capacitance (C/sub gb/), validated by means of two-dimensional numerical simulation, is proposed to extract the spatial distribution of oxide interface charges with reasonable accuracy.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"1 1","pages":"98-102"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82937782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-01-01DOI: 10.1109/RELPHY.2000.843932
S. Voldman, P. Juliano, R. Johnson, N. Schmidt, A. Joseph, S. Furkay, E. Rosenbaum, J. Dunn, D. Harame, B. Meyerson
This paper investigates high-current and electrostatic discharge (ESD) phenomenon in pseudomorphic epitaxial-base silicon-germanium (SiGe) heterojunction bipolar transistors (HBT). Transmission line pulse (TLP) and ESD human body model (HBM) wafer-level reliability testing, failure analysis and simulation of SiGe HBT devices is completed for high-current characterization and evaluation of the ESD robustness of a BiCMOS SiGe technology.
{"title":"Electrostatic discharge and high current pulse characterization of epitaxial-base silicon-germanium heterojunction bipolar transistors","authors":"S. Voldman, P. Juliano, R. Johnson, N. Schmidt, A. Joseph, S. Furkay, E. Rosenbaum, J. Dunn, D. Harame, B. Meyerson","doi":"10.1109/RELPHY.2000.843932","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843932","url":null,"abstract":"This paper investigates high-current and electrostatic discharge (ESD) phenomenon in pseudomorphic epitaxial-base silicon-germanium (SiGe) heterojunction bipolar transistors (HBT). Transmission line pulse (TLP) and ESD human body model (HBM) wafer-level reliability testing, failure analysis and simulation of SiGe HBT devices is completed for high-current characterization and evaluation of the ESD robustness of a BiCMOS SiGe technology.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"44 1","pages":"310-316"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89897237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-01-01DOI: 10.1109/RELPHY.2000.843898
E. Li, Elyse Rosenbaum, Leonard F. Register, J. Tao, P. Fang
This work demonstrates that V/sub g/=V/sub d/ is the worst case stress condition for deep submicron NMOSFETs and PMOSFETs operating at 100/spl deg/C. Degradation is more severe at 100/spl deg/C than at room temperature even for supply voltages greater than 2.5 V. The effect of channel length on the substrate current's temperature-dependence is also examined.
{"title":"Hot carrier induced degradation in deep submicron MOSFETs at 100/spl deg/C","authors":"E. Li, Elyse Rosenbaum, Leonard F. Register, J. Tao, P. Fang","doi":"10.1109/RELPHY.2000.843898","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843898","url":null,"abstract":"This work demonstrates that V/sub g/=V/sub d/ is the worst case stress condition for deep submicron NMOSFETs and PMOSFETs operating at 100/spl deg/C. Degradation is more severe at 100/spl deg/C than at room temperature even for supply voltages greater than 2.5 V. The effect of channel length on the substrate current's temperature-dependence is also examined.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"5 1","pages":"103-107"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85298472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-01-01DOI: 10.1109/RELPHY.2000.843929
N. Tošić, F. Kuper, T. Mouthaan
In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (/spl alpha/-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an /spl alpha/-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis.
{"title":"Transmission line model testing of top-gate amorphous silicon thin film transistors","authors":"N. Tošić, F. Kuper, T. Mouthaan","doi":"10.1109/RELPHY.2000.843929","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843929","url":null,"abstract":"In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (/spl alpha/-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an /spl alpha/-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"9 1","pages":"289-294"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88615376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-01-01DOI: 10.1109/RELPHY.2000.843911
Jiann Heng Chen, T. Lei, C. Chen, T. Chao, W. Wen, K. T. Chen
This study demonstrates high performance and reliable deep-submicron n-MOSFETs with ultra-thin gate oxide prepared by combining with nitrogen gate electrode implantation and native-oxide-free in-situ HF vapor pre-oxidation cleaning. Our results indicate that the performance and reliability, including the leakage current of the ultra-thin gate oxide, the drain current (I/sub d/), transconductance (G/sub m/), charge pumping current (I/sub cp/), stress induced leakage current (SILC), and hot carrier reliability of n-MOSFETs with 4 nm thin gate oxides are all significantly improved.
{"title":"High performance deep-submicron n-MOSFETs by nitrogen implantation and in-situ HF vapor clean","authors":"Jiann Heng Chen, T. Lei, C. Chen, T. Chao, W. Wen, K. T. Chen","doi":"10.1109/RELPHY.2000.843911","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843911","url":null,"abstract":"This study demonstrates high performance and reliable deep-submicron n-MOSFETs with ultra-thin gate oxide prepared by combining with nitrogen gate electrode implantation and native-oxide-free in-situ HF vapor pre-oxidation cleaning. Our results indicate that the performance and reliability, including the leakage current of the ultra-thin gate oxide, the drain current (I/sub d/), transconductance (G/sub m/), charge pumping current (I/sub cp/), stress induced leakage current (SILC), and hot carrier reliability of n-MOSFETs with 4 nm thin gate oxides are all significantly improved.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"27 1","pages":"180-185"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87478316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-01-01DOI: 10.1109/RELPHY.2000.843945
Li Shi, O. Kwon, Guanghua Wu, A. Majumdar
Localized Joule heating in submicron features affects reliability of VLSI devices. This paper reports the use of batch-fabricated probes for scanning thermal microscopy (SThM) to characterize self-heating in miniaturized devices. The spatial resolution of the SThM technique is found to be about 70 nm. Existence of a liquid film bridging the tip and sample during scanning is verified and the thermal contact conductance of the liquid bridge is found to be significant. The thermal design of the probe was optimized in previous work and its thermal performance is now characterized. We apply the SThM technique for mapping temperature distribution on VLSI via structures under DC current heating. Excellent agreement was found between the results obtained from the SThM technique and that from a resistive thermometry method. This paper also demonstrates a novel phase imaging technique for locating subsurface hot spots. The subsurface imaging technique has the potential to be used for detecting defects in multilevel interconnects.
{"title":"Quantitative thermal probing of devices at sub-100 nm resolution","authors":"Li Shi, O. Kwon, Guanghua Wu, A. Majumdar","doi":"10.1109/RELPHY.2000.843945","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843945","url":null,"abstract":"Localized Joule heating in submicron features affects reliability of VLSI devices. This paper reports the use of batch-fabricated probes for scanning thermal microscopy (SThM) to characterize self-heating in miniaturized devices. The spatial resolution of the SThM technique is found to be about 70 nm. Existence of a liquid film bridging the tip and sample during scanning is verified and the thermal contact conductance of the liquid bridge is found to be significant. The thermal design of the probe was optimized in previous work and its thermal performance is now characterized. We apply the SThM technique for mapping temperature distribution on VLSI via structures under DC current heating. Excellent agreement was found between the results obtained from the SThM technique and that from a resistive thermometry method. This paper also demonstrates a novel phase imaging technique for locating subsurface hot spots. The subsurface imaging technique has the potential to be used for detecting defects in multilevel interconnects.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"41 1","pages":"394-398"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72778031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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