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2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)最新文献

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Single contact optical beam induced currents (SCOBIC)-a new failure analysis technique 单接触光束感应电流(SCOBIC)是一种新的失效分析技术
J. Chin, J. Phang, D. Chan, C. E. Soh, G. Gilfeather
The Single Contact Optical Beam Induced Currents (SCOBIC) is a new failure analysis technique. By connecting the substrate or power pins of an integrated circuit to the current amplifier, many junctions can be imaged. In contrast, in the optical beam induced current (OBIC) technique, only the junction directly connected to the current amplifier is imaged. The implementation of the SCOBIC approach is discussed and experimental results which validates the SCOBIC approach is presented. Application of the SCOBIC technique for CMOS devices is also discussed.
单接触光束感应电流(SCOBIC)是一种新的失效分析技术。通过将集成电路的衬底或电源引脚连接到电流放大器,可以对许多结进行成像。相比之下,在光束感应电流(OBIC)技术中,只有直接连接到电流放大器的结被成像。讨论了SCOBIC方法的实现,并给出了验证SCOBIC方法的实验结果。讨论了SCOBIC技术在CMOS器件中的应用。
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引用次数: 11
Evidence for recombination at oxide defects and new SILC model 氧化物缺陷处重组的证据和新的SILC模型
D. Ielmini, A.S. Spinellii, A. Lacaita, G. Ghidini
This work presents experimental and computational investigations on the physical mechanisms of SILC. Carrier separation measurements are carried out on MOS samples with oxide thickness 6-8 nm, highlighting the electron and hole contributions to the SILC. We have investigated the relation between these components by means of time-relaxation. It is found that a linear relationship holds between electron SILC and hole SILC, measured at different times after the initial high-field stress. The same linearity has been observed for increasing fluences of injected electrons, at fixed stressing field. A correlation between electron and hole ILC is found also from a comparison between carrier separation data obtained in n/sup +/- and p/sup +/- polysilicon devices. These experimental data entails that hole SILC is due to a recombination current. As a result of these experimental findings, a new model for the SILC is developed. This model is based on trap-assisted tunneling, but also accounts for hole tunneling and includes Shockley-Hall-Read recombination process in the bulk oxide as a new leakage mechanism. Simulations in the oxide thickness range 5.9-8.2 nm show excellent agreement with I-V measurements and carrier-separation data. The resulting defect concentration scales with the oxide thickness, in agreement with published results. The energy distribution of defects responsible for the steady-state leakage is located 0.7-1.3 eV below the Si conduction-band minimum. Capture cross sections of 10/sup -13/ and 10/sup -16/ cm/sup 2/ have been assumed for electrons and holes respectively, compatible with a donor charge state of the SILC-related defect centers. Simulations are finally shown for oxide thickness t/sub 0x/=2.8 nm. The mechanism of recombination in the bulk oxide accounts very well for the observation of low-voltage SILC in ultrathin oxide, showing the effectiveness of the proposed SILC model.
这项工作提出了对SILC的物理机制的实验和计算研究。在氧化厚度为6-8 nm的MOS样品上进行了载流子分离测量,突出了电子和空穴对SILC的贡献。我们用时间松弛的方法研究了这些分量之间的关系。发现在初始高场应力后不同时间测量的电子硅固相密度与空穴硅固相密度之间存在线性关系。在固定应力场下,注入电子的影响增加,也观察到同样的线性关系。通过比较n/sup +/-和p/sup +/-多晶硅器件的载流子分离数据,发现了电子和空穴ILC之间的相关性。这些实验数据表明,空穴SILC是由复合电流引起的。基于这些实验结果,我们建立了一个新的SILC模型。该模型基于陷阱辅助隧道作用,但也考虑了空穴隧道作用,并将块体氧化物中的Shockley-Hall-Read复合过程作为一种新的泄漏机制。在5.9 ~ 8.2 nm的氧化厚度范围内的模拟结果与I-V测量值和载流子分离数据非常吻合。所得到的缺陷浓度与氧化物厚度成正比,与已发表的结果一致。导致稳态泄漏的缺陷能量分布在硅导带最小值以下0.7 ~ 1.3 eV。假设电子和空穴的俘获截面分别为10/sup -13/和10/sup -16/ cm/sup 2/,与silc相关缺陷中心的供体电荷态相容。最后给出了氧化层厚度t/sub =2.8 nm时的模拟结果。体氧化物中的复合机制很好地解释了超薄氧化物中低压硅碳交换的观察结果,表明了所提出的硅碳交换模型的有效性。
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引用次数: 10
Early stage hot carrier degradation of state-of-the-art LDD N-MOSFETs 最新LDD n - mosfet的早期热载流子退化
S. K. Manhas, M. M. De Souza, A. S. Gates, S. Chetlur, E. M. Sankara Narayanan
A detailed investigation of the hot carrier degradation of submicron LDD n-MOSFETs reveals a new early stage degradation regime, which deviates from power law behaviour. The quantitative analysis obtained through extraction of drain series resistance and mobility shows a two-stage drain series resistance degradation. For the first time, the degradation in the spacer region is clearly distinguished from that in the channel region of the device. For the technologies under investigation, the damage is seen to spread to the channel within 10 seconds, far earlier than reported in the literature.
对亚微米LDD n- mosfet的热载流子降解进行了详细的研究,揭示了一种偏离幂律行为的新的早期降解机制。通过提取漏系电阻和迁移率的定量分析表明,漏系电阻的退化是两阶段的。第一次,在间隔区域的退化明显区别于在器件的通道区域。对于正在研究的技术,损害可以在10秒内扩散到通道,远远早于文献报道。
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引用次数: 8
Quasi-breakdown in ultra-thin SiO/sub 2/ films: occurrence characterization and reliability assessment methodology 超薄SiO/ sub2 /薄膜的准击穿:发生特征和可靠性评估方法
S. Bruyère, E. Vincent, G. Ghibaudo
This paper discusses different statistical approaches for the quasi-breakdown phenomenon. In particular, a novel methodology based on the idea that breakdown and quasi-breakdown are competing mechanisms and that they have to be separately analyzed, is developed and well validated for oxide thickness ranging from 3.5 down to 2.5 nm. This methodology is demonstrated to well explain all the quasi-breakdown rate variations with temperature, voltage, area and oxide thickness. Moreover, this new approach enables to rigorously determine the quasi-breakdown acceleration factor with temperature and electric field, which have been found to be different from the breakdown ones. As a result, and confirmed by the difference observed between the obtained time to breakdown and time to quasi-breakdown spreads, the defects at the origin of both phenomena have to be different. Finally, a reliability assessment methodology is presented enabling a proper analysis of both phenomena for reliability evaluation and lifetime prediction.
本文讨论了拟击穿现象的不同统计方法。特别是,基于击穿和准击穿是相互竞争的机制,它们必须单独分析的想法,开发了一种新的方法,并在从3.5到2.5 nm的氧化物厚度范围内得到了很好的验证。该方法被证明可以很好地解释所有准击穿率随温度、电压、面积和氧化物厚度的变化。此外,该方法还可以严格地确定温度和电场对准击穿加速因子的影响,这与击穿加速因子不同。因此,得到的击穿时间和准击穿扩散时间之间的差异证实了这一点,即两种现象起源处的缺陷一定是不同的。最后,提出了一种可靠性评估方法,该方法能够对可靠性评估和寿命预测两种现象进行适当的分析。
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引用次数: 36
Nontactile reliability testing of a micro optical attenuator 微光衰减器的非触觉可靠性测试
C. Rembe, H. Aschemann, S. aus der Wiesche, E. Hofer, H. Debéda, J. Mohr, U. Wallrabe
The reliability investigations presented in this paper have been performed on a micro opto electro mechanical switch developed for switching and attenuation of light propagation in optical fibers. It is demonstrated that high-speed cine photomicrography together with model based evaluation of the image sequences is a powerful diagnostic tool for reliability testing of dynamic processes in micro electro mechanical systems (MEMS).
本文对一种用于光纤中光传播的开关和衰减的微光电开关进行了可靠性研究。结果表明,高速电影显微成像技术与基于模型的图像序列评价技术是微机电系统(MEMS)动态过程可靠性测试的有力诊断工具。
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引用次数: 3
Analysis of oxide breakdown mechanism occurring during ESD pulses ESD脉冲中氧化物击穿机理分析
C. Leroux, P. Andreucci, G. Reimbold
In new technologies, concern for oxide breakdown during ESD (ElectroStatic Discharge) is becoming more and more important. It is usually evaluated using the classical 1/E law for the time to breakdown. In this study, we report different experiments demonstrating that this model for the time to breakdown need to be improved in the case of ESD stresses. A model for the conduction at these high current densities is proposed. The times to breakdown are analyzed on a large range of current densities. We show that we must take into account the effects of current crowding, electrical breakdown, temperature increase during the pulse and thermal breakdown to understand the failure mechanisms. A model is proposed to evaluate the heating during the ESD pulses and to predict the oxide strength.
在新技术中,对静电放电过程中氧化物击穿的关注越来越受到重视。通常使用经典的1/E定律来评估故障时间。在这项研究中,我们报告了不同的实验,表明在ESD应力的情况下,该模型需要改进击穿时间。提出了高电流密度下的导电模型。在较大的电流密度范围内分析了击穿时间。研究表明,必须考虑电流拥挤、电击穿、脉冲温度升高和热击穿的影响,才能理解失效机制。提出了一个模型来评估静电放电脉冲期间的加热和预测氧化物强度。
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引用次数: 18
Reliability studies of bent-beam electro-thermal actuators 弯梁电热致动器可靠性研究
L. Que, Jaesung Park, Mo-Huang Li, Y. Gianchandani
This paper reports on the first lifetime studies of the recently developed bent-beam electro-thermal microactuators. Measurements of p/sup ++/ Si bulk micromachined devices under varying operating conditions reveal that device lifetimes and degradation patterns are linked to actuation conditions as well as certain dimensional parameters. Device lifetimes in excess of 30 million cycles are observed. A model similar to that used for fatigue of steel is shown to be very suitable for predicting performance degradation. The model parameters are explored as a function of operating conditions.
本文报道了最近研制的弯梁电热微致动器的首次寿命研究。在不同操作条件下对p/sup ++/ Si体微机械器件的测量表明,器件寿命和降解模式与驱动条件以及某些尺寸参数有关。据观察,设备寿命超过3000万次。与钢的疲劳模型相似的模型被证明是非常适合预测性能退化的。研究了模型参数随工况的变化规律。
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引用次数: 17
Reliability assessment through defect based testing 通过基于缺陷的测试进行可靠性评估
B. Lisenker, Y. Mitnick
In this paper it is shown that a small linear variation of poly critical dimensions, effective channel length, and transistor threshold voltage caused by non-controlled process variations will result in an exponential variation in the of state conductivity of a transistor. For the first time, it is shown, that the application of the percolation theory makes it possible to integrate the contribution of short channel MOSFET's to the standby current of deep-sub-micron CMOS microprocessors taking into consideration the above process variations. It is proved that a Fault model, which consists of an equivalent effective MOSFET with inherent defects, can represent a CMOS VLSI circuit in standby mode. The model permits the use of standby current versus voltage test results for screening, built-in reliability and the process monitoring. The viability of this model is examined on 32-bit 0.25 /spl mu/m CMOS microprocessors. Results obtained on the product line confirm the model and show a strong correlation between rejected devices and infant mortality failures.
本文表明,由非受控工艺变化引起的多临界尺寸、有效沟道长度和晶体管阈值电压的微小线性变化将导致晶体管的状态电导率呈指数变化。第一次表明,渗透理论的应用使得考虑上述工艺变化的情况下集成短沟道MOSFET对深亚微米CMOS微处理器待机电流的贡献成为可能。证明了一个由等效的有效MOSFET和固有缺陷组成的故障模型可以表示待机状态下的CMOS VLSI电路。该模型允许使用备用电流对电压测试结果进行筛选,内置可靠性和过程监控。在32位0.25 /spl mu/m CMOS微处理器上检验了该模型的可行性。在生产线上获得的结果证实了该模型,并显示出被拒绝的设备与婴儿死亡率失败之间存在很强的相关性。
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引用次数: 10
Lifetime prediction of IGBT modules for traction applications 牵引应用IGBT模块寿命预测
M. Ciappa, W. Fichtner
Bond wire lift-off caused by low-cycle fatigue is one among the dominant failure mechanisms of modern high power Insulated Gate Bipolar Transistors multichip modules used in traction applications. A model is proposed which is calibrated basing on data from accelerated tests and which predicts quantitatively the lifetime of devices submitted to cyclic loads as they are encountered in current converters of railway systems. It assumes linear accumulation of the thermal-cycle fatigue damage and takes into account the redundancy of the bond wires within a complex multichip module.
低周疲劳引起的键线脱落是现代牵引用大功率绝缘栅双极晶体管多芯片模块的主要失效机制之一。提出了一个基于加速试验数据标定的模型,该模型定量地预测了铁路系统变流器中装置在循环荷载作用下的寿命。它假设热循环疲劳损伤的线性累积,并考虑了复杂多芯片模块中焊线的冗余性。
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引用次数: 96
Multi parameter method for yield analysis and reliability assessment 成品率分析和可靠性评估的多参数方法
Y. Mitnick, B. Lisenker, U. Sasson, R. Miller
Parametric failure is becoming the main reason of yield/reliability loss in new products. Microprocessors on 0.35 /spl mu/m and 0.25 /spl mu/m processes show a high level of parametric (soft) failure. We propose to introduce a parametric process-to-design baseline by using basic physical relations of integrated product parameters and transistor level parameters as a function of systematic process instabilities on the die/wafer level. The deviations from the baseline are caused by process-related defects that impact yield and reliability. We have introduced a new multi-parameter method in order to calculate this deviation and separate between parametric systematic defects and random defects. The analysis of >700 K 0.25 /spl mu/m microprocessor units showed that >16% of the units that have high deviation failed in burn-in (BI). The analysis of excursion material showed that the yield in subgroups of the units is a strong function of the deviation from the baseline. The new methodology enables the impact of process variation sources on product yield reliability and performance to be assessed.
参数失效已成为新产品成品率/可靠性损失的主要原因。在0.35 /spl mu/m和0.25 /spl mu/m进程上的微处理器显示出高水平的参数(软)故障。我们建议将集成产品参数和晶体管级参数的基本物理关系作为芯片/晶圆级系统工艺不稳定性的函数,引入参数化工艺到设计基线。与基线的偏差是由影响产量和可靠性的过程相关缺陷引起的。我们引入了一种新的多参数方法来计算这种偏差,并将参数系统缺陷与随机缺陷区分开来。对>700 K 0.25 /spl mu/m微处理器单元的分析表明,>16%的高偏差单元在老化(BI)中失败。对偏移材料的分析表明,单元亚组的产率与基线偏差有很强的关系。新方法使过程变异源对产品良率可靠性和性能的影响得以评估。
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引用次数: 5
期刊
2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)
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