Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843914
H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Kume, K. Okuyama, Y. Manabe, A. Nozoe, H. Uchida, M. Hidaka, K. Ogura
We propose a new data retention model after endurance stress that may be explained as a combination of two retention mechanisms. One inherent retention characteristic is ruled by thermionic emission and is dominant above 150 C. The other retention mechanism is dominant below 85 to 125 C and is controlled by anomalous SILC. We have clarified that the data retention properties after P/E cycling were well fitted by the hopping conduction model. In particular, the presence of traps generated by excessive P/E cycling played a significant role in the temperature dependence of the retention lifetime.
{"title":"A new data retention mechanism after endurance stress on flash memory","authors":"H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Kume, K. Okuyama, Y. Manabe, A. Nozoe, H. Uchida, M. Hidaka, K. Ogura","doi":"10.1109/RELPHY.2000.843914","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843914","url":null,"abstract":"We propose a new data retention model after endurance stress that may be explained as a combination of two retention mechanisms. One inherent retention characteristic is ruled by thermionic emission and is dominant above 150 C. The other retention mechanism is dominant below 85 to 125 C and is controlled by anomalous SILC. We have clarified that the data retention properties after P/E cycling were well fitted by the hopping conduction model. In particular, the presence of traps generated by excessive P/E cycling played a significant role in the temperature dependence of the retention lifetime.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"35 1","pages":"194-199"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89218769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843900
L. Sheng, C. De Tandt, W. Ranson, R. Vounckx
This paper discusses the reliability characterization of thermal microstructures implemented on industrial 0.8 /spl mu/m CMOS chips. Various degradation and failure mechanisms are identified and evaluated under high temperature operation. The results can be used to optimize the design of thermally based microsensors on CMOS chips.
本文讨论了在工业0.8 /spl μ m CMOS芯片上实现的热微结构的可靠性表征。在高温运行下，识别和评估了各种退化和失效机制。研究结果可用于优化基于CMOS芯片的热传感器设计。
{"title":"Reliability characterization of thermal micro-structures implemented on 0.8 /spl mu/m CMOS chips","authors":"L. Sheng, C. De Tandt, W. Ranson, R. Vounckx","doi":"10.1109/RELPHY.2000.843900","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843900","url":null,"abstract":"This paper discusses the reliability characterization of thermal microstructures implemented on industrial 0.8 /spl mu/m CMOS chips. Various degradation and failure mechanisms are identified and evaluated under high temperature operation. The results can be used to optimize the design of thermally based microsensors on CMOS chips.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"21 1","pages":"112-117"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78794880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843942
A. Zanchi, F. Zappa, M. Ghioni, A. P. Morrison
We present process probes useful to investigate the process-dependent quality of p-n junctions in semiconductors. The probes are sensitive to the presence of thermal generation centers, which ignite macroscopic current avalanches. Since the carrier generation events are promoted by the presence of localized imperfections such as dislocations, stacking faults, etc., the avalanche ignition rate represents a suitable figure of merit for ranking the overall process cleanliness. In particular, by using these probes we report a nonuniform distribution of lattice defects within certain junctions. This phenomenon has been verified by means of standard etching and infrared optical inspection. Some technological hints are finally provided, capable of reducing the defectivity and improving the fabrication of microelectronic devices.
{"title":"On-chip probes for silicon defectivity ranking and mapping","authors":"A. Zanchi, F. Zappa, M. Ghioni, A. P. Morrison","doi":"10.1109/RELPHY.2000.843942","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843942","url":null,"abstract":"We present process probes useful to investigate the process-dependent quality of p-n junctions in semiconductors. The probes are sensitive to the presence of thermal generation centers, which ignite macroscopic current avalanches. Since the carrier generation events are promoted by the presence of localized imperfections such as dislocations, stacking faults, etc., the avalanche ignition rate represents a suitable figure of merit for ranking the overall process cleanliness. In particular, by using these probes we report a nonuniform distribution of lattice defects within certain junctions. This phenomenon has been verified by means of standard etching and infrared optical inspection. Some technological hints are finally provided, capable of reducing the defectivity and improving the fabrication of microelectronic devices.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"1 1","pages":"370-376"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83057257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843888
J. Suehle, E. Vogel, Bin Wang, J. Bernstein
A comprehensive time-dependent dielectric breakdown study was conducted on sub-3 nm SiO/sub 2/ films over a temperature range from 22/spl deg/C to 350/spl deg/C. Two breakdown modes were observed in current versus time characteristics and low voltage I-V curves depending on device area and stress voltage. Larger device areas and lower stress voltage produced higher occurrences of soft/noisy breakdown events while smaller device areas and larger stress voltages produced harder/thermal breakdown events. Stress temperature did not affect the breakdown mode. The results indicate that both breakdown modes exhibit the same thermal acceleration if the first occurrence of current noise is used as a breakdown criteria for those devices exhibiting noisy breakdown. The observed strong dependence of the thermal activation energy on gate voltage may explain previous reports of increased temperature acceleration for ultra-thin films.
{"title":"Temperature dependence of soft breakdown and wear-out in sub-3 nm SiO/sub 2/ films","authors":"J. Suehle, E. Vogel, Bin Wang, J. Bernstein","doi":"10.1109/RELPHY.2000.843888","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843888","url":null,"abstract":"A comprehensive time-dependent dielectric breakdown study was conducted on sub-3 nm SiO/sub 2/ films over a temperature range from 22/spl deg/C to 350/spl deg/C. Two breakdown modes were observed in current versus time characteristics and low voltage I-V curves depending on device area and stress voltage. Larger device areas and lower stress voltage produced higher occurrences of soft/noisy breakdown events while smaller device areas and larger stress voltages produced harder/thermal breakdown events. Stress temperature did not affect the breakdown mode. The results indicate that both breakdown modes exhibit the same thermal acceleration if the first occurrence of current noise is used as a breakdown criteria for those devices exhibiting noisy breakdown. The observed strong dependence of the thermal activation energy on gate voltage may explain previous reports of increased temperature acceleration for ultra-thin films.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"17 1","pages":"33-39"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88434200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843926
G. Meneghesso, S. Santirosi, E. Novarini, C. Contiero, E. Zanoni
In this paper we will present data concerning the ESD robustness of smart power protection structures (fabricated in Bipolar, CMOS, DMOS, BCD technology) for input-output circuits. A comparison between the robustness of "p-body" and "p-well" based structures and a study of the influence of layout parameters on the ESD robustness will be given. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented. Failure analysis has been carried out by means of SEM device cross-sections.
{"title":"ESD robustness of smart-power protection structures evaluated by means of HBM and TLP tests","authors":"G. Meneghesso, S. Santirosi, E. Novarini, C. Contiero, E. Zanoni","doi":"10.1109/RELPHY.2000.843926","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843926","url":null,"abstract":"In this paper we will present data concerning the ESD robustness of smart power protection structures (fabricated in Bipolar, CMOS, DMOS, BCD technology) for input-output circuits. A comparison between the robustness of \"p-body\" and \"p-well\" based structures and a study of the influence of layout parameters on the ESD robustness will be given. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented. Failure analysis has been carried out by means of SEM device cross-sections.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"16 1","pages":"270-275"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88490948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843933
M. Tammaro
The effect of a Cu-vacancy binding energy on electromigration transport in Al-Cu alloys is studied in detail. A lattice-gas model for electromigration is developed which accounts for the Cu-vacancy binding energy. Expressions for the diffusion coefficients are derived in the limit of low vacancy concentrations and calculated using Monte Carlo simulations. The diffusion equations are solved for the failure times and concentration profiles. Our results show that for a binding energy of about 0.2 eV there is a dramatic increase in the failure time for copper doping levels of only 1%. The concentration profiles are consistent with 'incubation time' phenomena in experiments where the copper is found to drift away from the blocking boundary before failure occurs.
{"title":"The role of copper in electromigration: the effect of a Cu-vacancy binding energy","authors":"M. Tammaro","doi":"10.1109/RELPHY.2000.843933","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843933","url":null,"abstract":"The effect of a Cu-vacancy binding energy on electromigration transport in Al-Cu alloys is studied in detail. A lattice-gas model for electromigration is developed which accounts for the Cu-vacancy binding energy. Expressions for the diffusion coefficients are derived in the limit of low vacancy concentrations and calculated using Monte Carlo simulations. The diffusion equations are solved for the failure times and concentration profiles. Our results show that for a binding energy of about 0.2 eV there is a dramatic increase in the failure time for copper doping levels of only 1%. The concentration profiles are consistent with 'incubation time' phenomena in experiments where the copper is found to drift away from the blocking boundary before failure occurs.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"36 1","pages":"317-323"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89132790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843928
Kaustav Banerjee, Dae-Yong Kim, A. Amerasekera, Chenming Hu, S. S. Wong, Kenneth E. Goodson
This work presents a detailed microanalysis of interconnect failure mechanisms under short-pulse stress conditions arising during peak current and electrostatic discharge (ESD) events. TEM and SEM analysis have been used to show that passivated AlCu lines can undergo localized melting and voiding under sub-critical current pulses that heat the lines well past their melting point but below a critical failure temperature causing open circuit failures. It is observed that the damage caused by the melting and voiding remains latent since no physical evidence of damage can be detected under optical microscope and no change in the electrical resistance of these lines can be measured. The voids observed under TEM and SEM result from electromigration under very high current densities and high temperature. TEM diffraction patterns confirm that the molten regions exhibit smaller grain sizes, which are introduced as a result of rapid resolidification from a molten state. A thermomechanical model has also been formulated to account for the open circuit failure mode at which the passivation layers are fractured.
{"title":"Microanalysis of VLSI interconnect failure modes under short-pulse stress conditions","authors":"Kaustav Banerjee, Dae-Yong Kim, A. Amerasekera, Chenming Hu, S. S. Wong, Kenneth E. Goodson","doi":"10.1109/RELPHY.2000.843928","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843928","url":null,"abstract":"This work presents a detailed microanalysis of interconnect failure mechanisms under short-pulse stress conditions arising during peak current and electrostatic discharge (ESD) events. TEM and SEM analysis have been used to show that passivated AlCu lines can undergo localized melting and voiding under sub-critical current pulses that heat the lines well past their melting point but below a critical failure temperature causing open circuit failures. It is observed that the damage caused by the melting and voiding remains latent since no physical evidence of damage can be detected under optical microscope and no change in the electrical resistance of these lines can be measured. The voids observed under TEM and SEM result from electromigration under very high current densities and high temperature. TEM diffraction patterns confirm that the molten regions exhibit smaller grain sizes, which are introduced as a result of rapid resolidification from a molten state. A thermomechanical model has also been formulated to account for the open circuit failure mode at which the passivation layers are fractured.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"115 1","pages":"283-288"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74331862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843913
M. Okandan, S. Fonash, B. Maiti, H. Tseng, P. Tobin
Evolution to quasi-breakdown with constant current stressing, annealing behavior and response to further post-quasi-breakdown stressing are observed in 30 /spl Aring/ (measured by ellipsometry) furnace grown oxide and oxynitride samples. The innate behavior of the dielectrics is clearly demonstrated in the wear-out/failure stage with these measurements and anneals. Devices tested are NMOS transistors with channel width of 15 /spl mu/m and lengths ranging from 15 to 0.225 /spl mu/m.
{"title":"Analysis of evolution to and beyond quasi-breakdown in ultra-thin oxide and oxynitride","authors":"M. Okandan, S. Fonash, B. Maiti, H. Tseng, P. Tobin","doi":"10.1109/RELPHY.2000.843913","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843913","url":null,"abstract":"Evolution to quasi-breakdown with constant current stressing, annealing behavior and response to further post-quasi-breakdown stressing are observed in 30 /spl Aring/ (measured by ellipsometry) furnace grown oxide and oxynitride samples. The innate behavior of the dielectrics is clearly demonstrated in the wear-out/failure stage with these measurements and anneals. Devices tested are NMOS transistors with channel width of 15 /spl mu/m and lengths ranging from 15 to 0.225 /spl mu/m.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"8 1","pages":"191-193"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89019189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843924
D. Dieci, R. Menozzi, T. Tomasi, G. Sozzi, C. Lanzieri, C. Canali
This work shows data of hot electron degradation of power AlGaAs/GaAs HFETs and uses them to infer general indications on the bias point dependence of the device degradation, the meaningfulness of the breakdown voltage figure of merit and the physical phenomena taking place in the devices during the stress.
{"title":"Breakdown and degradation issues and the choice of a safe load line for power HFET operation","authors":"D. Dieci, R. Menozzi, T. Tomasi, G. Sozzi, C. Lanzieri, C. Canali","doi":"10.1109/RELPHY.2000.843924","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843924","url":null,"abstract":"This work shows data of hot electron degradation of power AlGaAs/GaAs HFETs and uses them to infer general indications on the bias point dependence of the device degradation, the meaningfulness of the breakdown voltage figure of merit and the physical phenomena taking place in the devices during the stress.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"68 1","pages":"258-263"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89348659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843908
Sung-Kye Park, M. Suh, Jae-Young Kim, G. Yoon, S. Jang
In this paper, we intensively investigate CMOSFET characteristics induced by moisture diffusion from the ILD layer in 0.23 um DRAM with STI and COB (Capacitor Over Bit-line) structure. The representative phenomena are the anomalous short channel hump effect of the nMOSFET and the degradation of the short channel margin for CMOSFET. From our extensive experimental results, we obviously found that the origin of the short channel humps was due to the boron segregation at the Si/SiO/sub 2/ interface of the STI edge region by oxygen components in the moisture diffused from the ILD film combined with the capping SiN film, and short channel margin degradation due to the oxidation enhanced diffusion of boron. In order to explain the anomalous hump phenomena we propose a new quantitative hump model, and suggest the hump suppression method using the barrier SiN film before ILD. Additionally, we perform the evaluation of hot carrier lifetime for each sample.
在本文中，我们深入研究了具有STI和COB(电容过位线)结构的0.23 um DRAM中ILD层的水分扩散引起的CMOSFET特性。具有代表性的现象是nMOSFET的异常短沟道驼峰效应和CMOSFET的短沟道裕度退化。从我们广泛的实验结果中，我们明显地发现，短通道峰的起源是由于从ILD膜中扩散的水分中的氧成分与封盖的SiN膜结合在STI边缘区域的Si/SiO/sub 2/界面处产生的硼偏析，以及由于硼的氧化增强扩散而导致的短通道边缘降解。为了解释异常驼峰现象，我们提出了一种新的定量驼峰模型，并提出了在ILD前利用势垒SiN膜抑制驼峰的方法。此外，我们对每个样品的热载流子寿命进行了评估。
{"title":"CMOSFET characteristics induced by moisture diffusion from inter-layer dielectric in 0.23 um DRAM technology with shallow trench isolation","authors":"Sung-Kye Park, M. Suh, Jae-Young Kim, G. Yoon, S. Jang","doi":"10.1109/RELPHY.2000.843908","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843908","url":null,"abstract":"In this paper, we intensively investigate CMOSFET characteristics induced by moisture diffusion from the ILD layer in 0.23 um DRAM with STI and COB (Capacitor Over Bit-line) structure. The representative phenomena are the anomalous short channel hump effect of the nMOSFET and the degradation of the short channel margin for CMOSFET. From our extensive experimental results, we obviously found that the origin of the short channel humps was due to the boron segregation at the Si/SiO/sub 2/ interface of the STI edge region by oxygen components in the moisture diffused from the ILD film combined with the capping SiN film, and short channel margin degradation due to the oxidation enhanced diffusion of boron. In order to explain the anomalous hump phenomena we propose a new quantitative hump model, and suggest the hump suppression method using the barrier SiN film before ILD. Additionally, we perform the evaluation of hot carrier lifetime for each sample.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"1 1","pages":"164-168"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81932463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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