Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243330
Y. Shuto, S. Yamamoto, S. Sugahara
Static noise margins (SNMs) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNMs as an optimized 6T-SRAM cell. SNMs for other recently-proposed NV-SRAM cells using STT-MTJs were also evaluated, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode.
{"title":"Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs","authors":"Y. Shuto, S. Yamamoto, S. Sugahara","doi":"10.1109/SNW.2012.6243330","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243330","url":null,"abstract":"Static noise margins (SNMs) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNMs as an optimized 6T-SRAM cell. SNMs for other recently-proposed NV-SRAM cells using STT-MTJs were also evaluated, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89087947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243297
Wei Du, D. Putranto, H. Satoh, A. Ono, P. Priambodo, D. Hartanto, H. Inokawa
Optoelectrical method to evaluate the lifetime of single holes in SOI MOSFET is presented, in which the device is illuminated with a continuous light and the histograms of the digitized drain current is analyzed. It was found that smaller number of holes and the higher transverse electric field greatly enhance the hole lifetime.
{"title":"Optoelectrical lifetime evaluation of single holes in SOI MOSFET","authors":"Wei Du, D. Putranto, H. Satoh, A. Ono, P. Priambodo, D. Hartanto, H. Inokawa","doi":"10.1109/SNW.2012.6243297","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243297","url":null,"abstract":"Optoelectrical method to evaluate the lifetime of single holes in SOI MOSFET is presented, in which the device is illuminated with a continuous light and the histograms of the digitized drain current is analyzed. It was found that smaller number of holes and the higher transverse electric field greatly enhance the hole lifetime.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"10 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90876587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243285
C. Jung-Kubiak, J. Gill, T. Reck, C. Lee, J. Siles, G. Chattopadhyay, R. Lin, K. Cooper, I. Mehdi
Silicon micromachining technology is naturally suited for making THz components, where precision and accuracy are essentials. We report here the development of robust micromachining techniques to enable novel active and passive components in the submillimeter-wave region. These features will enable large format submillimeter-wave heterodyne arrays and 3-D integration in the THz region, where fabricating circuits and structures becomes difficult with conventional machining.
{"title":"Silicon microfabrication technologies for THz applications","authors":"C. Jung-Kubiak, J. Gill, T. Reck, C. Lee, J. Siles, G. Chattopadhyay, R. Lin, K. Cooper, I. Mehdi","doi":"10.1109/SNW.2012.6243285","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243285","url":null,"abstract":"Silicon micromachining technology is naturally suited for making THz components, where precision and accuracy are essentials. We report here the development of robust micromachining techniques to enable novel active and passive components in the submillimeter-wave region. These features will enable large format submillimeter-wave heterodyne arrays and 3-D integration in the THz region, where fabricating circuits and structures becomes difficult with conventional machining.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"74 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80946270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243283
A. Balandin, S. Rumyantsev, G. Liu, M. Shur, R. Potyrailo
The low-frequency 1/f noise in graphene transistors has been studied extensively owing to the proposed graphene applications in analog devices and communication systems [1-5]. The studies were motivated by the fact that the low-frequency noise can be up-converted by device nonlinearity and contribute to the phase noise of the system. Similarly, the sensor sensitivity is often limited by the electronic low-frequency noise. Therefore, noise is usually considered as one of the main limiting factors for the device or overall system operation. However, the electronic noise spectrum itself can be used as a sensing parameter increasing the sensor sensitivity and selectivity. Here, we show that vapors of different chemicals produce distinguishably different effects on the low-frequency noise spectra of the graphene-on-Si transistor. Our study showed that some gases change the electrical resistance of pristine graphene devices without changing their low-frequency noise spectra while other gases modify the noise spectra by inducing Lorentzian components with distinctive features. The characteristic corner frequency fC of the Lorentzian noise bulges in graphene devices is different for different chemicals and varies from fC=10 - 20 Hz for tetrahydrofuran to fC=1300 - 1600 Hz for chloroform. We tested the selected set of chemicals vapors on different graphene device samples and alternated different vapors for the same samples. The obtained results indicate that 1/f noise in combination with other sensing parameters can allow one to achieve the selective gas sensing with a single pristine graphene transistor. Our method of gas sensing with graphene does not require graphene surface functionalization or fabrication of an array of the devices with each tuned to a certain chemical. The observation of the Lorentzian components in the vapor-exposed graphene can also help in developing an accurate theoretical description of the noise mechanism in graphene.
{"title":"Selective gas sensing with a single graphene-on-silicon transistor","authors":"A. Balandin, S. Rumyantsev, G. Liu, M. Shur, R. Potyrailo","doi":"10.1109/SNW.2012.6243283","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243283","url":null,"abstract":"The low-frequency 1/f noise in graphene transistors has been studied extensively owing to the proposed graphene applications in analog devices and communication systems [1-5]. The studies were motivated by the fact that the low-frequency noise can be up-converted by device nonlinearity and contribute to the phase noise of the system. Similarly, the sensor sensitivity is often limited by the electronic low-frequency noise. Therefore, noise is usually considered as one of the main limiting factors for the device or overall system operation. However, the electronic noise spectrum itself can be used as a sensing parameter increasing the sensor sensitivity and selectivity. Here, we show that vapors of different chemicals produce distinguishably different effects on the low-frequency noise spectra of the graphene-on-Si transistor. Our study showed that some gases change the electrical resistance of pristine graphene devices without changing their low-frequency noise spectra while other gases modify the noise spectra by inducing Lorentzian components with distinctive features. The characteristic corner frequency fC of the Lorentzian noise bulges in graphene devices is different for different chemicals and varies from fC=10 - 20 Hz for tetrahydrofuran to fC=1300 - 1600 Hz for chloroform. We tested the selected set of chemicals vapors on different graphene device samples and alternated different vapors for the same samples. The obtained results indicate that 1/f noise in combination with other sensing parameters can allow one to achieve the selective gas sensing with a single pristine graphene transistor. Our method of gas sensing with graphene does not require graphene surface functionalization or fabrication of an array of the devices with each tuned to a certain chemical. The observation of the Lorentzian components in the vapor-exposed graphene can also help in developing an accurate theoretical description of the noise mechanism in graphene.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"54 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83852206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243360
S. Mori, N. Morioka, J. Suda, T. Kimoto
We calculated the conduction band structure of GeNWs by a tight-binding model and obtained the fundamental understanding of electron transport characteristics in [001], [110], [111], and [112] GeNW FETs. The simulation of ballistic electron transport revealed that [110] GeNW FETs on the (001) face achieve high drive current as well as high injection velocity, being the best choice for n-channel FETs.
{"title":"Orientation and size effects on ballistic electron transport properties in gate-all-around rectangular germanium nanowire FETs","authors":"S. Mori, N. Morioka, J. Suda, T. Kimoto","doi":"10.1109/SNW.2012.6243360","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243360","url":null,"abstract":"We calculated the conduction band structure of GeNWs by a tight-binding model and obtained the fundamental understanding of electron transport characteristics in [001], [110], [111], and [112] GeNW FETs. The simulation of ballistic electron transport revealed that [110] GeNW FETs on the (001) face achieve high drive current as well as high injection velocity, being the best choice for n-channel FETs.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"7 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78342804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243320
J. Y. Seo, Yoon Kim, Se Hwan Park, Wandong Kim, Do-Bin Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park
In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).
{"title":"Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array","authors":"J. Y. Seo, Yoon Kim, Se Hwan Park, Wandong Kim, Do-Bin Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park","doi":"10.1109/SNW.2012.6243320","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243320","url":null,"abstract":"In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"46 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86006916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243288
J. Kamioka, T. Kodera, K. Horibe, Y. Kawano, S. Oda
We realized lithographically-defined electrically-tunable silicon quantum dot (QD) and charge sensor. Two types of device were fabricated and measured. One is heavily P-doped, and the other is back gate (BG)-induced undoped QD device. I-V characteristic of QD and charge sensor was clearly observed in both devices. Then, we estimate capacitance between the charge sensor and QD or two side gates (SGs) from the measurement and the simulation, and compared two devices in terms of their charging energy.
{"title":"Fabrication and evaluation of heavily P-doped Si quantum dot and back-gate induced Si quantum dot","authors":"J. Kamioka, T. Kodera, K. Horibe, Y. Kawano, S. Oda","doi":"10.1109/SNW.2012.6243288","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243288","url":null,"abstract":"We realized lithographically-defined electrically-tunable silicon quantum dot (QD) and charge sensor. Two types of device were fabricated and measured. One is heavily P-doped, and the other is back gate (BG)-induced undoped QD device. I-V characteristic of QD and charge sensor was clearly observed in both devices. Then, we estimate capacitance between the charge sensor and QD or two side gates (SGs) from the measurement and the simulation, and compared two devices in terms of their charging energy.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84854248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243327
D. Ferry
Graphene has become of great interest in recent years for its unique band structure and prospective importance in both microwave and logic devices. Recently, the use of a boron nitride layer between the graphene and the silicon dioxide substrate has shown enhanced mobilities due to displacing the disorder charge, typical on the oxide, further from the graphene material. On the other hand, like the oxide, boron nitride has polar optical modes which can interact with the carriers in graphene to lower their mobility. We have used an ensemble Monte Carlo technique to study the transport in graphene on a boron nitride layer. Scattering by the intrinsic phonons of graphene, as well as by the flexural modes of the rippled layer, and the remote polar mode of boron nitride has been included. The flexural modes are described by the model of Castro et al. While the EMC uses the simple Dirac band structure, coupling constants for the intrinsic phonon modes are taken by fitting to scattering rates determined from first-principles calculations. We find that, at low temperatures, the mobility is dominated primarily by the intrinsic graphene phonons and the flexural modes. This arises as the interfacial polar mode of boron nitride lies at an energy of 200 meV, which is largely too high to interact well with the majority of the carriers in graphene. On the other hand, at room temperature, the mobility begins to be dominated by the remote polar mode of the boron nitride. Nevertheless, the prospects of reaching a high velocity, needed for device performance particularly at microwave frequencies, remains very good.
{"title":"Transport in graphene on boron nitride","authors":"D. Ferry","doi":"10.1109/SNW.2012.6243327","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243327","url":null,"abstract":"Graphene has become of great interest in recent years for its unique band structure and prospective importance in both microwave and logic devices. Recently, the use of a boron nitride layer between the graphene and the silicon dioxide substrate has shown enhanced mobilities due to displacing the disorder charge, typical on the oxide, further from the graphene material. On the other hand, like the oxide, boron nitride has polar optical modes which can interact with the carriers in graphene to lower their mobility. We have used an ensemble Monte Carlo technique to study the transport in graphene on a boron nitride layer. Scattering by the intrinsic phonons of graphene, as well as by the flexural modes of the rippled layer, and the remote polar mode of boron nitride has been included. The flexural modes are described by the model of Castro et al. While the EMC uses the simple Dirac band structure, coupling constants for the intrinsic phonon modes are taken by fitting to scattering rates determined from first-principles calculations. We find that, at low temperatures, the mobility is dominated primarily by the intrinsic graphene phonons and the flexural modes. This arises as the interfacial polar mode of boron nitride lies at an energy of 200 meV, which is largely too high to interact well with the majority of the carriers in graphene. On the other hand, at room temperature, the mobility begins to be dominated by the remote polar mode of the boron nitride. Nevertheless, the prospects of reaching a high velocity, needed for device performance particularly at microwave frequencies, remains very good.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"88 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86338211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243337
R. Suzuki, M. Nozue, T. Saraya, T. Hiramoto
Dot formation mechanisms of single-electron transistors (SETs) and single-hole transistors (SHTs) are reinvestigated. “Shared channel” SET/SHTs in form of nanowire (NW) channel FETs are fabricated and characterized. It is suggested that, in addition to quantum confinement effect (QCE), the positive charges create parasitic dots in SHT channels resulting in multiple-dot SHTs. It is concluded that a <;110>; SET is the best structure to obtain room temperature (RT) operating single-dot device with high yield.
{"title":"Reinvestigation of dot formation mechanisms in silicon nanowire channel single-electron/hole transistors operating at room temperature","authors":"R. Suzuki, M. Nozue, T. Saraya, T. Hiramoto","doi":"10.1109/SNW.2012.6243337","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243337","url":null,"abstract":"Dot formation mechanisms of single-electron transistors (SETs) and single-hole transistors (SHTs) are reinvestigated. “Shared channel” SET/SHTs in form of nanowire (NW) channel FETs are fabricated and characterized. It is suggested that, in addition to quantum confinement effect (QCE), the positive charges create parasitic dots in SHT channels resulting in multiple-dot SHTs. It is concluded that a <;110>; SET is the best structure to obtain room temperature (RT) operating single-dot device with high yield.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85264743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243305
Jung Han Lee, Jieun Lee, Min-Chul Sun, W. Lee, M. Uhm, Seonwook Hwang, I. Chung, D. M. Kim, Dae Hwan Kim, Byung-Gook Park
A silicon nanowire field effect transistor (SiNW FET) was fabricated through the fabrication method compatible with that of MOSFET including back-end process without lift-off process. However, when it is working in an aqueous solution, the SiNW device as well as other transducer devices has various inherent instability problems such as hysteresis characteristics. We observed the hysteresis in DI water (DW) and confirmed that it is caused by mobile ion effect in DW with various experimental results.
{"title":"Analysis of hysteresis characteristics of fabricated SiNW biosensor in aqueous environment with reference electrode","authors":"Jung Han Lee, Jieun Lee, Min-Chul Sun, W. Lee, M. Uhm, Seonwook Hwang, I. Chung, D. M. Kim, Dae Hwan Kim, Byung-Gook Park","doi":"10.1109/SNW.2012.6243305","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243305","url":null,"abstract":"A silicon nanowire field effect transistor (SiNW FET) was fabricated through the fabrication method compatible with that of MOSFET including back-end process without lift-off process. However, when it is working in an aqueous solution, the SiNW device as well as other transducer devices has various inherent instability problems such as hysteresis characteristics. We observed the hysteresis in DI water (DW) and confirmed that it is caused by mobile ion effect in DW with various experimental results.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83162409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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