Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243349
M. Han, Jong Ho Lee, D. Seo, Chong-Dae Park, Youngcheol Oh, I. Cho
SONOS memory with TFET is proposed to achieve off leakage current characteristics. SONOS memory with TFET exhibits extremely small off state leakage current, good FN program efficiency. Program characteristics and disturbance characteristics were investigated with device simulation. It is expected that SONOS memory with TFET can be a promising candidate for mobile devices with require low-power consumption.
{"title":"Low standby power charge trap flash memory with tunneling field effect transistor","authors":"M. Han, Jong Ho Lee, D. Seo, Chong-Dae Park, Youngcheol Oh, I. Cho","doi":"10.1109/SNW.2012.6243349","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243349","url":null,"abstract":"SONOS memory with TFET is proposed to achieve off leakage current characteristics. SONOS memory with TFET exhibits extremely small off state leakage current, good FN program efficiency. Program characteristics and disturbance characteristics were investigated with device simulation. It is expected that SONOS memory with TFET can be a promising candidate for mobile devices with require low-power consumption.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"57 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73406586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243326
R. Mears, N. Xu, N. Damrongplasit, H. Takeuchi, R. Stephenson, N. Cody, A. Yiptong, X. Huang, M. Hytha, Tsu-Jae King-Liu
We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.
{"title":"Simultaneous carrier transport enhancement and variability reduction in Si MOSFETs by insertion of partial monolayers of oxygen","authors":"R. Mears, N. Xu, N. Damrongplasit, H. Takeuchi, R. Stephenson, N. Cody, A. Yiptong, X. Huang, M. Hytha, Tsu-Jae King-Liu","doi":"10.1109/SNW.2012.6243326","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243326","url":null,"abstract":"We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"58 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75908871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243345
E. Hsieh, S. Chung, C. Tsai, R. Huang, C. Tsai, C. Liang
The variation of saturation drain current (Id,sat), induced by the random dopant variation (RDF), has been extensively studied by a new multivariate analysis method. It was found that the variation of Id,sat is originated from Vth,sat and saturation velocity (Vsat), while the variation of Vth,sat comes from the drain induced barrier lowering (DIBL). However, the experimental results shows that Vsat dominates the variation of Id,sat. From the transport theory, Vsat is further decomposed into Vinj and Bsat, showing that Vinj is the dominant factor of Id,sat variation. The faster the Vinj is, the less the Id,sat variation becomes. If one improves the injection velocity, then the variation of Id,sat can be suppressed. This has been one of the significant benefits of strained silicon technology in CMOS device scaling.
{"title":"The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices","authors":"E. Hsieh, S. Chung, C. Tsai, R. Huang, C. Tsai, C. Liang","doi":"10.1109/SNW.2012.6243345","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243345","url":null,"abstract":"The variation of saturation drain current (I<sub>d,sat</sub>), induced by the random dopant variation (RDF), has been extensively studied by a new multivariate analysis method. It was found that the variation of I<sub>d,sat</sub> is originated from V<sub>th,sat</sub> and saturation velocity (V<sub>sat</sub>), while the variation of V<sub>th,sat</sub> comes from the drain induced barrier lowering (DIBL). However, the experimental results shows that V<sub>sat</sub> dominates the variation of I<sub>d,sat</sub>. From the transport theory, V<sub>sat</sub> is further decomposed into V<sub>inj</sub> and B<sub>sat</sub>, showing that V<sub>inj</sub> is the dominant factor of I<sub>d,sat</sub> variation. The faster the V<sub>inj</sub> is, the less the I<sub>d,sat</sub> variation becomes. If one improves the injection velocity, then the variation of I<sub>d,sat</sub> can be suppressed. This has been one of the significant benefits of strained silicon technology in CMOS device scaling.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"126 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79745294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243355
Sunghun Jung, Jeong-Hoon Oh, K. Ryoo, Sungjun Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park
By inserting copper (Cu) metal layer between platinum (Pt) and titanium dioxide (TiO2), we have observed both unipolar and bipolar resistive switching characteristics in Pt/Cu/TiO2/Pt stacked RRAM cell. In order to analyze the conduction mechanism, we have conducted I-V fitting. And based on measurement results of bias polarity dependency, we have found that copper plays a role as oxygen reservoir. It can explain redox mechanism in bipolar resistive switching cell.
{"title":"Effect of Cu insertion layer between top electrode and switching layer on resistive switching characteristics","authors":"Sunghun Jung, Jeong-Hoon Oh, K. Ryoo, Sungjun Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park","doi":"10.1109/SNW.2012.6243355","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243355","url":null,"abstract":"By inserting copper (Cu) metal layer between platinum (Pt) and titanium dioxide (TiO2), we have observed both unipolar and bipolar resistive switching characteristics in Pt/Cu/TiO2/Pt stacked RRAM cell. In order to analyze the conduction mechanism, we have conducted I-V fitting. And based on measurement results of bias polarity dependency, we have found that copper plays a role as oxygen reservoir. It can explain redox mechanism in bipolar resistive switching cell.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"84 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77360166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243354
Ju-Wan Lee, M. Jeong, Byung-Gook Park, Hyungcheol Shin, Jang-Sik Lee
In this paper, we have studied a new 3-D stacked NAND flash memory structure and explained the fabrication sequence and key features of fabricated devices. Reasonable operation of the devices was shown in terms of ΔVth, retention and cycling characteristics. Moreover, the device characteristics were quite improved by removing the etch damage on the side surface (channel) of poly-Si BL layers when CDE process was adopted after etching the BL stack.
{"title":"3-D stacked NAND flash memory having lateral bit-line layers and vertical gate","authors":"Ju-Wan Lee, M. Jeong, Byung-Gook Park, Hyungcheol Shin, Jang-Sik Lee","doi":"10.1109/SNW.2012.6243354","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243354","url":null,"abstract":"In this paper, we have studied a new 3-D stacked NAND flash memory structure and explained the fabrication sequence and key features of fabricated devices. Reasonable operation of the devices was shown in terms of ΔVth, retention and cycling characteristics. Moreover, the device characteristics were quite improved by removing the etch damage on the side surface (channel) of poly-Si BL layers when CDE process was adopted after etching the BL stack.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"124 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77343856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243341
J. Verduijn, G. Tettamanzi, R. Wacquez, B. Roche, B. Voisin, X. Jehl, M. Sanquer, S. Rogge
Using low temperature measurements we have been able to identify the influence of only about five donors in the channel the channel of an ultra-scaled MOSFET as the source of an anomalously low room temperature threshold voltage and large sub-threshold slope. Further we observe the influence of these dopants on the low temperature threshold voltage shift as a function of applied back gate voltage. The understanding of this behavior allows us to identify resonant tunneling mediated by a single donor in the channel of a doped channel device and we show that the back gate strongly modifies the tunnel coupling. These results give new insights in dopant transport in ultra-scaled MOSFETs, which is relevant for conventional device characteristics as well as for new dopant-based device architectures.
{"title":"Mapping of single donors in nano-scale MOSFETs at low temperature","authors":"J. Verduijn, G. Tettamanzi, R. Wacquez, B. Roche, B. Voisin, X. Jehl, M. Sanquer, S. Rogge","doi":"10.1109/SNW.2012.6243341","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243341","url":null,"abstract":"Using low temperature measurements we have been able to identify the influence of only about five donors in the channel the channel of an ultra-scaled MOSFET as the source of an anomalously low room temperature threshold voltage and large sub-threshold slope. Further we observe the influence of these dopants on the low temperature threshold voltage shift as a function of applied back gate voltage. The understanding of this behavior allows us to identify resonant tunneling mediated by a single donor in the channel of a doped channel device and we show that the back gate strongly modifies the tunnel coupling. These results give new insights in dopant transport in ultra-scaled MOSFETs, which is relevant for conventional device characteristics as well as for new dopant-based device architectures.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"143 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80338164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243306
Sang Wan Kim, W. Choi, Hyungjin Kim, Min-Chul Sun, H. Kim, Byung-Gook Park
In this paper, hump effects of L-shaped tunneling field-effect transistors (TFETs) have been investigated. It turns out that the hump effects are originated from the two different turn-on voltages (Vturn-on's). By using device simulation, the source junction design has been optimized in order to suppress the hump effects.
{"title":"Investigation on hump effects of L-shaped tunneling filed-effect transistors","authors":"Sang Wan Kim, W. Choi, Hyungjin Kim, Min-Chul Sun, H. Kim, Byung-Gook Park","doi":"10.1109/SNW.2012.6243306","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243306","url":null,"abstract":"In this paper, hump effects of L-shaped tunneling field-effect transistors (TFETs) have been investigated. It turns out that the hump effects are originated from the two different turn-on voltages (Vturn-on's). By using device simulation, the source junction design has been optimized in order to suppress the hump effects.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"58 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87090783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243331
Yi Wu, Shimeng Yu, X. Guan, H. Wong
This paper gives an overview of recent works on metal oxide resistive switching memory (RRAM). We explored the stochastic nature of resistive switching in metal oxide RRAM and a 2-D analytical solver was established to explain the switching parameter variations in HfOx-based RRAM. As an example of application beyond digital memory/storage, AlOx-based RRAM was explored for neuromorphic computing.
{"title":"Recent progress of resistive switching random access memory (RRAM)","authors":"Yi Wu, Shimeng Yu, X. Guan, H. Wong","doi":"10.1109/SNW.2012.6243331","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243331","url":null,"abstract":"This paper gives an overview of recent works on metal oxide resistive switching memory (RRAM). We explored the stochastic nature of resistive switching in metal oxide RRAM and a 2-D analytical solver was established to explain the switching parameter variations in HfOx-based RRAM. As an example of application beyond digital memory/storage, AlOx-based RRAM was explored for neuromorphic computing.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"62 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81278630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The process is simple and mask free. For the 3-nm-thick channel devices, the S.S. of 88 mV/dec and Ion/Ioff ratio of more than 108 can be achieved. Extreme low applied voltage for band-to-band-tunneling-induced hot electron injection tunneling (BBHE) operation and excellent retention are proposed.
{"title":"A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals","authors":"Hung-Bin Chen, Shih-Han Lin, Jia-Jiun Wu, Yung-Chun Wu, Chun-Yen Chang","doi":"10.1109/SNW.2012.6243321","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243321","url":null,"abstract":"A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The process is simple and mask free. For the 3-nm-thick channel devices, the S.S. of 88 mV/dec and Ion/Ioff ratio of more than 108 can be achieved. Extreme low applied voltage for band-to-band-tunneling-induced hot electron injection tunneling (BBHE) operation and excellent retention are proposed.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"73 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72808255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243290
R. Mizokuchi, T. Kodera, K. Horibe, Y. Kawano, S. Oda
We fabricate a serial triple quantum dot (TQD) system, which is made on a silicon-on-insulator (SOI) wafer by dry etching and integrated with single electron transistors (SETs) as charge sensors. We observe charge transitions of a dot in the TQD in the characteristic of the charge sensor which is the furthest to the dot. It implies a SET charge sensor has a capability of sensing of all the charge transitions in TQD.
{"title":"Charge sensing of a Si triple quantum dot system using single electron transistors","authors":"R. Mizokuchi, T. Kodera, K. Horibe, Y. Kawano, S. Oda","doi":"10.1109/SNW.2012.6243290","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243290","url":null,"abstract":"We fabricate a serial triple quantum dot (TQD) system, which is made on a silicon-on-insulator (SOI) wafer by dry etching and integrated with single electron transistors (SETs) as charge sensors. We observe charge transitions of a dot in the TQD in the characteristic of the charge sensor which is the furthest to the dot. It implies a SET charge sensor has a capability of sensing of all the charge transitions in TQD.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"48 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76861524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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