Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243318
Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara
The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n+-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller Vt variations, and a higher program speed are obtained in the TG-type flash memories than in the DG-type memories. Moreover, it was also confirmed that over-erase is effectively suppressed by split-gate structure.
{"title":"Comparative study of tri-gate- and double-gate-type poly-Si fin-channel split-gate flash memories","authors":"Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara","doi":"10.1109/SNW.2012.6243318","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243318","url":null,"abstract":"The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n+-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller Vt variations, and a higher program speed are obtained in the TG-type flash memories than in the DG-type memories. Moreover, it was also confirmed that over-erase is effectively suppressed by split-gate structure.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"16 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86156492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243340
S. Shin, M. Ryu, K. Kim
Negative differential resistance (NDR) devices are proposed with ultra-high peak-to-valley current ratio (PVCR) over 104 based on silicon nanowire structure.
基于硅纳米线结构，提出了具有超高峰谷电流比(PVCR)的负差分电阻(NDR)器件。
{"title":"Negative Differential resistance devices with ultra-high peak-to-valley current ratio based on silicon nanowire structure","authors":"S. Shin, M. Ryu, K. Kim","doi":"10.1109/SNW.2012.6243340","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243340","url":null,"abstract":"Negative differential resistance (NDR) devices are proposed with ultra-high peak-to-valley current ratio (PVCR) over 104 based on silicon nanowire structure.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"210 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76262321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243344
T. Mizutani, Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, T. Hiramoto
Drain current variability in silicon-on-thin-BOX (SOTB) MOSFETs are analyzed by decomposing into current variability components and compared with conventional bulk MOSFETs. It is found that drain current variability in SOTB MOSFETs is largely suppressed thanks to not only reduced VTH variability but also reduced current-onset voltage (COV) variability due to intrinsic channel.
{"title":"Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs","authors":"T. Mizutani, Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, T. Hiramoto","doi":"10.1109/SNW.2012.6243344","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243344","url":null,"abstract":"Drain current variability in silicon-on-thin-BOX (SOTB) MOSFETs are analyzed by decomposing into current variability components and compared with conventional bulk MOSFETs. It is found that drain current variability in SOTB MOSFETs is largely suppressed thanks to not only reduced VTH variability but also reduced current-onset voltage (COV) variability due to intrinsic channel.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73157014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243300
M. Ryu, Sung-Ho Kim, Kyung Rok Kim
In this study, we investigate the effects of amorphous silicon (a-Si) mass density variations on the electrical series and contact resistance of nanoscale structures for thin-film transistors (TFTs). Impurity distributions according to the variation of a-Si mass density (ρa-Si) are obtained from Monte-Carlo (MC) method and the resistance extraction are performed by using device simulation based on transfer length method (TLM) with a-Si mobility and Schottky contact model. Under the small variations of ±5% from standard ρa-Si, electrical resistances are significantly changed with 30% variations from its typical characteristics in nanoscale TFTs.
{"title":"Effects of amorphous silicon atomic density variation on series and contact resistances in nanoscale thin-film structures","authors":"M. Ryu, Sung-Ho Kim, Kyung Rok Kim","doi":"10.1109/SNW.2012.6243300","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243300","url":null,"abstract":"In this study, we investigate the effects of amorphous silicon (a-Si) mass density variations on the electrical series and contact resistance of nanoscale structures for thin-film transistors (TFTs). Impurity distributions according to the variation of a-Si mass density (ρa-Si) are obtained from Monte-Carlo (MC) method and the resistance extraction are performed by using device simulation based on transfer length method (TLM) with a-Si mobility and Schottky contact model. Under the small variations of ±5% from standard ρa-Si, electrical resistances are significantly changed with 30% variations from its typical characteristics in nanoscale TFTs.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"55 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84732294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243317
A. Liao, Z. Ong, A. Serov, F. Xiong, E. Pop
Power consumption and thermal management are significant challenges in electronics, from mobile devices to data centers. A fundamental examination of such aspects could lead to orders of magnitude improvements in energy efficiency. We present recent highlights from our work examining dissipation in nanoscale devices, at contacts, interfaces, and in novel materials. Advances include the use of high-thermal conductivity materials (graphene), low-power data storage (based on phase change rather than charge), and thermoelectric effects for highly localized cooling. Results suggest much room to improve power dissipation in nanoscale electronics, towards fundamental limits, through the co-design of geometry and materials.
{"title":"Energy-efficiency and thermal management in nanoscale devices","authors":"A. Liao, Z. Ong, A. Serov, F. Xiong, E. Pop","doi":"10.1109/SNW.2012.6243317","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243317","url":null,"abstract":"Power consumption and thermal management are significant challenges in electronics, from mobile devices to data centers. A fundamental examination of such aspects could lead to orders of magnitude improvements in energy efficiency. We present recent highlights from our work examining dissipation in nanoscale devices, at contacts, interfaces, and in novel materials. Advances include the use of high-thermal conductivity materials (graphene), low-power data storage (based on phase change rather than charge), and thermoelectric effects for highly localized cooling. Results suggest much room to improve power dissipation in nanoscale electronics, towards fundamental limits, through the co-design of geometry and materials.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87525908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243325
S. Hibino, T. Nishimura, K. Nagashio, K. Kita, A. Toriumi
This paper presents experimental results of the counter dipole formation in SiO2/high-k (Al2O3 and Y2O3)/SiO2/Si gate stacks for the first time. The results definitely support the high-k/SiO2 interface dipole layer formation in metal/high-k gate CMOS.
{"title":"Counter dipole layer formation in SiO2/high-k/SiO2/Si gate stacks","authors":"S. Hibino, T. Nishimura, K. Nagashio, K. Kita, A. Toriumi","doi":"10.1109/SNW.2012.6243325","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243325","url":null,"abstract":"This paper presents experimental results of the counter dipole formation in SiO<sub>2</sub>/high-k (Al<sub>2</sub>O<sub>3</sub> and Y<sub>2</sub>O<sub>3</sub>)/SiO<sub>2</sub>/Si gate stacks for the first time. The results definitely support the high-k/SiO<sub>2</sub> interface dipole layer formation in metal/high-k gate CMOS.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"209 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88068257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243358
T. Hosoi, Y. Odake, K. Chikaraishi, H. Arimura, N. Kitano, T. Shimura, H. Watanabe
We have investigated the diffusion kinetics of Hf in TiN/HfSiO gate stacks. The Hf upward diffusion is found to be independent of interfacial SiO2 growth, but depends on the amount of oxygen in the gate stacks. It is also revealed that Hf diffusion into TiN electrode occurs at above 650°C and leads to high-k degradation.
{"title":"Oxygen-induced high-k degradation in TiN/HfSiO gate stacks","authors":"T. Hosoi, Y. Odake, K. Chikaraishi, H. Arimura, N. Kitano, T. Shimura, H. Watanabe","doi":"10.1109/SNW.2012.6243358","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243358","url":null,"abstract":"We have investigated the diffusion kinetics of Hf in TiN/HfSiO gate stacks. The Hf upward diffusion is found to be independent of interfacial SiO2 growth, but depends on the amount of oxygen in the gate stacks. It is also revealed that Hf diffusion into TiN electrode occurs at above 650°C and leads to high-k degradation.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"11 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84600332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243328
H. Ohno
I have reviewed current status of MTJ and how it can be used in memories and logic circuits, referring to some of our recent implementations. The ultimate scalability of MTJ technology will be determined by both materials involved and processing technology. It is difficult to foresee how far in dimension one can go at this point. But we should be able to learn from the materials science for hard disk media that can realize high Δ at dimensions less than 10nm and is continuing to develop a patterned one.
{"title":"Magnetic tunnel junction for magnetoresistive random access memory and beyond","authors":"H. Ohno","doi":"10.1109/SNW.2012.6243328","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243328","url":null,"abstract":"I have reviewed current status of MTJ and how it can be used in memories and logic circuits, referring to some of our recent implementations. The ultimate scalability of MTJ technology will be determined by both materials involved and processing technology. It is difficult to foresee how far in dimension one can go at this point. But we should be able to learn from the materials science for hard disk media that can realize high Δ at dimensions less than 10nm and is continuing to develop a patterned one.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"186 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83045169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243335
H. Hwang, E. J. Paek, J. H. Yang, C. Kang, B. H. Lee
Characteristics of new reconfigurable graphene device with Metal/ Ferroelectric (PVDF-TrFE)/Graphene (MFG) stack is presented. Key features include programming speed <; 100nsec, retention up to 1000sec, endurance upto 1000 cycles and more than 775% on/off ratio. While memory like functionalities are primarily presented in this paper, MFG device has many versatile applications such as reconfigurable interconnect resistor or logic device, pressure sensitive touch sensor and so on.
{"title":"Characteristics of Metal/Ferroelectric (PVDF-TrFE)/Graphene (MFG) device","authors":"H. Hwang, E. J. Paek, J. H. Yang, C. Kang, B. H. Lee","doi":"10.1109/SNW.2012.6243335","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243335","url":null,"abstract":"Characteristics of new reconfigurable graphene device with Metal/ Ferroelectric (PVDF-TrFE)/Graphene (MFG) stack is presented. Key features include programming speed <; 100nsec, retention up to 1000sec, endurance upto 1000 cycles and more than 775% on/off ratio. While memory like functionalities are primarily presented in this paper, MFG device has many versatile applications such as reconfigurable interconnect resistor or logic device, pressure sensitive touch sensor and so on.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"59 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76093217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243353
Ko-Hui Lee, Horng-Chih Lin, Tiao-Yuan Huang
Gate-all-around poly-silicon nanowire (GAA poly-Si NW) SONOS devices embedded with silicon nanocrystals (Si-NCs) were fabricated and characterized. As Si-NCs are incorporated, the transfer characteristics show a large clockwise Id-Vg hysteresis and a small kink under reverse sweep. Si dangling bonds located at SiNC/nitride interfaces are suspected to be responsible for the observations.
{"title":"Impacts of silicon nanocrystal incorporation on the transfer characteristics of poly-silicon nanowire SONOS devices","authors":"Ko-Hui Lee, Horng-Chih Lin, Tiao-Yuan Huang","doi":"10.1109/SNW.2012.6243353","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243353","url":null,"abstract":"Gate-all-around poly-silicon nanowire (GAA poly-Si NW) SONOS devices embedded with silicon nanocrystals (Si-NCs) were fabricated and characterized. As Si-NCs are incorporated, the transfer characteristics show a large clockwise Id-Vg hysteresis and a small kink under reverse sweep. Si dangling bonds located at SiNC/nitride interfaces are suspected to be responsible for the observations.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"61 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75027671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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