Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243313
S. Monfray, O. Puscasu, G. Savelli, U. Soupremanien, E. Ollier, C. Guérin, L. Fréchette, É. Léveillé, G. Mirshekari, C. Maitre, P. Coronel, K. Domanski, P. Grabiec, P. Ancey, D. Guyomar, V. Bottarel, G. Ricotti, F. Boeuf, F. Gaillard, T. Skotnicki
Thermal gradients, commonly present in our environment (fluid lines, warm fronts, electronics) are sources of energy rarely used today. This paper aims to present innovative approaches of thin and/or flexible thermal energy harvesters for smart and autonomous sensor network applications. The harvester system will be based on the collaborative work of interrelated energy nodes/units, which will be either piezo-thermofluidic converters (use of rapid thermal cycles of a working fluid) or piezo-thermomechanic converters (use of the mechanical energy developed by rapid snapping of micro-switches). The two kinds of energy nodes convert a heat flux into storable electrical energy through a piezoelectric transducer. Miniaturization of the energy nodes will lead to increased thermal transfer rates and consequently increased harvested power. To effectively use thermal energy sources in varying environments, the nodes will be adaptive versus different thermal gradients (in a predefined temperature range) and will possibly influence each other. The concept is unique in the sense that it is based on a matrix structure of micro or mini energy nodes which will work together in a collective approach to optimize the harvested energy, and which do not require the use of radiators as classical Seebeck approach, thanks to the controlled thermal resistance. This opens the door to new properties and features of the object, with better performances. It could therefore be declined on flexible substrates, allowing conformability around the sources of potential heat for low power applications.
{"title":"Innovative thermal energy harvesting for zero power electronics","authors":"S. Monfray, O. Puscasu, G. Savelli, U. Soupremanien, E. Ollier, C. Guérin, L. Fréchette, É. Léveillé, G. Mirshekari, C. Maitre, P. Coronel, K. Domanski, P. Grabiec, P. Ancey, D. Guyomar, V. Bottarel, G. Ricotti, F. Boeuf, F. Gaillard, T. Skotnicki","doi":"10.1109/SNW.2012.6243313","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243313","url":null,"abstract":"Thermal gradients, commonly present in our environment (fluid lines, warm fronts, electronics) are sources of energy rarely used today. This paper aims to present innovative approaches of thin and/or flexible thermal energy harvesters for smart and autonomous sensor network applications. The harvester system will be based on the collaborative work of interrelated energy nodes/units, which will be either piezo-thermofluidic converters (use of rapid thermal cycles of a working fluid) or piezo-thermomechanic converters (use of the mechanical energy developed by rapid snapping of micro-switches). The two kinds of energy nodes convert a heat flux into storable electrical energy through a piezoelectric transducer. Miniaturization of the energy nodes will lead to increased thermal transfer rates and consequently increased harvested power. To effectively use thermal energy sources in varying environments, the nodes will be adaptive versus different thermal gradients (in a predefined temperature range) and will possibly influence each other. The concept is unique in the sense that it is based on a matrix structure of micro or mini energy nodes which will work together in a collective approach to optimize the harvested energy, and which do not require the use of radiators as classical Seebeck approach, thanks to the controlled thermal resistance. This opens the door to new properties and features of the object, with better performances. It could therefore be declined on flexible substrates, allowing conformability around the sources of potential heat for low power applications.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"31 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89908324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243336
A. Fujiwara, G. Yamahata, K. Nishiguchi, G. Lansbergen, Y. Ono
In this paper we describe our recent efforts to develop SE transfer devices based on Si nanotechnology.
在本文中，我们描述了我们最近的努力开发基于硅纳米技术的SE转移器件。
{"title":"Silicon single-electron transfer devices: Ultimate control of electric charge","authors":"A. Fujiwara, G. Yamahata, K. Nishiguchi, G. Lansbergen, Y. Ono","doi":"10.1109/SNW.2012.6243336","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243336","url":null,"abstract":"In this paper we describe our recent efforts to develop SE transfer devices based on Si nanotechnology.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90185285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243299
J. Campbell, K. Cheung, S. Drozdov, R. Southwick, J. Ryan, A. Oates, J. Suehle
A recently developed series resistance (RSD) extraction procedure from a single nanoscale device is shown to be highly robust. Despite these virtues, the technique unexpectedly results in a channel length-dependent RSD which is observed across a wide range of channel lengths and across many different technologies (SiO2, SiON, and high-k) (see Figs. 1a-f). This observation obviously raises some concerning issues and implications as RSD is universally accepted as channel length-independent. However, careful examination of the RSD extraction procedure as well as comparison between RSD-corrected field effect mobility (uFE) and geometric magnetoresistance mobility (uMR) suggests that this unexpected observation may be valid.
{"title":"Channel length-dependent series resistance?","authors":"J. Campbell, K. Cheung, S. Drozdov, R. Southwick, J. Ryan, A. Oates, J. Suehle","doi":"10.1109/SNW.2012.6243299","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243299","url":null,"abstract":"A recently developed series resistance (R<sub>SD</sub>) extraction procedure from a single nanoscale device is shown to be highly robust. Despite these virtues, the technique unexpectedly results in a channel length-dependent R<sub>SD</sub> which is observed across a wide range of channel lengths and across many different technologies (SiO<sub>2</sub>, SiON, and high-k) (see Figs. 1a-f). This observation obviously raises some concerning issues and implications as R<sub>SD</sub> is universally accepted as channel length-independent. However, careful examination of the R<sub>SD</sub> extraction procedure as well as comparison between R<sub>SD</sub>-corrected field effect mobility (u<sub>FE</sub>) and geometric magnetoresistance mobility (u<sub>MR</sub>) suggests that this unexpected observation may be valid.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"81 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89925171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243324
Li-Jung Liu, K. Chang-Liao, C. Fu, H. Hsieh, Chun-Chang Lu, Tien-Ko Wang, P. Gu, M. Tsai
The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ~ 1 nm. The source/drain activation temperature at 650 °C is especially suitable for high-k gate dielectric process.
{"title":"High-performance pMOSFETs with high-k gate dielectric and dislocation-free epitaxial Si/Ge super-lattice channel","authors":"Li-Jung Liu, K. Chang-Liao, C. Fu, H. Hsieh, Chun-Chang Lu, Tien-Ko Wang, P. Gu, M. Tsai","doi":"10.1109/SNW.2012.6243324","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243324","url":null,"abstract":"The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ~ 1 nm. The source/drain activation temperature at 650 °C is especially suitable for high-k gate dielectric process.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"39 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90495995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243339
H. Takenaka, M. Shinohara, T. Uchida, M. Arita, A. Fujiwara, Y. Ono, K. Nishiguchi, H. Inokawa, Y. Takahashi
High-frequency limit of Si single-electron transistor (SET) is investigated. Since the SETs inevitably have tunnel barriers, the operation speed is thought to be low. To measure the high frequency properties of SETs, we employed their special rectification characteristics, which occurred due to the asymmetry of Coulomb diamond when alternating current voltage was applied to the drain terminal. By the use of the effect, we evaluated the high-frequency properties of Si SETs.
{"title":"High-frequency properties of Si single-electron transistor","authors":"H. Takenaka, M. Shinohara, T. Uchida, M. Arita, A. Fujiwara, Y. Ono, K. Nishiguchi, H. Inokawa, Y. Takahashi","doi":"10.1109/SNW.2012.6243339","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243339","url":null,"abstract":"High-frequency limit of Si single-electron transistor (SET) is investigated. Since the SETs inevitably have tunnel barriers, the operation speed is thought to be low. To measure the high frequency properties of SETs, we employed their special rectification characteristics, which occurred due to the asymmetry of Coulomb diamond when alternating current voltage was applied to the drain terminal. By the use of the effect, we evaluated the high-frequency properties of Si SETs.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"2001 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78553580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In nanoscale devices with only a few oxide traps, characterization of trap response during NBTI stress is challenging due to the stochastic nature of trapping/detrapping behavior. This paper successfully extends the statistical trap-response (STR) method from DC to AC device operation, for getting a full understanding of the trap occupancy probability and the aging-induced dynamic variations under DC and AC NBTI. The AC trap response and the AC NBTI fluctuations are found largely deviating from the DC case, indicating different physical mechanisms.
{"title":"On the statistical trap-response (STR) method for characterizing random trap occupancy and NBTI fluctuation","authors":"Jibin Zou, Changze Liu, Runsheng Wang, Xiaoqing Xu, Jinhua Liu, Hanming Wu, Yangyuan Wang, Ru Huang","doi":"10.1109/SNW.2012.6243346","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243346","url":null,"abstract":"In nanoscale devices with only a few oxide traps, characterization of trap response during NBTI stress is challenging due to the stochastic nature of trapping/detrapping behavior. This paper successfully extends the statistical trap-response (STR) method from DC to AC device operation, for getting a full understanding of the trap occupancy probability and the aging-induced dynamic variations under DC and AC NBTI. The AC trap response and the AC NBTI fluctuations are found largely deviating from the DC case, indicating different physical mechanisms.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85754678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243281
N. Hasegawa, R. Sako, H. Tsuchiya, M. Ogawa
In this study, an electrical heterojunction consisting of multi-connected semiconducting and metallic graphene nanoribbons with armchair-edged configurations, is considered and discuss its basic properties by performing the electronic band structure calculations.
{"title":"Band structure and electron transport in multi-junction graphene nanoribbons","authors":"N. Hasegawa, R. Sako, H. Tsuchiya, M. Ogawa","doi":"10.1109/SNW.2012.6243281","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243281","url":null,"abstract":"In this study, an electrical heterojunction consisting of multi-connected semiconducting and metallic graphene nanoribbons with armchair-edged configurations, is considered and discuss its basic properties by performing the electronic band structure calculations.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81873948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243314
D. Hisamoto, S. Saito, A. Shima, H. Yoshimoto, K. Torii
We have proposed an alternative approach for developing a steep subthreshold swing FET that is less than the theoretical diffusion-based limit of 60 mV/decade at room temperature. Instead of using a simple IGFET, we formed a complex device in a “single device” and worked it as a sub-circuit, which resulted in a steep subthreshold swing. We formed a tunnel junction in a drain diffusion layer of the MOSFET so that we could stuff a tunnel-injection bipolar, a resistor, and a MOSFET inside a single “scaled MOSFET”. We used device simulation to clarify the concept of “device complex”. Results showed a steep subthreshold swing even if the supply voltage was low (~0.2 V).
{"title":"New type steep-S device using the bipolar action","authors":"D. Hisamoto, S. Saito, A. Shima, H. Yoshimoto, K. Torii","doi":"10.1109/SNW.2012.6243314","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243314","url":null,"abstract":"We have proposed an alternative approach for developing a steep subthreshold swing FET that is less than the theoretical diffusion-based limit of 60 mV/decade at room temperature. Instead of using a simple IGFET, we formed a complex device in a “single device” and worked it as a sub-circuit, which resulted in a steep subthreshold swing. We formed a tunnel junction in a drain diffusion layer of the MOSFET so that we could stuff a tunnel-injection bipolar, a resistor, and a MOSFET inside a single “scaled MOSFET”. We used device simulation to clarify the concept of “device complex”. Results showed a steep subthreshold swing even if the supply voltage was low (~0.2 V).","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"76 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74145321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243338
M. Hori, T. Shinada, F. Guagliardo, G. Ferrari, E. Prati
We fabricated silicon transistors containing two and six arsenic ions implanted in one dimensional array along the channel by single-ion implantation method. The quantum transport was measured through the D0 and D- states of the arsenic ions at low temperature. We observed two different quantum transport regimes from the individual donor regime to the intermediate doping regime in which Hubbard bands are formed in agreement with the theoretical models. These results indicate that our deterministic single-ion doping method is more effective and reliable for single-dopant transistor development and pave the way towards single atom electronics for extended CMOS applications [12].
{"title":"Quantum transport property in FETs with deterministically implanted single-arsenic ions using single-ion implantation","authors":"M. Hori, T. Shinada, F. Guagliardo, G. Ferrari, E. Prati","doi":"10.1109/SNW.2012.6243338","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243338","url":null,"abstract":"We fabricated silicon transistors containing two and six arsenic ions implanted in one dimensional array along the channel by single-ion implantation method. The quantum transport was measured through the D0 and D- states of the arsenic ions at low temperature. We observed two different quantum transport regimes from the individual donor regime to the intermediate doping regime in which Hubbard bands are formed in agreement with the theoretical models. These results indicate that our deterministic single-ion doping method is more effective and reliable for single-dopant transistor development and pave the way towards single atom electronics for extended CMOS applications [12].","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"46 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72907700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243284
K. Shahil, V. Goyal, R. Gulotty, A. Balandin
Summary form only given. Continuous scaling of Si CMOS devices and circuits, increased speed and integration densities resulted in problems with thermal management of nanoscale device and computer chips. Further progress in information, communication and energy storage technologies requires more efficient heat removal methods and stimulates the search for thermal interface material (TIMs) with enhanced thermal conductivity. The commonly used TIMs are filled with the particles such as silver or silica. The conventional TIMs require high volume fractions of the filler (~70%) to achieve thermal conductivity of ~1-5 W/mK. Recently, some of us discovered that graphene has extremely high intrinsic thermal conductivity, which exceeds that of carbon nanotubes. To use this property for thermal management of nanoscale electronic devices, we utilized the inexpensive liquid-phase exfoliated graphene and multi-layer graphene (MLG) as filler materials in TIMs. The thermal properties of the obtained graphene-epoxy composites were measured using the “laser flash” technique. It was found that the thermal conductivity enhancement factor exceeded a factor of 23 at 10% of the graphene volume loading fraction. This enhancement is larger than anything that has been achieved using other fillers. We have also tested graphene flakes in the electrically-conductive hybrid graphene-metal particle TIMs. The thermal conductivity of resulting composites was increased by a factor of ~5 in a temperature range from 300 K to 400 K at a small graphene loading fraction of 5-vol.-%. The unusually strong enhancement of thermal properties was attributed to the high thermal conductivity of graphene, strong graphene coupling to matrix materials and the large range of the length-scale - from nanometers to micrometers - of the graphene and silver particle fillers. Graphene-based TIMs have a number of other advantages related to their viscosity and adhesion, which meet the industry requirements. Our results suggest that graphene can become excellent filler materials in the next generation of TIMs for the electronic, optoelectronic and photovoltaic solar cell applications.
{"title":"Graphene fillers for ultra-efficient thermal interface materials","authors":"K. Shahil, V. Goyal, R. Gulotty, A. Balandin","doi":"10.1109/SNW.2012.6243284","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243284","url":null,"abstract":"Summary form only given. Continuous scaling of Si CMOS devices and circuits, increased speed and integration densities resulted in problems with thermal management of nanoscale device and computer chips. Further progress in information, communication and energy storage technologies requires more efficient heat removal methods and stimulates the search for thermal interface material (TIMs) with enhanced thermal conductivity. The commonly used TIMs are filled with the particles such as silver or silica. The conventional TIMs require high volume fractions of the filler (~70%) to achieve thermal conductivity of ~1-5 W/mK. Recently, some of us discovered that graphene has extremely high intrinsic thermal conductivity, which exceeds that of carbon nanotubes. To use this property for thermal management of nanoscale electronic devices, we utilized the inexpensive liquid-phase exfoliated graphene and multi-layer graphene (MLG) as filler materials in TIMs. The thermal properties of the obtained graphene-epoxy composites were measured using the “laser flash” technique. It was found that the thermal conductivity enhancement factor exceeded a factor of 23 at 10% of the graphene volume loading fraction. This enhancement is larger than anything that has been achieved using other fillers. We have also tested graphene flakes in the electrically-conductive hybrid graphene-metal particle TIMs. The thermal conductivity of resulting composites was increased by a factor of ~5 in a temperature range from 300 K to 400 K at a small graphene loading fraction of 5-vol.-%. The unusually strong enhancement of thermal properties was attributed to the high thermal conductivity of graphene, strong graphene coupling to matrix materials and the large range of the length-scale - from nanometers to micrometers - of the graphene and silver particle fillers. Graphene-based TIMs have a number of other advantages related to their viscosity and adhesion, which meet the industry requirements. Our results suggest that graphene can become excellent filler materials in the next generation of TIMs for the electronic, optoelectronic and photovoltaic solar cell applications.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73151364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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