Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243289
T. Ferrus, A. Rossi, T. Kodera, T. Kambara, W. Lin, S. Oda, D. Williams
Here we present the results of an investigation on microwave-induced effects that we have observed in silicon devices, including phosphorous doped and Metal-Oxide-Semiconductor Single Electron Transistors (SET) as well as IDQD. Continuous pulsed microwave and single shot measurements are used to demonstrate that photons in the range of 10-15 GHz allow manipulation of the electron number in the island of a doped SET, despite the high value for the charging energy and in a regime where photon assisted tunnelling is not observable. The method is applied to a device made of a SET with a capacitively coupled IDQD. Partial control of the qubit is obtained and results in the possibility of manipulating charge states in an isolated structure with GHz photons.
{"title":"Microwave manipulation of electrons in silicon quantum dots","authors":"T. Ferrus, A. Rossi, T. Kodera, T. Kambara, W. Lin, S. Oda, D. Williams","doi":"10.1109/SNW.2012.6243289","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243289","url":null,"abstract":"Here we present the results of an investigation on microwave-induced effects that we have observed in silicon devices, including phosphorous doped and Metal-Oxide-Semiconductor Single Electron Transistors (SET) as well as IDQD. Continuous pulsed microwave and single shot measurements are used to demonstrate that photons in the range of 10-15 GHz allow manipulation of the electron number in the island of a doped SET, despite the high value for the charging energy and in a regime where photon assisted tunnelling is not observable. The method is applied to a device made of a SET with a capacitively coupled IDQD. Partial control of the qubit is obtained and results in the possibility of manipulating charge states in an isolated structure with GHz photons.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"159 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77550551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243361
Y. Maegawa, S. Koba, H. Tsuchiya, M. Ogawa
III-V compound semiconductors are expected as a post-Si channel material, because they have higher electron mobility and lower effective mass than Si. Actually, the high performance of InGaAs MOSFETs with high-k gate dielectrics has been demonstrated [1,2]. On the other hand, due to a quasi-ballistic behavior of electron transport, III-V channel MOSFETs may be more vulnerable by quantum mechanical effects such as quantum reflection and tunneling, as compared to conventional Si-MOSFETs. In this paper, we investigate quantum transport effects in III-V channel MOSFETs by using a Wigner Monte Carlo (WMC) simulation [3,4], which can fully incorporate the quantum transport effects. As a result, we found that the quantum reflection reduces on-current, while the source-drain (SD) direct tunneling increases subthreshold current even as the channel length is larger than 10 nm.
III-V化合物半导体具有比Si更高的电子迁移率和更低的有效质量，有望成为后Si通道材料。实际上，具有高k栅极电介质的InGaAs mosfet的高性能已经被证明[1,2]。另一方面，由于电子传递的准弹道行为，与传统的si- mosfet相比，III-V沟道mosfet可能更容易受到量子力学效应(如量子反射和隧道效应)的影响。在本文中，我们使用WMC (Wigner Monte Carlo)模拟来研究III-V沟道mosfet中的量子输运效应[3,4]，该模拟可以充分考虑量子输运效应。结果发现，即使通道长度大于10 nm，量子反射也会降低导通电流，而源漏直接隧穿会增加亚阈值电流。
{"title":"Quantum transport simulation of III–V MOSFETs based on Wigner Monte Carlo approach","authors":"Y. Maegawa, S. Koba, H. Tsuchiya, M. Ogawa","doi":"10.1109/SNW.2012.6243361","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243361","url":null,"abstract":"III-V compound semiconductors are expected as a post-Si channel material, because they have higher electron mobility and lower effective mass than Si. Actually, the high performance of InGaAs MOSFETs with high-k gate dielectrics has been demonstrated [1,2]. On the other hand, due to a quasi-ballistic behavior of electron transport, III-V channel MOSFETs may be more vulnerable by quantum mechanical effects such as quantum reflection and tunneling, as compared to conventional Si-MOSFETs. In this paper, we investigate quantum transport effects in III-V channel MOSFETs by using a Wigner Monte Carlo (WMC) simulation [3,4], which can fully incorporate the quantum transport effects. As a result, we found that the quantum reflection reduces on-current, while the source-drain (SD) direct tunneling increases subthreshold current even as the channel length is larger than 10 nm.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90824273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we for the first time assess the characteristics and sensitivity of p-type junctionless (JL) gate-all around (GAA) nanowire transistor using 3D quantum transport device simulation for CMOS technology implementation. Since the doping concentration of p-type junctionless nanowire transistor does not as high as in n-type device due solid solubility of boron in silicon, it can be made by using midgap gate electrode material for appropriate threshold voltage. The p-type JLGAA transistor shows good on/off current ratio and better short channel characteristics compare to conventional inversion mode GAA structure. The sensitivity analyses show that the channel thickness affects the device performance such as threshold voltage (Vth), on current (Ion), and off current (Ioff) significantly. In contrast, the channel length and oxide thickness have less impact owing to well control of short channel effect.
{"title":"Characteristics and sensitivity of p-type junctionless gate-all-around nanowire transistor","authors":"Ming-Hung Han, Y. Jhan, Jia-Jiun Wu, Hung-Bin Chen, Yung-Chun Wu, Chun-Yen Chang","doi":"10.1109/SNW.2012.6243304","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243304","url":null,"abstract":"In this study, we for the first time assess the characteristics and sensitivity of p-type junctionless (JL) gate-all around (GAA) nanowire transistor using 3D quantum transport device simulation for CMOS technology implementation. Since the doping concentration of p-type junctionless nanowire transistor does not as high as in n-type device due solid solubility of boron in silicon, it can be made by using midgap gate electrode material for appropriate threshold voltage. The p-type JLGAA transistor shows good on/off current ratio and better short channel characteristics compare to conventional inversion mode GAA structure. The sensitivity analyses show that the channel thickness affects the device performance such as threshold voltage (Vth), on current (Ion), and off current (Ioff) significantly. In contrast, the channel length and oxide thickness have less impact owing to well control of short channel effect.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"33 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84701602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243287
M. Bareiss, B. Weiler, D. Kalblein, U. Zschieschang, H. Klauk, G. Scarpa, B. Fabel, P. Lugli, W. Porod
Nano diodes show great potential for applications in detectors, communications and energy harvesting. In this work, we focus on nano transfer printing (nTP) to fabricate nm-scale diodes over extensive areas. Using a temperature-enhanced process, several millions of diodes were transfer-printed in one single step. We show the reliable transfer of functioning MIM diodes, which were electrically characterized by conductive Atomic Force Microscopy (c-AFM) measurements. Quantum-mechanical tunneling was determined to be the main conduction mechanism across the metal-oxide-metal junction.
{"title":"Nano-transfer printing of functioning MIM tunnel diodes","authors":"M. Bareiss, B. Weiler, D. Kalblein, U. Zschieschang, H. Klauk, G. Scarpa, B. Fabel, P. Lugli, W. Porod","doi":"10.1109/SNW.2012.6243287","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243287","url":null,"abstract":"Nano diodes show great potential for applications in detectors, communications and energy harvesting. In this work, we focus on nano transfer printing (nTP) to fabricate nm-scale diodes over extensive areas. Using a temperature-enhanced process, several millions of diodes were transfer-printed in one single step. We show the reliable transfer of functioning MIM diodes, which were electrically characterized by conductive Atomic Force Microscopy (c-AFM) measurements. Quantum-mechanical tunneling was determined to be the main conduction mechanism across the metal-oxide-metal junction.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"5 Suppl 1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89327273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243322
M. Lemme, S. Vaziri, A. D. Smith, J. Li, S. Rodriguez, A. Rusu, M. Ostling
Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment and high contact resistance. In addition, graphene has no energy band gap and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour. This has steered interest away from logic to analog radio frequency (RF) applications. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology. GFETs slightly lag behind in maximum cut-off frequency FT,max up to a carrier mobility of 3000 cm2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves.
石墨烯作为More Moore和More Than Moore器件和应用的潜在未来选择，已经引起了电子器件界的注意。这要归功于其卓越的材料特性，包括在原始石墨烯中超过几百纳米的弹道电导率或100,000 cm2/Vs的载流子迁移率。此外，标准CMOS技术可以应用于石墨烯以制造器件。然而，集成石墨烯器件由于石墨烯及其介电环境和高接触电阻的缺陷而受到散射的性能限制。此外，石墨烯没有能带隙，因此石墨烯mosfet (gfet)不能关闭，而是表现出双极性行为。这使得人们的兴趣从逻辑转向模拟射频(RF)应用。本讲座将系统地比较实际的gfet与当前硅CMOS技术的预期射频性能。gfet在最大截止频率FT方面略有落后，载流子迁移率最高可达3000 cm2/Vs，可以实现与65nm硅fet相似的射频性能。虽然强烈的非线性电压依赖性门电容固有地限制了性能，但随着GFET工艺技术的改进，其他寄生因素(如接触电阻)有望得到优化。
{"title":"Graphene for More Moore and More Than Moore applications","authors":"M. Lemme, S. Vaziri, A. D. Smith, J. Li, S. Rodriguez, A. Rusu, M. Ostling","doi":"10.1109/SNW.2012.6243322","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243322","url":null,"abstract":"Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment and high contact resistance. In addition, graphene has no energy band gap and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour. This has steered interest away from logic to analog radio frequency (RF) applications. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology. GFETs slightly lag behind in maximum cut-off frequency FT,max up to a carrier mobility of 3000 cm2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"16 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75881658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243348
Ashok Kumar, T. Saraya, S. Miyano, T. Hiramoto
The post fabrication technique for self-improvement of SRAM cell stability is validated by experiment using 1k DMA SRAM TEG array. It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to VDD terminal. The mechanism of the phenomena is also analyzed by measuring VTH of all transistors before and after stress and it is newly found that |VTH| of weaker PFET in the cell is selectively lowered by the self-improve mechanism.
{"title":"Self-improvement of cell stability in SRAM by post fabrication technique","authors":"Ashok Kumar, T. Saraya, S. Miyano, T. Hiramoto","doi":"10.1109/SNW.2012.6243348","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243348","url":null,"abstract":"The post fabrication technique for self-improvement of SRAM cell stability is validated by experiment using 1k DMA SRAM TEG array. It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to VDD terminal. The mechanism of the phenomena is also analyzed by measuring VTH of all transistors before and after stress and it is newly found that |VTH| of weaker PFET in the cell is selectively lowered by the self-improve mechanism.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"39 5 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77533125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243316
O. Puscasu, S. Monfray, F. Boeuf, G. Savelli, F. Gaillard, D. Guyomar, T. Skotnicki
An innovation approach to thermal energy harvesting is presented. It consists of a two step conversion of heat into electricity. The new technique can be used for powering ultra-low power electronics and autonomous systems. One of the keys to improve the generated power density is downscaling of individual devices. Laws modeling downscaling have been established in this paper and show that the miniaturization of the devices by a factor k increases the generated power density by the same factor, due to the increased speed of heat transfer. The scaling laws predict increasing power gain when miniaturizing the devices with use of e.g. VLSI technologies. This can help in providing a strong alternative to Seebeck devices.
{"title":"Scale laws for enhanced power for MEMS based heat energy harvesting","authors":"O. Puscasu, S. Monfray, F. Boeuf, G. Savelli, F. Gaillard, D. Guyomar, T. Skotnicki","doi":"10.1109/SNW.2012.6243316","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243316","url":null,"abstract":"An innovation approach to thermal energy harvesting is presented. It consists of a two step conversion of heat into electricity. The new technique can be used for powering ultra-low power electronics and autonomous systems. One of the keys to improve the generated power density is downscaling of individual devices. Laws modeling downscaling have been established in this paper and show that the miniaturization of the devices by a factor k increases the generated power density by the same factor, due to the increased speed of heat transfer. The scaling laws predict increasing power gain when miniaturizing the devices with use of e.g. VLSI technologies. This can help in providing a strong alternative to Seebeck devices.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"25 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76978912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243359
Wei Wang, Jing Wang, Mei Zhao, R. Liang, Jun Xu
We inserted a C-containing layer in a metal/Ge structure, using a chemical bath. This layer enabled the Schottky barrier height (SBH) to be modulated. The chemical bath with 1-octadecene and 1-dodecene were performed separately with Ge substrates. The ultrathin C-containing layer stops the penetration of free electron wave functions from the metal to the Ge. Metal-induced gap states are alleviated and the pinned Fermi level is released. The SBH is lowered to 0.17 eV. This new formation method is promising and much less complex than traditional ones.
{"title":"Metal/Ge Schottky barrier modulation with C-containing layer by chemical bath","authors":"Wei Wang, Jing Wang, Mei Zhao, R. Liang, Jun Xu","doi":"10.1109/SNW.2012.6243359","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243359","url":null,"abstract":"We inserted a C-containing layer in a metal/Ge structure, using a chemical bath. This layer enabled the Schottky barrier height (SBH) to be modulated. The chemical bath with 1-octadecene and 1-dodecene were performed separately with Ge substrates. The ultrathin C-containing layer stops the penetration of free electron wave functions from the metal to the Ge. Metal-induced gap states are alleviated and the pinned Fermi level is released. The SBH is lowered to 0.17 eV. This new formation method is promising and much less complex than traditional ones.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"93-94 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76211150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243299
J. Campbell, K. Cheung, S. Drozdov, R. Southwick, J. Ryan, A. Oates, J. Suehle
A recently developed series resistance (RSD) extraction procedure from a single nanoscale device is shown to be highly robust. Despite these virtues, the technique unexpectedly results in a channel length-dependent RSD which is observed across a wide range of channel lengths and across many different technologies (SiO2, SiON, and high-k) (see Figs. 1a-f). This observation obviously raises some concerning issues and implications as RSD is universally accepted as channel length-independent. However, careful examination of the RSD extraction procedure as well as comparison between RSD-corrected field effect mobility (uFE) and geometric magnetoresistance mobility (uMR) suggests that this unexpected observation may be valid.
{"title":"Channel length-dependent series resistance?","authors":"J. Campbell, K. Cheung, S. Drozdov, R. Southwick, J. Ryan, A. Oates, J. Suehle","doi":"10.1109/SNW.2012.6243299","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243299","url":null,"abstract":"A recently developed series resistance (R<sub>SD</sub>) extraction procedure from a single nanoscale device is shown to be highly robust. Despite these virtues, the technique unexpectedly results in a channel length-dependent R<sub>SD</sub> which is observed across a wide range of channel lengths and across many different technologies (SiO<sub>2</sub>, SiON, and high-k) (see Figs. 1a-f). This observation obviously raises some concerning issues and implications as R<sub>SD</sub> is universally accepted as channel length-independent. However, careful examination of the R<sub>SD</sub> extraction procedure as well as comparison between R<sub>SD</sub>-corrected field effect mobility (u<sub>FE</sub>) and geometric magnetoresistance mobility (u<sub>MR</sub>) suggests that this unexpected observation may be valid.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"81 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89925171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-10DOI: 10.1109/SNW.2012.6243324
Li-Jung Liu, K. Chang-Liao, C. Fu, H. Hsieh, Chun-Chang Lu, Tien-Ko Wang, P. Gu, M. Tsai
The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ~ 1 nm. The source/drain activation temperature at 650 °C is especially suitable for high-k gate dielectric process.
{"title":"High-performance pMOSFETs with high-k gate dielectric and dislocation-free epitaxial Si/Ge super-lattice channel","authors":"Li-Jung Liu, K. Chang-Liao, C. Fu, H. Hsieh, Chun-Chang Lu, Tien-Ko Wang, P. Gu, M. Tsai","doi":"10.1109/SNW.2012.6243324","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243324","url":null,"abstract":"The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ~ 1 nm. The source/drain activation temperature at 650 °C is especially suitable for high-k gate dielectric process.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"39 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90495995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：