Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105681
Mingxiang Chen, T. Xu, Sheng Liu, C. Wong
Direct bonded copper (DBC) as heat spreader and highly thermal conductive adhesives as thermal interface materials (TIMs), the light performances of packaged high-brightness light-emitting diodes (HB-LEDs) were tested. The results indicated that the light output power of LED modules increased with the thermal conductivities of TIMs. Apart from its low bulk thermal resistance, highly thermal conductive adhesive has high adhesion with adjacent substrates which resulted in low contact thermal resistance, then the optical performance and reliability of LED package can be improved.
{"title":"Study on thermal conductive adhesives for high-power LEDs packaging","authors":"Mingxiang Chen, T. Xu, Sheng Liu, C. Wong","doi":"10.1109/ISAPM.2011.6105681","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105681","url":null,"abstract":"Direct bonded copper (DBC) as heat spreader and highly thermal conductive adhesives as thermal interface materials (TIMs), the light performances of packaged high-brightness light-emitting diodes (HB-LEDs) were tested. The results indicated that the light output power of LED modules increased with the thermal conductivities of TIMs. Apart from its low bulk thermal resistance, highly thermal conductive adhesive has high adhesion with adjacent substrates which resulted in low contact thermal resistance, then the optical performance and reliability of LED package can be improved.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78876518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105694
Xiao Hong, P. Lai
The expansion of integrated circuit applications is driving chip costs down. To respond to the lower price the lower price expectations, manufacturers bring Plastic packages which is cost less expensive packaging solutions. Today although the electronic packaging industry there are still many enterprises were to have lead solder, but this does not preclude the “lead-free” has become the main topic of electronic materials and microelectronics. In this transitional period, lead and lead-free both assemble on the plastic package in the field of application is already unavoidable. Problem existed in lead or lead-free materials, technology, equipment, system compatibility and other issues. The reliability of the plastic package IC is becoming a key concern. The popcorn effect is caused when moisture inside a plastic package turns to steam and expands rapidly during infrared and vapor phase reflow solder process. Under certain conditions, the force from the expanding moisture can cause stresses inside the package. Solder ball inside with lead process and outside with lead-free may result in failure. It is prompted by the melting point of lead and lead-free material is different in the same BGA packaging chip. In most severe cases, the packaging defects and the stress may result in external package cracks. And in this paper, a sample is given that the BGA packaging chip exist void in the die/die attach interface. Capillary phenomenon is present in the package closest to the die attach, and lead to a short circuit between some pins. Pay more attention to the reliability of mixed assembly process is of great value.
{"title":"The popcorn effect of lead and lead-free mixed assembly process in high density plastic packages","authors":"Xiao Hong, P. Lai","doi":"10.1109/ISAPM.2011.6105694","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105694","url":null,"abstract":"The expansion of integrated circuit applications is driving chip costs down. To respond to the lower price the lower price expectations, manufacturers bring Plastic packages which is cost less expensive packaging solutions. Today although the electronic packaging industry there are still many enterprises were to have lead solder, but this does not preclude the “lead-free” has become the main topic of electronic materials and microelectronics. In this transitional period, lead and lead-free both assemble on the plastic package in the field of application is already unavoidable. Problem existed in lead or lead-free materials, technology, equipment, system compatibility and other issues. The reliability of the plastic package IC is becoming a key concern. The popcorn effect is caused when moisture inside a plastic package turns to steam and expands rapidly during infrared and vapor phase reflow solder process. Under certain conditions, the force from the expanding moisture can cause stresses inside the package. Solder ball inside with lead process and outside with lead-free may result in failure. It is prompted by the melting point of lead and lead-free material is different in the same BGA packaging chip. In most severe cases, the packaging defects and the stress may result in external package cracks. And in this paper, a sample is given that the BGA packaging chip exist void in the die/die attach interface. Capillary phenomenon is present in the package closest to the die attach, and lead to a short circuit between some pins. Pay more attention to the reliability of mixed assembly process is of great value.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81316229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105674
Xin Luo, Wenhui Du, Xiuzhen Lu, Toshikazu Yamaguchi, J. Gavin, L. Ye, Johan Liu
The composition and thickness of surface oxide of solder particles has a direct effect on adhesion and electrical resistance of soldering joint and resultant the quality of interconnect and the reliability of packaged system. Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) were used to examine the oxide layer on solder powders in the present paper. However, for the surface oxide layer of a lead-free solder particle, the TEM sample for the oxide layer has never been done for studying its thickness or appearance before. And it is the first time in this work to use Focus Ion Beam (FIB) technology to prepare TEM specimen for solder particles and show TEM pictures of their surface oxide layer. High angle annular dark field (HAADF) pattern was applied to distinguish between the oxide layer and the solder matrix by the contrast of average atomic number. The solder powders were exposed in air (70% relative humidity) at 150°C for 0, 120 and 240 h to simulate the accelerated growth of oxide. The surface oxide thickness was 6 nm and 50 nm measured by TEM for 0 h and 120 h samples respectively. Confirming by AES measurement, the thickness of 5 nm and 50 nm were gotten using intersection analysis method for AES depth profiles. It is found that the increase of surface oxide thickness of solder particles is proportional to the rooting of time. The elemental distribution along the oxide was quantified by line scanning using STEM and the atomic ratio of Sn to O in the oxide layer nearer to the outer, the middle, and the inner (adjacent to the solder matrix) were found to be 1:2, 2:3 and 1:1, respectively. The result was validated using XPS which gave Sn to O ratio of 1:2 at 5 nm depth of surface oxide.
{"title":"Investigation of accelerated surface oxidation of Sn-3.5Ag-0.5Cu solder particles by TEM and STEM","authors":"Xin Luo, Wenhui Du, Xiuzhen Lu, Toshikazu Yamaguchi, J. Gavin, L. Ye, Johan Liu","doi":"10.1109/ISAPM.2011.6105674","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105674","url":null,"abstract":"The composition and thickness of surface oxide of solder particles has a direct effect on adhesion and electrical resistance of soldering joint and resultant the quality of interconnect and the reliability of packaged system. Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) were used to examine the oxide layer on solder powders in the present paper. However, for the surface oxide layer of a lead-free solder particle, the TEM sample for the oxide layer has never been done for studying its thickness or appearance before. And it is the first time in this work to use Focus Ion Beam (FIB) technology to prepare TEM specimen for solder particles and show TEM pictures of their surface oxide layer. High angle annular dark field (HAADF) pattern was applied to distinguish between the oxide layer and the solder matrix by the contrast of average atomic number. The solder powders were exposed in air (70% relative humidity) at 150°C for 0, 120 and 240 h to simulate the accelerated growth of oxide. The surface oxide thickness was 6 nm and 50 nm measured by TEM for 0 h and 120 h samples respectively. Confirming by AES measurement, the thickness of 5 nm and 50 nm were gotten using intersection analysis method for AES depth profiles. It is found that the increase of surface oxide thickness of solder particles is proportional to the rooting of time. The elemental distribution along the oxide was quantified by line scanning using STEM and the atomic ratio of Sn to O in the oxide layer nearer to the outer, the middle, and the inner (adjacent to the solder matrix) were found to be 1:2, 2:3 and 1:1, respectively. The result was validated using XPS which gave Sn to O ratio of 1:2 at 5 nm depth of surface oxide.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88921120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105707
Y. Tao, Y. P. Wu, B. Wu, M. Cai
Recently, a serious crack issue for a commercial BGA has taken place frequently in the normal PCBA assembly line, which has lead to abnormal failure rate spikes in the first pass yield trend chart, and caused line down issue already. Both cross section and Dye & Pry has been carried out to find out the fracture mode in the suspected pin of the failed unit. The cross section result shows that both BGA solder separation and PCB prepreg separation occurs there. Dye & Pry reveals that the crack pins mainly gather at corner “D” of this BGA, and 100% dye is presented there. In order to find out the root cause of this case, a series of destructive experiments have been carried out. Firstly, shear test of the raw BGA solder joint are performed. It reveals that there is no obvious difference for the solder strength between the BGA balls at the four corners and those in the center area, which indicates that the BGA raw material is not related to the root cause of this case. Secondly, in order to identify the point at which the ball crack are starting in production line, samples including bare PCB and assembled PCBA have been collected at different work station in both SMT and product build line, which will all act as the experiment specimens for a series of cross section and Dye & Pry of next step. The results show that the FCT (Functional Circuit Test) after SMT line is one of the suspected stations where the solder crack initiation will take place. After that, Strain gauge has been performed to check in both these locations, and the results show that the strain value is out of spec. Finally, some idle probes under BGA in FCT is suggested to be the root cause to trigger solder crack initiation, and both cross section and Dye & Pry result proves that the BGA crack issue can be solved after removing those probes.
{"title":"Investigation of BGA crack issue in normal production line","authors":"Y. Tao, Y. P. Wu, B. Wu, M. Cai","doi":"10.1109/ISAPM.2011.6105707","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105707","url":null,"abstract":"Recently, a serious crack issue for a commercial BGA has taken place frequently in the normal PCBA assembly line, which has lead to abnormal failure rate spikes in the first pass yield trend chart, and caused line down issue already. Both cross section and Dye & Pry has been carried out to find out the fracture mode in the suspected pin of the failed unit. The cross section result shows that both BGA solder separation and PCB prepreg separation occurs there. Dye & Pry reveals that the crack pins mainly gather at corner “D” of this BGA, and 100% dye is presented there. In order to find out the root cause of this case, a series of destructive experiments have been carried out. Firstly, shear test of the raw BGA solder joint are performed. It reveals that there is no obvious difference for the solder strength between the BGA balls at the four corners and those in the center area, which indicates that the BGA raw material is not related to the root cause of this case. Secondly, in order to identify the point at which the ball crack are starting in production line, samples including bare PCB and assembled PCBA have been collected at different work station in both SMT and product build line, which will all act as the experiment specimens for a series of cross section and Dye & Pry of next step. The results show that the FCT (Functional Circuit Test) after SMT line is one of the suspected stations where the solder crack initiation will take place. After that, Strain gauge has been performed to check in both these locations, and the results show that the strain value is out of spec. Finally, some idle probes under BGA in FCT is suggested to be the root cause to trigger solder crack initiation, and both cross section and Dye & Pry result proves that the BGA crack issue can be solved after removing those probes.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72789702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105739
Shi Lingfeng, Xia Yuanming, Zhang Ke, Jia Jun, Liu Chen, Lai Xin-quan
Currently, the multilayer Package-on-Package (PoP) stacking technique as the mainstream 3D vertical packaging solution is extensively applied in the manufacture process of portable electronic instruments. While the warpages on the packages caused by the mismatch of the Coefficient of Thermal Expansion (CTE) and stiffness during the assembly and stacking processes are seriously threaten to the stability and reliability. In this paper, a novel four layers PoP stacking technique in which the number of memory die packaged are increased to twice of the traditional two layers PoP is presented. The metal cylinders with stable CTE are placed between the neighboring layers to reduce the warpages on the packages. The high memory density and excellent reliability could meet the requirements of the miniaturization and lightening of the portable instruments.
{"title":"A novel four layers package-on-package stacking technique","authors":"Shi Lingfeng, Xia Yuanming, Zhang Ke, Jia Jun, Liu Chen, Lai Xin-quan","doi":"10.1109/ISAPM.2011.6105739","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105739","url":null,"abstract":"Currently, the multilayer Package-on-Package (PoP) stacking technique as the mainstream 3D vertical packaging solution is extensively applied in the manufacture process of portable electronic instruments. While the warpages on the packages caused by the mismatch of the Coefficient of Thermal Expansion (CTE) and stiffness during the assembly and stacking processes are seriously threaten to the stability and reliability. In this paper, a novel four layers PoP stacking technique in which the number of memory die packaged are increased to twice of the traditional two layers PoP is presented. The metal cylinders with stable CTE are placed between the neighboring layers to reduce the warpages on the packages. The high memory density and excellent reliability could meet the requirements of the miniaturization and lightening of the portable instruments.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78264464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105715
Hongwu Zhang, F. Sun, Yang Liu, Zhenya Zhou, Y. Qin
Dynamic voltage signal across solder joints during mechanical vibration test was monitored and collected real-timely with a self-designed data acquisition system. Failure process of solder joint was studied by processing and analyzing data. In the paper, lifetime of solder joint was also compared by changing solder joint location, solder joint composition and vibration acceleration. Results indicated that voltage across solder joints kept at about 0.14v from 0s to 40s, which indicated that crack of solder joint did not form. Voltage of solder joint suddenly rose to 0.45v between 44.2s and 45.2s, which illustrated crack initiation and growth rapidly. In addition, lifetime of solder joint on the edge of test board was about 4.5 times longer than that of solder joint in the center of test board. It was found that with vibration acceleration from 20g to 25g increase of 25%, lifetime of solder joint decreased from 980s to 105s with 89%.
{"title":"Failure process of solder joint under mechanical vibration based on a real-time data acquisition method","authors":"Hongwu Zhang, F. Sun, Yang Liu, Zhenya Zhou, Y. Qin","doi":"10.1109/ISAPM.2011.6105715","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105715","url":null,"abstract":"Dynamic voltage signal across solder joints during mechanical vibration test was monitored and collected real-timely with a self-designed data acquisition system. Failure process of solder joint was studied by processing and analyzing data. In the paper, lifetime of solder joint was also compared by changing solder joint location, solder joint composition and vibration acceleration. Results indicated that voltage across solder joints kept at about 0.14v from 0s to 40s, which indicated that crack of solder joint did not form. Voltage of solder joint suddenly rose to 0.45v between 44.2s and 45.2s, which illustrated crack initiation and growth rapidly. In addition, lifetime of solder joint on the edge of test board was about 4.5 times longer than that of solder joint in the center of test board. It was found that with vibration acceleration from 20g to 25g increase of 25%, lifetime of solder joint decreased from 980s to 105s with 89%.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78334169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105734
J. Liao, S. Liu, Y. T. Yu, Y. Lin, G. Jin, G. Huang, Z. Fu
The ability to improve the mechanical properties of a microelectronic package, including reducing the thermal-mechanical stress and increasing the die breaking strength is a long-sought goal in electrical assembly and packaging technology. Failure modes related with die backside stress caused by warpage or cosmetic defects may occur without a well control of die-backside stress. In this study, the modifications of die backside stress by coating of a thin layer of AlN or Si3N4 have been investigated. The simulation through the Finite Element Method (FEM) indicated that the stress distribution can be modified after coating and it is strongly related to the thickness of the coated layer, as the stress of die backside surface reduces. Die breaking strength has been measured by 3 point bending test and the measurement results are compared between samples with and without coatings. It is demonstrated that the die breaking strength is related with the thickness and the surface roughness of the coating layer of AlN or Si3N4. Improvement in the die breaking strength can be realized when the thickness and surface roughness are both optimized. The results suggested the additional coating of the die backside may be a feasible way to improve the mechanical properties of the electronic packages.
{"title":"Die backside stress modification by coating of Si3N4 or AlN layers","authors":"J. Liao, S. Liu, Y. T. Yu, Y. Lin, G. Jin, G. Huang, Z. Fu","doi":"10.1109/ISAPM.2011.6105734","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105734","url":null,"abstract":"The ability to improve the mechanical properties of a microelectronic package, including reducing the thermal-mechanical stress and increasing the die breaking strength is a long-sought goal in electrical assembly and packaging technology. Failure modes related with die backside stress caused by warpage or cosmetic defects may occur without a well control of die-backside stress. In this study, the modifications of die backside stress by coating of a thin layer of AlN or Si3N4 have been investigated. The simulation through the Finite Element Method (FEM) indicated that the stress distribution can be modified after coating and it is strongly related to the thickness of the coated layer, as the stress of die backside surface reduces. Die breaking strength has been measured by 3 point bending test and the measurement results are compared between samples with and without coatings. It is demonstrated that the die breaking strength is related with the thickness and the surface roughness of the coating layer of AlN or Si3N4. Improvement in the die breaking strength can be realized when the thickness and surface roughness are both optimized. The results suggested the additional coating of the die backside may be a feasible way to improve the mechanical properties of the electronic packages.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76675176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105742
Hongfu Zhou, Jianbin Wang
4,4′-Diphenyl Bismaleimide/Diallyl Bisphenol A/Bisphenol-A Cyanate Ester/Epoxy Resin copolymer matrix resins were developed by fusion prepolymerization and solution prepolymerization method, and use the bismaleimide (BMI)-based copolymer matrix resins/glass fabric prepared for copper clad laminates, which illustrate Tg at 230.7°C, dielectric constant at 3.57(1MHz) and dielectric loss constant at 0.0053(1MHz), volume resistivity at 2.3×1013Ω·cm and surface resistivity at 2.4×1015Ω, thermal expansion coefficient at 1.1×10–5/°C (x y-axis) and 5.7×10–5/°C (z-axis), dip soldering of resistance(288°C) is more than 62s, peel strength at 16.7N/cm, flexural strength at 458.3MP, moisture absorption at 0.19%, the test results explain that the performance is better than Japanese product copper clad laminates with bismaleimide/triazine-based resin(BT resin).
{"title":"Preparation of copper clad laminates with high performance bismaleimide-based copolymer matrix resins","authors":"Hongfu Zhou, Jianbin Wang","doi":"10.1109/ISAPM.2011.6105742","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105742","url":null,"abstract":"4,4′-Diphenyl Bismaleimide/Diallyl Bisphenol A/Bisphenol-A Cyanate Ester/Epoxy Resin copolymer matrix resins were developed by fusion prepolymerization and solution prepolymerization method, and use the bismaleimide (BMI)-based copolymer matrix resins/glass fabric prepared for copper clad laminates, which illustrate Tg at 230.7°C, dielectric constant at 3.57(1MHz) and dielectric loss constant at 0.0053(1MHz), volume resistivity at 2.3×1013Ω·cm and surface resistivity at 2.4×1015Ω, thermal expansion coefficient at 1.1×10–5/°C (x y-axis) and 5.7×10–5/°C (z-axis), dip soldering of resistance(288°C) is more than 62s, peel strength at 16.7N/cm, flexural strength at 458.3MP, moisture absorption at 0.19%, the test results explain that the performance is better than Japanese product copper clad laminates with bismaleimide/triazine-based resin(BT resin).","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80548114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105693
Bin Yao, P. Lai, J. Liu, Xiaosi Liang
The trend of electronics industry is toward advanced high density packaging technologies. The reliability of integrated circuits (ICs) which is significantly affected by thermal stress has become more essential as the packaging density increases. In this paper, an accelerated thermal reliability test method for evaluating the packaging reliability of ICs which includes hot step, cold step and rapid thermal cycling test is presented. The technology of FIMV (Force current measure voltage) was applied during the reliability test as an indicator of degradation of packaging property, which allowed the reliability performance of ICs to be assessed in real time. The experimental results showed that the thermal stress resulted in the degradation of interfacial adhesion of plastic packaging ICs. Because of the temperature changing during the rapid thermal test, the strain and stress due to the coefficient of thermal expansion (CTE) mismatch between the encapsulant and the adjacent materials could contribute to delamination or de-adhesion. In some cases it was directly linked to a failure if some severe defects occured because of delamination, such as wire bond lift-off or fracture. Crack in die attach adhesive based on the same failure mechanism was also found. Additionally, unwanted brittle Au-Al intermetallic compound was detected at the bond interface because of the effect of high temperature. The formation of the Au-Al intermetallic compound led to the increase of electrical resistance and the weakening of bond strength which resulted in bond lift-off finally. At last future research work in this field is suggested.
电子工业的发展趋势是采用先进的高密度封装技术。随着封装密度的增加，受热应力影响较大的集成电路的可靠性变得越来越重要。本文提出了一种集成电路封装可靠性的加速热可靠性测试方法，包括热步、冷步和快速热循环测试。在可靠性测试中，采用FIMV (Force current measure voltage)技术作为封装性能退化的指标，实时评估集成电路的可靠性性能。实验结果表明，热应力会导致塑料封装集成电路的界面附着力下降。在快速热测试过程中，由于温度的变化，由于封装剂与邻近材料之间的热膨胀系数(CTE)不匹配而产生的应变和应力可能导致分层或脱粘。在某些情况下，如果由于分层而发生严重缺陷，例如钢丝粘结脱落或断裂，则与故障直接相关。基于相同的失效机理，还发现了模具粘接胶的裂纹。此外，由于高温的影响，在键界面处发现了多余的脆性金铝金属间化合物。Au-Al金属间化合物的形成导致电阻增大，粘结强度减弱，最终导致粘结脱落。最后对该领域今后的研究工作提出了建议。
{"title":"The effect of thermal stress on high density packaging integrated circuits","authors":"Bin Yao, P. Lai, J. Liu, Xiaosi Liang","doi":"10.1109/ISAPM.2011.6105693","DOIUrl":"https://doi.org/10.1109/ISAPM.2011.6105693","url":null,"abstract":"The trend of electronics industry is toward advanced high density packaging technologies. The reliability of integrated circuits (ICs) which is significantly affected by thermal stress has become more essential as the packaging density increases. In this paper, an accelerated thermal reliability test method for evaluating the packaging reliability of ICs which includes hot step, cold step and rapid thermal cycling test is presented. The technology of FIMV (Force current measure voltage) was applied during the reliability test as an indicator of degradation of packaging property, which allowed the reliability performance of ICs to be assessed in real time. The experimental results showed that the thermal stress resulted in the degradation of interfacial adhesion of plastic packaging ICs. Because of the temperature changing during the rapid thermal test, the strain and stress due to the coefficient of thermal expansion (CTE) mismatch between the encapsulant and the adjacent materials could contribute to delamination or de-adhesion. In some cases it was directly linked to a failure if some severe defects occured because of delamination, such as wire bond lift-off or fracture. Crack in die attach adhesive based on the same failure mechanism was also found. Additionally, unwanted brittle Au-Al intermetallic compound was detected at the bond interface because of the effect of high temperature. The formation of the Au-Al intermetallic compound led to the increase of electrical resistance and the weakening of bond strength which resulted in bond lift-off finally. At last future research work in this field is suggested.","PeriodicalId":6440,"journal":{"name":"2011 International Symposium on Advanced Packaging Materials (APM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84056128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-19DOI: 10.1109/ISAPM.2011.6105683
S. Gao, Yibin Chen, Renjie Zeng
Y3−xCexAl5O12 (YAG: Ce3+) phosphor particles were prepared by a new method called co-precipitation and low temperature spray pyrolysis (CP-LTSP) with oxalic acid and ammonia as precipitant. It corresponds to the first-step chemical liquid reaction, the second step dehydration and partial decomposition of precipitation droplets at 250°C and then heating at 1100°C or above. Spherical as-prepared particles and agglomerate-free YAG: Ce3+ phosphor particles were obtained respectively. Pure YAG phase could be formed after LTSP at 250°C and then annealing at 1100°C for 4 h. The emission spectra and XRD patterns of YAG: Ce3+ phosphor particles indicated that the optimum doping concentration of Ce3+ was 0.06. The emission intensity increased with the increase of annealing temperature. As a result, the YAG: Ce3+ phosphor particles without optimization annealed at 1550°C for 4 h had the similar emission intensity (96%) of the commercial phosphor by the solid-state method.
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