Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804071
A. Azhari, T. Kikkawa
A DC-20 GHz differential transmit/receive (T/R) double-pole-four-throw (DP4T) switching matrix has been developed on standard 65 nm CMOS process for the first time for ultra-wideband radar based tumor detection. The measured input and output matching bandwidth are 0–20 GHz where both the input and output return losses are greater than 10 dB. Measured average insertion loss from Tx or Rx port to different output ports are 2.72 dB, 3.6 dB, 4.5 dB and 5.9 dB at 3 GHz, 6 GHz, 10 GHz and 17 GHz, respectively, with a power consumption of less than 1 mW. When the output ports were connected to PCB connectors, 0–18 GHz matching bandwidth was obtained by flip chip mounting, quarter wavelength microstripline impedance matching and optimization of the thickness and dielectric constant of printed circuit board.
{"title":"DC-20 GHz differential transmit/receieve DP4T switching matrix for radar-based target detection","authors":"A. Azhari, T. Kikkawa","doi":"10.1109/APCCAS.2016.7804071","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804071","url":null,"abstract":"A DC-20 GHz differential transmit/receive (T/R) double-pole-four-throw (DP4T) switching matrix has been developed on standard 65 nm CMOS process for the first time for ultra-wideband radar based tumor detection. The measured input and output matching bandwidth are 0–20 GHz where both the input and output return losses are greater than 10 dB. Measured average insertion loss from Tx or Rx port to different output ports are 2.72 dB, 3.6 dB, 4.5 dB and 5.9 dB at 3 GHz, 6 GHz, 10 GHz and 17 GHz, respectively, with a power consumption of less than 1 mW. When the output ports were connected to PCB connectors, 0–18 GHz matching bandwidth was obtained by flip chip mounting, quarter wavelength microstripline impedance matching and optimization of the thickness and dielectric constant of printed circuit board.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"77 1","pages":"706-709"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90648997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804019
Inhyuk Choi, Hyunggoy Oh, Sungho Kang
In this paper, the reconfigurable test access mechanism (RTAM) is designed based on the emerging test standard to reduce the cumulative stack test time of the 3-dimensional integrated circuit (3-D IC). The RTAM enables the test scheduling to reflect the variation of the test constraints in the overall stack test phases. Simulation results show the RTAM achieves the cumulative stack test time reduction compared with a non-reconfigurable TAM for the stacked dies in the 3-D IC.
{"title":"Test access mechaism for stack test time reduction of 3-dimensional integrated circuit","authors":"Inhyuk Choi, Hyunggoy Oh, Sungho Kang","doi":"10.1109/APCCAS.2016.7804019","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804019","url":null,"abstract":"In this paper, the reconfigurable test access mechanism (RTAM) is designed based on the emerging test standard to reduce the cumulative stack test time of the 3-dimensional integrated circuit (3-D IC). The RTAM enables the test scheduling to reflect the variation of the test constraints in the overall stack test phases. Simulation results show the RTAM achieves the cumulative stack test time reduction compared with a non-reconfigurable TAM for the stacked dies in the 3-D IC.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"5 1","pages":"522-525"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84329650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804058
T. Adiono, Angga Pradana, Rachmad Vidya Wicaksana Putra, S. Fuada
Visible Light Communication (VLC) technology in indoor implementation is challenged by ambient light and other lighting noise, such as fluorescent lamp and bulb. The ambient light could create a DC offset or signal with specific frequency range. Thus, we propose analog filters design in the VLC Analog Front-End (AFE) receiver that can eliminate the ambient light noise. The proposed design uses DC offset removal, incorporated with automatic and manual adjustment mode. In automatic mode, we design the analog filter using High Pass Filter (HPF) which have fc = 10Hz; meanwhile, in manual mode we design a reference circuit using potentiometer and differential amplifier for direct current blocking. For reducing signal interference from lamp flickering, the proposed design uses Band Stop Filter (BSF) which has fc = 100Hz. The experimental results, both simulation and realtime, show that our proposed design can reduce signal interference and ambient light. We also test the design using PWM and BPSK modulation to evaluate Bit Error Rate (BER) performance.
{"title":"Analog filters design in VLC analog front-end receiver for reducing indoor ambient light noise","authors":"T. Adiono, Angga Pradana, Rachmad Vidya Wicaksana Putra, S. Fuada","doi":"10.1109/APCCAS.2016.7804058","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804058","url":null,"abstract":"Visible Light Communication (VLC) technology in indoor implementation is challenged by ambient light and other lighting noise, such as fluorescent lamp and bulb. The ambient light could create a DC offset or signal with specific frequency range. Thus, we propose analog filters design in the VLC Analog Front-End (AFE) receiver that can eliminate the ambient light noise. The proposed design uses DC offset removal, incorporated with automatic and manual adjustment mode. In automatic mode, we design the analog filter using High Pass Filter (HPF) which have fc = 10Hz; meanwhile, in manual mode we design a reference circuit using potentiometer and differential amplifier for direct current blocking. For reducing signal interference from lamp flickering, the proposed design uses Band Stop Filter (BSF) which has fc = 100Hz. The experimental results, both simulation and realtime, show that our proposed design can reduce signal interference and ambient light. We also test the design using PWM and BPSK modulation to evaluate Bit Error Rate (BER) performance.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"10 1","pages":"581-584"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86580974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803961
T. Shindo, K. Jin'no
There are several types of switching pattern design of the matrix converter. In this paper, we discuss the switching pattern design of the matrix converter. As a new switching pattern design method, the application of the PSO, which is one of the non-linear optimization method. Further, the switching pattern is confirmed generated from numerical experiments.
{"title":"Particle swarm optimization for matrix converter of switching pattern design","authors":"T. Shindo, K. Jin'no","doi":"10.1109/APCCAS.2016.7803961","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803961","url":null,"abstract":"There are several types of switching pattern design of the matrix converter. In this paper, we discuss the switching pattern design of the matrix converter. As a new switching pattern design method, the application of the PSO, which is one of the non-linear optimization method. Further, the switching pattern is confirmed generated from numerical experiments.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"22 1","pages":"309-312"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87652431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804002
Zhen Yu, Hai-Ning Liang, Charles Fleming, K. Man
Usable security for virtual reality systems (VR) is an area that is relatively underexplored. This research investigates the feasibility of some authentication mechanisms for VR. We implemented three password methods including 3D patterns, 2D sliding patterns, and a PIN system within a VR environment. Two experiments were conducted to test the usability and security level of the three password systems. The results suggested that the 3D password system may have the highest security level among the three systems, whereas the pattern lock and PIN systems were likely to be perceived as more usable.
{"title":"An exploration of usable authentication mechanisms for virtual reality systems","authors":"Zhen Yu, Hai-Ning Liang, Charles Fleming, K. Man","doi":"10.1109/APCCAS.2016.7804002","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804002","url":null,"abstract":"Usable security for virtual reality systems (VR) is an area that is relatively underexplored. This research investigates the feasibility of some authentication mechanisms for VR. We implemented three password methods including 3D patterns, 2D sliding patterns, and a PIN system within a VR environment. Two experiments were conducted to test the usability and security level of the three password systems. The results suggested that the 3D password system may have the highest security level among the three systems, whereas the pattern lock and PIN systems were likely to be perceived as more usable.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"458-460"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82986663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803919
Ching-Wen Lin, C. Chen
Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.
{"title":"A processor shield for software-based on-line self-test","authors":"Ching-Wen Lin, C. Chen","doi":"10.1109/APCCAS.2016.7803919","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803919","url":null,"abstract":"Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 5 1","pages":"149-152"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82876060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804001
J. Wang, M. Leach, Zhao Wang, K. Man, E. Lim
Research is increasingly focusing on energy harvesting as energy demands continue to rise and natural resources begin to deplete. This paper briefly introduces a basic framework of the rectifying antenna (rectenna) system and three different examples of rectennas for RF energy harvesting and wireless power transmission.
{"title":"Rectanna design for energy harvesting","authors":"J. Wang, M. Leach, Zhao Wang, K. Man, E. Lim","doi":"10.1109/APCCAS.2016.7804001","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804001","url":null,"abstract":"Research is increasingly focusing on energy harvesting as energy demands continue to rise and natural resources begin to deplete. This paper briefly introduces a basic framework of the rectifying antenna (rectenna) system and three different examples of rectennas for RF energy harvesting and wireless power transmission.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"11 1","pages":"456-457"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90185263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803924
D. Rieth, C. Heller, G. Ascheid
Shaped Offset QPSK (SOQPSK) is a highly bandwidth-efficient constant envelope waveform. In order to increase hardware and energy efficiency, a new architecture for fully coherent SOQPSK demodulation is proposed that is suitable for continuous and burst mode transmission. It contains Decision-Directed (DD) synchronization loops for frequency, phase and timing offsets and a low complex method combining robust Start of Frame (SoF) detection with Phase Ambiguity Resolution (PAR) based on nested Barker codes. A coarse grained pipeline structure aims for minimal clock speeds and energy consumption while keeping the overall throughput high. Large complexity reductions are achieved by a multiplier-free Matched Filter (MF) design. Computer simulations and Field Programmable Gate Array (FPGA) implementation results show that the complexity-accuracy trade-offs have been reasonably chosen in terms of close-to-optimal Bit Error Rate (BER) performance and that hardware efficiency gains of more than 90 % compared with implementations from literature are achievable.
{"title":"Fully coherent shaped offset QPSK demodulator architecture with superior hardware efficiency","authors":"D. Rieth, C. Heller, G. Ascheid","doi":"10.1109/APCCAS.2016.7803924","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803924","url":null,"abstract":"Shaped Offset QPSK (SOQPSK) is a highly bandwidth-efficient constant envelope waveform. In order to increase hardware and energy efficiency, a new architecture for fully coherent SOQPSK demodulation is proposed that is suitable for continuous and burst mode transmission. It contains Decision-Directed (DD) synchronization loops for frequency, phase and timing offsets and a low complex method combining robust Start of Frame (SoF) detection with Phase Ambiguity Resolution (PAR) based on nested Barker codes. A coarse grained pipeline structure aims for minimal clock speeds and energy consumption while keeping the overall throughput high. Large complexity reductions are achieved by a multiplier-free Matched Filter (MF) design. Computer simulations and Field Programmable Gate Array (FPGA) implementation results show that the complexity-accuracy trade-offs have been reasonably chosen in terms of close-to-optimal Bit Error Rate (BER) performance and that hardware efficiency gains of more than 90 % compared with implementations from literature are achievable.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 1","pages":"168-171"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90237444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803894
Haicheng Tu, Yongxiang Xia, H. Iu, Chi K. Tse
Cascading failures happened in power grids degrade the robustness of such complex systems. In the cascading process, links can be critical for the propagation of failures. Then It is possible that switching off some links may help the network improve its robustness. In this paper, with the consideration of both the electrical characteristics and complex network structure, we try to assess how the robustness of the IEEE 118 Bus can be improved by switching off a set of transmission links. An evolution algorithm is applied to achieve the optimal performance. Simulation results show that the proposed strategy can effectively relieve the damage to the power system caused by cascading failures at a low cost.
{"title":"Improving robustness of power systems via optimal link switch-off","authors":"Haicheng Tu, Yongxiang Xia, H. Iu, Chi K. Tse","doi":"10.1109/APCCAS.2016.7803894","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803894","url":null,"abstract":"Cascading failures happened in power grids degrade the robustness of such complex systems. In the cascading process, links can be critical for the propagation of failures. Then It is possible that switching off some links may help the network improve its robustness. In this paper, with the consideration of both the electrical characteristics and complex network structure, we try to assess how the robustness of the IEEE 118 Bus can be improved by switching off a set of transmission links. An evolution algorithm is applied to achieve the optimal performance. Simulation results show that the proposed strategy can effectively relieve the damage to the power system caused by cascading failures at a low cost.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"163 1","pages":"54-56"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80320426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803905
Sijie Pan, P. Mok
This paper proposes a single on/off reference tracking buck converter for DVFS application with a novel turning point prediction based on the turning point of the output voltage. The equation to determine the turning point of the output voltage for optimal reference tracking is analyzed and implemented by a current multiplier and divider circuit. In addition, a new reference tracking scheme is introduced to avoid undershoot of output voltage caused by load change. This work is simulated in a 0.13-μm CMOS process and simulation results show fast reference tracking capability with 1.48 μs/V for up reference tracking, 1.91 μs/V for down reference tracking, and effective reduction of the undershoot and overshoot problem.
{"title":"A single on/off reference tracking buck converter using turning point prediction for DVFS application","authors":"Sijie Pan, P. Mok","doi":"10.1109/APCCAS.2016.7803905","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803905","url":null,"abstract":"This paper proposes a single on/off reference tracking buck converter for DVFS application with a novel turning point prediction based on the turning point of the output voltage. The equation to determine the turning point of the output voltage for optimal reference tracking is analyzed and implemented by a current multiplier and divider circuit. In addition, a new reference tracking scheme is introduced to avoid undershoot of output voltage caused by load change. This work is simulated in a 0.13-μm CMOS process and simulation results show fast reference tracking capability with 1.48 μs/V for up reference tracking, 1.91 μs/V for down reference tracking, and effective reduction of the undershoot and overshoot problem.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"112 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76869774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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