Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804077
C. Jang, Sanghun Kim, Young Hwan Kim
This paper proposes the power constrained contrast enhancement algorithm for OLED display based on the multi-mapping functions for improving the local contrast of the input image. The proposed method divides the input image into several blocks. Then, it calculates the multi-mapping functions corresponding to each block using convex optimization process between the image quality and power consumption. Using the multi-mapping function, the proposed method adjusts the mapping function and calculates the output image using the bilinear interpolation. In the experimental results, the proposed method improved the local contrast, and increased the enhancement performance measure and sharpness by up to 57.8% and 41.9% compared to benchmark methods.
{"title":"Contrast enhancement using multiple mapping functions for power reduction in OLED display","authors":"C. Jang, Sanghun Kim, Young Hwan Kim","doi":"10.1109/APCCAS.2016.7804077","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804077","url":null,"abstract":"This paper proposes the power constrained contrast enhancement algorithm for OLED display based on the multi-mapping functions for improving the local contrast of the input image. The proposed method divides the input image into several blocks. Then, it calculates the multi-mapping functions corresponding to each block using convex optimization process between the image quality and power consumption. Using the multi-mapping function, the proposed method adjusts the mapping function and calculates the output image using the bilinear interpolation. In the experimental results, the proposed method improved the local contrast, and increased the enhancement performance measure and sharpness by up to 57.8% and 41.9% compared to benchmark methods.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"61 1","pages":"725-726"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77863828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803981
N. S. Ahmad, S. J. A. Bakar
Due to nonlinear behavior of several phase-detectors, linear approximation method often leads to performance degradation in many phase-controlled systems, particularly when the phase errors are sufficiently large. In this work, with the nonlinearity considered in the system's model, a suitable criterion which takes into account both the nonlinearity's sector and slope bounds is employed to establish its global stability condition. The result is then incorporated into the existing H∞ synthesis in the controller/loop filter design. The searches are expressed in terms of convex linear matrix inequalities which are computationally tractable. To illustrate the improvement introduced via this approach, several numerical examples are included with comparisons over conventional linear approximation methods.
{"title":"Phase-controlled system design via mixed H∞ synthesis and nonlinear method","authors":"N. S. Ahmad, S. J. A. Bakar","doi":"10.1109/APCCAS.2016.7803981","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803981","url":null,"abstract":"Due to nonlinear behavior of several phase-detectors, linear approximation method often leads to performance degradation in many phase-controlled systems, particularly when the phase errors are sufficiently large. In this work, with the nonlinearity considered in the system's model, a suitable criterion which takes into account both the nonlinearity's sector and slope bounds is employed to establish its global stability condition. The result is then incorporated into the existing H∞ synthesis in the controller/loop filter design. The searches are expressed in terms of convex linear matrix inequalities which are computationally tractable. To illustrate the improvement introduced via this approach, several numerical examples are included with comparisons over conventional linear approximation methods.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"19 1","pages":"380-383"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76871652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803894
Haicheng Tu, Yongxiang Xia, H. Iu, Chi K. Tse
Cascading failures happened in power grids degrade the robustness of such complex systems. In the cascading process, links can be critical for the propagation of failures. Then It is possible that switching off some links may help the network improve its robustness. In this paper, with the consideration of both the electrical characteristics and complex network structure, we try to assess how the robustness of the IEEE 118 Bus can be improved by switching off a set of transmission links. An evolution algorithm is applied to achieve the optimal performance. Simulation results show that the proposed strategy can effectively relieve the damage to the power system caused by cascading failures at a low cost.
{"title":"Improving robustness of power systems via optimal link switch-off","authors":"Haicheng Tu, Yongxiang Xia, H. Iu, Chi K. Tse","doi":"10.1109/APCCAS.2016.7803894","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803894","url":null,"abstract":"Cascading failures happened in power grids degrade the robustness of such complex systems. In the cascading process, links can be critical for the propagation of failures. Then It is possible that switching off some links may help the network improve its robustness. In this paper, with the consideration of both the electrical characteristics and complex network structure, we try to assess how the robustness of the IEEE 118 Bus can be improved by switching off a set of transmission links. An evolution algorithm is applied to achieve the optimal performance. Simulation results show that the proposed strategy can effectively relieve the damage to the power system caused by cascading failures at a low cost.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"163 1","pages":"54-56"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80320426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803919
Ching-Wen Lin, C. Chen
Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.
{"title":"A processor shield for software-based on-line self-test","authors":"Ching-Wen Lin, C. Chen","doi":"10.1109/APCCAS.2016.7803919","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803919","url":null,"abstract":"Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 5 1","pages":"149-152"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82876060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803938
Daisuke Oku, M. Yanagisawa, N. Togawa
Scan-path test, which is one of design-for-test techniques using a scan chain, can control and observe internal registers in an LSI chip. However, attackers can also use it to retrieve secret information from cipher circuits. Recently, scan-based attacks using a scan chain inside an LSI chip is reported which can restore secret information by analyzing the scan data during cryptographic processing. In this paper, we pick up a scan-based attack method against a Trivium cipher, one of synchronous stream ciphers, and evaluate it using the FPGA platform called SASEBO-GII. We implement the Trivium cipher on the FPGA chip and perform the scan-based attack against it. We demonstrate that the scan-based attack can successfully restore the secret information in the FPGA chip within several minutes, even if the FPGA chip contains several circuits other than the Trivium cipher circuit, which reveals that the scan-based attack against the Trivium cipher is not only a simulation threat but a real threat.
{"title":"Implementation evaluation of scan-based attack against a Trivium cipher circuit","authors":"Daisuke Oku, M. Yanagisawa, N. Togawa","doi":"10.1109/APCCAS.2016.7803938","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803938","url":null,"abstract":"Scan-path test, which is one of design-for-test techniques using a scan chain, can control and observe internal registers in an LSI chip. However, attackers can also use it to retrieve secret information from cipher circuits. Recently, scan-based attacks using a scan chain inside an LSI chip is reported which can restore secret information by analyzing the scan data during cryptographic processing. In this paper, we pick up a scan-based attack method against a Trivium cipher, one of synchronous stream ciphers, and evaluate it using the FPGA platform called SASEBO-GII. We implement the Trivium cipher on the FPGA chip and perform the scan-based attack against it. We demonstrate that the scan-based attack can successfully restore the secret information in the FPGA chip within several minutes, even if the FPGA chip contains several circuits other than the Trivium cipher circuit, which reveals that the scan-based attack against the Trivium cipher is not only a simulation threat but a real threat.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"15 1","pages":"220-223"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81833221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804058
T. Adiono, Angga Pradana, Rachmad Vidya Wicaksana Putra, S. Fuada
Visible Light Communication (VLC) technology in indoor implementation is challenged by ambient light and other lighting noise, such as fluorescent lamp and bulb. The ambient light could create a DC offset or signal with specific frequency range. Thus, we propose analog filters design in the VLC Analog Front-End (AFE) receiver that can eliminate the ambient light noise. The proposed design uses DC offset removal, incorporated with automatic and manual adjustment mode. In automatic mode, we design the analog filter using High Pass Filter (HPF) which have fc = 10Hz; meanwhile, in manual mode we design a reference circuit using potentiometer and differential amplifier for direct current blocking. For reducing signal interference from lamp flickering, the proposed design uses Band Stop Filter (BSF) which has fc = 100Hz. The experimental results, both simulation and realtime, show that our proposed design can reduce signal interference and ambient light. We also test the design using PWM and BPSK modulation to evaluate Bit Error Rate (BER) performance.
{"title":"Analog filters design in VLC analog front-end receiver for reducing indoor ambient light noise","authors":"T. Adiono, Angga Pradana, Rachmad Vidya Wicaksana Putra, S. Fuada","doi":"10.1109/APCCAS.2016.7804058","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804058","url":null,"abstract":"Visible Light Communication (VLC) technology in indoor implementation is challenged by ambient light and other lighting noise, such as fluorescent lamp and bulb. The ambient light could create a DC offset or signal with specific frequency range. Thus, we propose analog filters design in the VLC Analog Front-End (AFE) receiver that can eliminate the ambient light noise. The proposed design uses DC offset removal, incorporated with automatic and manual adjustment mode. In automatic mode, we design the analog filter using High Pass Filter (HPF) which have fc = 10Hz; meanwhile, in manual mode we design a reference circuit using potentiometer and differential amplifier for direct current blocking. For reducing signal interference from lamp flickering, the proposed design uses Band Stop Filter (BSF) which has fc = 100Hz. The experimental results, both simulation and realtime, show that our proposed design can reduce signal interference and ambient light. We also test the design using PWM and BPSK modulation to evaluate Bit Error Rate (BER) performance.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"10 1","pages":"581-584"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86580974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804001
J. Wang, M. Leach, Zhao Wang, K. Man, E. Lim
Research is increasingly focusing on energy harvesting as energy demands continue to rise and natural resources begin to deplete. This paper briefly introduces a basic framework of the rectifying antenna (rectenna) system and three different examples of rectennas for RF energy harvesting and wireless power transmission.
{"title":"Rectanna design for energy harvesting","authors":"J. Wang, M. Leach, Zhao Wang, K. Man, E. Lim","doi":"10.1109/APCCAS.2016.7804001","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804001","url":null,"abstract":"Research is increasingly focusing on energy harvesting as energy demands continue to rise and natural resources begin to deplete. This paper briefly introduces a basic framework of the rectifying antenna (rectenna) system and three different examples of rectennas for RF energy harvesting and wireless power transmission.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"11 1","pages":"456-457"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90185263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803924
D. Rieth, C. Heller, G. Ascheid
Shaped Offset QPSK (SOQPSK) is a highly bandwidth-efficient constant envelope waveform. In order to increase hardware and energy efficiency, a new architecture for fully coherent SOQPSK demodulation is proposed that is suitable for continuous and burst mode transmission. It contains Decision-Directed (DD) synchronization loops for frequency, phase and timing offsets and a low complex method combining robust Start of Frame (SoF) detection with Phase Ambiguity Resolution (PAR) based on nested Barker codes. A coarse grained pipeline structure aims for minimal clock speeds and energy consumption while keeping the overall throughput high. Large complexity reductions are achieved by a multiplier-free Matched Filter (MF) design. Computer simulations and Field Programmable Gate Array (FPGA) implementation results show that the complexity-accuracy trade-offs have been reasonably chosen in terms of close-to-optimal Bit Error Rate (BER) performance and that hardware efficiency gains of more than 90 % compared with implementations from literature are achievable.
{"title":"Fully coherent shaped offset QPSK demodulator architecture with superior hardware efficiency","authors":"D. Rieth, C. Heller, G. Ascheid","doi":"10.1109/APCCAS.2016.7803924","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803924","url":null,"abstract":"Shaped Offset QPSK (SOQPSK) is a highly bandwidth-efficient constant envelope waveform. In order to increase hardware and energy efficiency, a new architecture for fully coherent SOQPSK demodulation is proposed that is suitable for continuous and burst mode transmission. It contains Decision-Directed (DD) synchronization loops for frequency, phase and timing offsets and a low complex method combining robust Start of Frame (SoF) detection with Phase Ambiguity Resolution (PAR) based on nested Barker codes. A coarse grained pipeline structure aims for minimal clock speeds and energy consumption while keeping the overall throughput high. Large complexity reductions are achieved by a multiplier-free Matched Filter (MF) design. Computer simulations and Field Programmable Gate Array (FPGA) implementation results show that the complexity-accuracy trade-offs have been reasonably chosen in terms of close-to-optimal Bit Error Rate (BER) performance and that hardware efficiency gains of more than 90 % compared with implementations from literature are achievable.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 1","pages":"168-171"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90237444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804050
Minh Hai Tran, Kosuke Oi, Y. Uwate, Y. Nishio
In many cases, mutual synchronization systems consisting of a large number of oscillators are used for practical model. In this work, we investigate synchronization phenomena observed by adding different frequency van der Pol oscillators coupled with star combination. By computer simulations, we confirm some of oscillators in the system are synchronized at anti-phase.
{"title":"Synchronization phenomena in star-coupled van der pol oscillators by adding different frequency oscillators","authors":"Minh Hai Tran, Kosuke Oi, Y. Uwate, Y. Nishio","doi":"10.1109/APCCAS.2016.7804050","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804050","url":null,"abstract":"In many cases, mutual synchronization systems consisting of a large number of oscillators are used for practical model. In this work, we investigate synchronization phenomena observed by adding different frequency van der Pol oscillators coupled with star combination. By computer simulations, we confirm some of oscillators in the system are synchronized at anti-phase.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"76 1","pages":"629-632"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86087823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803921
Chun-Wei Chen, Fang-Kai Hsu, Der-Wei Yang, Jonas Wang, Ming-Der Shieh
Single-image super-resolution is widely adopted for high resolution display related applications. Example learning-based approaches can provide plenty of image details by using trained dataset. Regression-based methods reduce the memory storage size by training mapping functions instead of using a huge dictionary. The reconstructed image quality can be further enhanced by combining various prediction results. This work presents an effective model reconstruction method for enhanced predictions. The desired model can be constructed offline when using the local multi-gradient level pattern as the clustering feature. Applying the proposed schemes can further improve the quality of reconstructed high resolution image while retaining almost the same time complexity as the original solution. Experimental results exhibit that the quality of reconstructed image using the proposed schemes is very close to that of Yang's work, but the proposed one can operate much faster than his solutions. Moreover, the space for storing mapping functions can be dramatically reduced by using the proposed model combining method.
{"title":"Effective model construction for enhanced prediction in example-based super-resolution","authors":"Chun-Wei Chen, Fang-Kai Hsu, Der-Wei Yang, Jonas Wang, Ming-Der Shieh","doi":"10.1109/APCCAS.2016.7803921","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803921","url":null,"abstract":"Single-image super-resolution is widely adopted for high resolution display related applications. Example learning-based approaches can provide plenty of image details by using trained dataset. Regression-based methods reduce the memory storage size by training mapping functions instead of using a huge dictionary. The reconstructed image quality can be further enhanced by combining various prediction results. This work presents an effective model reconstruction method for enhanced predictions. The desired model can be constructed offline when using the local multi-gradient level pattern as the clustering feature. Applying the proposed schemes can further improve the quality of reconstructed high resolution image while retaining almost the same time complexity as the original solution. Experimental results exhibit that the quality of reconstructed image using the proposed schemes is very close to that of Yang's work, but the proposed one can operate much faster than his solutions. Moreover, the space for storing mapping functions can be dramatically reduced by using the proposed model combining method.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"14 1","pages":"156-159"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86027096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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