首页 > 最新文献

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献

英文 中文
A low power and compact physical unclonable function based on the cascode current mirrors 基于级联码电流镜的低功耗、紧凑的物理不可克隆功能
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803913
Shibang Lin, Dejian Liang, Yuan Cao, Xiaofang Pan, Xiaojin Zhao
In this paper, we present a novel on-chip physical unclonable function (PUF) based on the cascode current mirrors. It exploits the process variation of a single transistor as the load of the current mirror to generate a reliable digital signature for the chip. By employing a cascode NMOS transistor in the current-mode PUF architecture, the proposed PUF greatly boosts the output impedance. As a result, the tiny mismatch current can be amplified to a large output voltage swing. In addition, the area overhead per bit is only two minimum-sized NMOS transistors: one for the load of the current mirror, the other one for the selecting switch. Moreover, the proposed PUF design is validated by our extensive post-layout simulation using UMC 65nm CMOS technology, with a power consumption per bit as low as 0.13μW. The average area for each response bit extracted from the design layout is 5.47μm2.
本文提出了一种基于级联码电流镜的片上物理不可克隆函数(PUF)。它利用单个晶体管的工艺变化作为电流反射镜的负载,为芯片生成可靠的数字签名。通过在电流模式PUF结构中采用级联编码NMOS晶体管,所提出的PUF极大地提高了输出阻抗。因此,微小的失配电流可以被放大到一个大的输出电压摆幅。此外,每比特的面积开销只有两个最小尺寸的NMOS晶体管:一个用于电流反射镜的负载,另一个用于选择开关。此外,我们采用UMC 65nm CMOS技术进行了广泛的布局后仿真,验证了所提出的PUF设计,每比特功耗低至0.13μW。从设计布局中提取的每个响应位的平均面积为5.47μm2。
{"title":"A low power and compact physical unclonable function based on the cascode current mirrors","authors":"Shibang Lin, Dejian Liang, Yuan Cao, Xiaofang Pan, Xiaojin Zhao","doi":"10.1109/APCCAS.2016.7803913","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803913","url":null,"abstract":"In this paper, we present a novel on-chip physical unclonable function (PUF) based on the cascode current mirrors. It exploits the process variation of a single transistor as the load of the current mirror to generate a reliable digital signature for the chip. By employing a cascode NMOS transistor in the current-mode PUF architecture, the proposed PUF greatly boosts the output impedance. As a result, the tiny mismatch current can be amplified to a large output voltage swing. In addition, the area overhead per bit is only two minimum-sized NMOS transistors: one for the load of the current mirror, the other one for the selecting switch. Moreover, the proposed PUF design is validated by our extensive post-layout simulation using UMC 65nm CMOS technology, with a power consumption per bit as low as 0.13μW. The average area for each response bit extracted from the design layout is 5.47μm2.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81358811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FPGA implementation of hamming code for increasing the frame rate of CAN communication 用FPGA实现汉明码,提高CAN通信的帧率
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804065
Ronnie Opone Serfa Juan, Min-Woo Jeong, Hyeong-Woo Cha, Hi-Seok Kim
Controller Area Network (CAN) protocol utilizes Cyclic Redundancy Check (CRC) code as a self-correcting method to detect and correct errors. The main objective of this algorithm is to use an alternative error correction scheme which is called as the Hamming code, replacing the conventional CRC code. Moreover, to possibly increase the CAN's frame rate of the system. The bit's positions of the redundant bits ‘r’ and the bit streams of the frames from the start-of-frame (SOF) to the control bit frames are determine. These bits will be fed into the redundant bit controller to compute for the necessary r. The redundant bit's positions are in power of 2, and will be calculated using modulo-2 operation. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results shows a significant increase of CAN's frame rate and, it minimizes the bits stuffing payload and can be a better option for detecting and correcting error in CAN System.
CAN (Controller Area Network)协议利用CRC (Cyclic Redundancy Check)码作为一种自纠错方法来检测和纠正错误。该算法的主要目的是使用一种称为汉明码的替代纠错方案来取代传统的CRC码。此外,尽可能提高系统的CAN帧率。确定冗余位' r '的位的位置以及从帧开始(SOF)到控制位帧的帧的位流。这些位将被送入冗余位控制器以计算所需的r。冗余位的位置是2的幂次,并将使用模-2运算进行计算。该方法是在Xilinx Virtex-5 FPGA上合成的。仿真结果表明,该方法显著提高了CAN的帧速率,减小了比特填充负载,是CAN系统中检测和纠错的一种较好的选择。
{"title":"FPGA implementation of hamming code for increasing the frame rate of CAN communication","authors":"Ronnie Opone Serfa Juan, Min-Woo Jeong, Hyeong-Woo Cha, Hi-Seok Kim","doi":"10.1109/APCCAS.2016.7804065","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804065","url":null,"abstract":"Controller Area Network (CAN) protocol utilizes Cyclic Redundancy Check (CRC) code as a self-correcting method to detect and correct errors. The main objective of this algorithm is to use an alternative error correction scheme which is called as the Hamming code, replacing the conventional CRC code. Moreover, to possibly increase the CAN's frame rate of the system. The bit's positions of the redundant bits ‘r’ and the bit streams of the frames from the start-of-frame (SOF) to the control bit frames are determine. These bits will be fed into the redundant bit controller to compute for the necessary r. The redundant bit's positions are in power of 2, and will be calculated using modulo-2 operation. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results shows a significant increase of CAN's frame rate and, it minimizes the bits stuffing payload and can be a better option for detecting and correcting error in CAN System.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76966036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Effect of traffic generation patterns on traffic performance of complex networks 流量生成方式对复杂网络流量性能的影响
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803896
Junwen Zeng, Jiajing Wu, Zhenhao Chen, Zibin Zheng
In this paper, we study the effect of traffic generation patterns on traffic performance of complex networks. We consider a generic type of networks consisting of two kinds of nodes: hosts and routers. In this kind of network, the traffic performance is closely related to the traffic generation pattern which is determined by the hosts' locations. We evaluate the performance of six kinds of methods to locate the hosts in Erdos-Renyi (ER) random network, Barabasi-Albert (BA) scale-free network and the Internet AS-level network. Our simulation results show that the traffic generation pattern has a significant effect on the traffic performance and provide insights into network design.
本文研究了复杂网络中流量生成方式对流量性能的影响。我们考虑由两种节点组成的一般类型的网络:主机和路由器。在这种网络中,流量性能与主机位置决定的流量生成模式密切相关。本文对Erdos-Renyi (ER)随机网络、Barabasi-Albert (BA)无标度网络和Internet as级网络中6种主机定位方法的性能进行了评价。我们的模拟结果表明,流量生成模式对流量性能有显著影响,并为网络设计提供了见解。
{"title":"Effect of traffic generation patterns on traffic performance of complex networks","authors":"Junwen Zeng, Jiajing Wu, Zhenhao Chen, Zibin Zheng","doi":"10.1109/APCCAS.2016.7803896","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803896","url":null,"abstract":"In this paper, we study the effect of traffic generation patterns on traffic performance of complex networks. We consider a generic type of networks consisting of two kinds of nodes: hosts and routers. In this kind of network, the traffic performance is closely related to the traffic generation pattern which is determined by the hosts' locations. We evaluate the performance of six kinds of methods to locate the hosts in Erdos-Renyi (ER) random network, Barabasi-Albert (BA) scale-free network and the Internet AS-level network. Our simulation results show that the traffic generation pattern has a significant effect on the traffic performance and provide insights into network design.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75741515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An accurate design approach for two-stage CMOS operational amplifiers 两级CMOS运算放大器的精确设计方法
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804049
Yushun Guo
This paper presents an accurate design approach for two-stage CMOS operational amplifiers developed based on the usual design procedure. It eliminates the errors existed in design results by employing the accurate MOS model and carrying out the design procedure iteratively. The specifications of the amplifier designed by this approach match exactly with the user specified values. A design example in 0.18μm CMOS technology is given to illustrate the effectiveness of the proposed design approach.
本文在常规设计程序的基础上,提出了一种两级CMOS运算放大器的精确设计方法。采用精确的MOS模型,迭代地执行设计过程,消除了设计结果中存在的误差。用这种方法设计的放大器的规格与用户指定的值完全匹配。最后以0.18μm CMOS工艺为例,验证了该设计方法的有效性。
{"title":"An accurate design approach for two-stage CMOS operational amplifiers","authors":"Yushun Guo","doi":"10.1109/APCCAS.2016.7804049","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804049","url":null,"abstract":"This paper presents an accurate design approach for two-stage CMOS operational amplifiers developed based on the usual design procedure. It eliminates the errors existed in design results by employing the accurate MOS model and carrying out the design procedure iteratively. The specifications of the amplifier designed by this approach match exactly with the user specified values. A design example in 0.18μm CMOS technology is given to illustrate the effectiveness of the proposed design approach.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83347151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A high background light subtraction circuit for long range time-of-flight cameras 一种用于远距离飞行时间照相机的高背景光减法电路
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804010
C. Anand, K. Jainwal, M. Sarkar
In this paper, a background light subtraction circuit is presented for a long range time-of-flight camera in outdoor applications. A low (de)modulation frequency is used for long range estimation, which saturates the photodiode due to integration of high-intensity background light. Therefore, long range cameras are generally limited to indoor applications. In this work, a circuit is proposed to subtract up to 120 klx BGL for 1.07–9.65 m distance. A (de)modulation frequency of 2.33 MHz with 33 % duty-cycle is used. The measurement results show a range resolution of 1.49 cm and 65 cm for 1.07 m and 9.65 m distance, respectively at 120 klx background light. The circuit is fabricated and characterized in UMC 180 nm technology.
本文提出了一种用于户外远程飞行时间相机的背景光减法电路。低(解)调制频率用于远距离估计,由于高强度背景光的集成,使光电二极管饱和。因此,远程摄像机通常仅限于室内应用。在这项工作中,提出了一种电路,在1.07-9.65 m距离上减去高达120 klx的BGL。调制频率为2.33 MHz,占空比为33%。测量结果表明,在120 klx背景光下,在1.07 m和9.65 m距离上,距离分辨率分别为1.49 cm和65 cm。该电路采用UMC 180nm工艺制备并表征。
{"title":"A high background light subtraction circuit for long range time-of-flight cameras","authors":"C. Anand, K. Jainwal, M. Sarkar","doi":"10.1109/APCCAS.2016.7804010","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804010","url":null,"abstract":"In this paper, a background light subtraction circuit is presented for a long range time-of-flight camera in outdoor applications. A low (de)modulation frequency is used for long range estimation, which saturates the photodiode due to integration of high-intensity background light. Therefore, long range cameras are generally limited to indoor applications. In this work, a circuit is proposed to subtract up to 120 klx BGL for 1.07–9.65 m distance. A (de)modulation frequency of 2.33 MHz with 33 % duty-cycle is used. The measurement results show a range resolution of 1.49 cm and 65 cm for 1.07 m and 9.65 m distance, respectively at 120 klx background light. The circuit is fabricated and characterized in UMC 180 nm technology.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83938752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On-glass operational amplifier using solution-processed a-IGZO TFTs 使用溶液处理的a-IGZO tft的玻璃上运算放大器
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804027
Daejung Kim, Keun-Yeong Choi, Hojin Lee
In this paper, we presented a novel operational amplifier (op-amp) only with solution-processed n-type amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The a-IGZO TFTs and common-source amplifier were fabricated on glass substrate through the solution process and confirmed to show stable electrical characteristics suitable for display driving circuits. Based on the experimental results, we designed an op-amp to have an overall gain of 30.5 dB, a cut-off frequency of 1.47 kHz, and a unit gain frequency of 6.65 kHz when supply voltage was ±15 V. Finally, by constituting the comparator, the proposed op-amp is expected to be used in power control and driving systems for display applications.
在本文中,我们提出了一种仅使用溶液处理的n型非晶铟镓锌氧化物(a- igzo)薄膜晶体管(TFTs)的新型运算放大器(运放)。采用溶液法在玻璃基板上制备了a-IGZO tft和共源放大器,并证实其具有稳定的电气特性,适合于显示驱动电路。根据实验结果,我们设计了一个在电源电压为±15 V时,总增益为30.5 dB,截止频率为1.47 kHz,单位增益频率为6.65 kHz的运放。最后,通过构成比较器,所提出的运算放大器有望用于显示应用的功率控制和驱动系统。
{"title":"On-glass operational amplifier using solution-processed a-IGZO TFTs","authors":"Daejung Kim, Keun-Yeong Choi, Hojin Lee","doi":"10.1109/APCCAS.2016.7804027","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804027","url":null,"abstract":"In this paper, we presented a novel operational amplifier (op-amp) only with solution-processed n-type amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The a-IGZO TFTs and common-source amplifier were fabricated on glass substrate through the solution process and confirmed to show stable electrical characteristics suitable for display driving circuits. Based on the experimental results, we designed an op-amp to have an overall gain of 30.5 dB, a cut-off frequency of 1.47 kHz, and a unit gain frequency of 6.65 kHz when supply voltage was ±15 V. Finally, by constituting the comparator, the proposed op-amp is expected to be used in power control and driving systems for display applications.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85061831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Live demonstration: Signal flow platform implementation into retinal cell pathway 现场演示:视网膜细胞通路信号流平台的实现
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804033
Seungbum Baek, J. Eshraghian, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, H. Iu, T. Fernando, K. Eshraghian
This live demonstration implements an established signal flow platform with its foundation derived from a system of nonlinear integral equations in a MATLAB simulation environment, characterizing the functional behavior of the signal that traverses from the photoreceptor to the ganglion cell in the vision processing architecture. While an increase in computational speed over the conventional method of solving a system of nonlinear ordinary differential equations (ODEs) has been confirmed for a single ganglion cell, the notion is extended to a retinal dual-pathway simulation which provides for a significantly improved adoption for organic mechanisms. There are various numerical methods in solving such a system which all have a bearing on both speed and error, and as such, systematic analyses using two common forms of integral solving methods are shown to improve the overall performance of simulating the extended pathway of the retinal model.
本演示在MATLAB仿真环境中实现了一个已建立的信号流平台,该平台的基础来源于一个非线性积分方程系统,表征了视觉处理架构中信号从光感受器到神经节细胞的功能行为。虽然对于单个神经节细胞,求解非线性常微分方程(ode)系统的传统方法的计算速度有所提高,但该概念已扩展到视网膜双通路模拟,从而显着改善了对有机机制的采用。求解这类系统有多种数值方法,它们都对速度和误差有影响,因此,使用两种常见形式的积分求解方法进行系统分析,可以提高模拟视网膜模型扩展路径的整体性能。
{"title":"Live demonstration: Signal flow platform implementation into retinal cell pathway","authors":"Seungbum Baek, J. Eshraghian, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, H. Iu, T. Fernando, K. Eshraghian","doi":"10.1109/APCCAS.2016.7804033","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804033","url":null,"abstract":"This live demonstration implements an established signal flow platform with its foundation derived from a system of nonlinear integral equations in a MATLAB simulation environment, characterizing the functional behavior of the signal that traverses from the photoreceptor to the ganglion cell in the vision processing architecture. While an increase in computational speed over the conventional method of solving a system of nonlinear ordinary differential equations (ODEs) has been confirmed for a single ganglion cell, the notion is extended to a retinal dual-pathway simulation which provides for a significantly improved adoption for organic mechanisms. There are various numerical methods in solving such a system which all have a bearing on both speed and error, and as such, systematic analyses using two common forms of integral solving methods are shown to improve the overall performance of simulating the extended pathway of the retinal model.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82390570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of non-ideal effects and electrochemical impedance spectroscopy of arrayed flexible NiO-based pH sensor 阵列柔性镍基pH传感器的非理想效应及电化学阻抗谱分析
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804086
Siao-Jie Yan, J. Chou, Yi-Hung Liao, Chih-Hsien Lai, Jian-Syun Chen, Bo-Yang Zhuang, Hsiang-Yi Chen, Ting-Wei Tseng
In this study, nickel oxide (NiO) was used as sensing film of arrayed flexible NiO-based pH sensor, which could reach high sensitivity (63.376 mV/pH) by potentiometric measurement system. Non-ideal effects of the sensor, such as drift and hysteresis effects, were investigated. Drift rate in pH 7 was 3.436 mV/hr, and hysteresis voltages in loops of pH 7 → pH 3 → pH 7 → pH 11 → pH 7 and pH 7 → pH 11 → pH 7 → pH 3 → pH 7 were respectively 4.496 mV and 1.817 mV. Moreover, sensing mechanism was characterized by electrochemical impedance spectroscopy.
本研究以氧化镍(NiO)为传感膜制备了阵列柔性NiO基pH传感器,该传感器通过电位测量系统可达到63.376 mV/pH的高灵敏度。研究了传感器的非理想效应,如漂移效应和滞后效应。pH 7的漂移速率为3.436 mV/hr, pH 7→pH 3→pH 7→pH 11→pH 7和pH 7→pH 11→pH 7→pH 3→pH 7回路的滞后电压分别为4.496 mV和1.817 mV。利用电化学阻抗谱对传感机理进行了表征。
{"title":"Analysis of non-ideal effects and electrochemical impedance spectroscopy of arrayed flexible NiO-based pH sensor","authors":"Siao-Jie Yan, J. Chou, Yi-Hung Liao, Chih-Hsien Lai, Jian-Syun Chen, Bo-Yang Zhuang, Hsiang-Yi Chen, Ting-Wei Tseng","doi":"10.1109/APCCAS.2016.7804086","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804086","url":null,"abstract":"In this study, nickel oxide (NiO) was used as sensing film of arrayed flexible NiO-based pH sensor, which could reach high sensitivity (63.376 mV/pH) by potentiometric measurement system. Non-ideal effects of the sensor, such as drift and hysteresis effects, were investigated. Drift rate in pH 7 was 3.436 mV/hr, and hysteresis voltages in loops of pH 7 → pH 3 → pH 7 → pH 11 → pH 7 and pH 7 → pH 11 → pH 7 → pH 3 → pH 7 were respectively 4.496 mV and 1.817 mV. Moreover, sensing mechanism was characterized by electrochemical impedance spectroscopy.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72579122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Machine learning (ML)-based lithography optimizations 基于机器学习(ML)的光刻优化
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804021
Seongbo Shim, Suhyeong Choi, Youngsoo Shin
Recent lithography optimizations demand higher accuracy and cause longer runtime. Optical proximity correction (OPC) and sub-resolution assist feature (SRAF) insertion, for example, take a few days due to lengthy lithography simulations and high pattern density. Etch proximity correction (EPC) is another example of intensive optimization due to a complex physical model of etching process. Machine learning has recently been applied to these lithography optimizations with some success. In this paper, we introduce basic algorithms of machine learning technique, e.g. support vector machine (SVM) and neural networks, and how they are applied to lithography optimization problems. Discussion on learning parameters, preparation of compact learning data set, technique to avoid over-fitting are also provided.
最近的光刻优化要求更高的精度,并导致更长的运行时间。例如,光学接近校正(OPC)和亚分辨率辅助特征(SRAF)插入需要几天时间,因为光刻模拟时间长,图案密度高。由于蚀刻过程的物理模型复杂,蚀刻邻近校正(EPC)是强化优化的另一个例子。机器学习最近被应用于这些光刻优化,并取得了一些成功。本文介绍了机器学习技术的基本算法,如支持向量机(SVM)和神经网络,以及它们如何应用于光刻优化问题。讨论了学习参数、紧凑学习数据集的制备以及避免过拟合的方法。
{"title":"Machine learning (ML)-based lithography optimizations","authors":"Seongbo Shim, Suhyeong Choi, Youngsoo Shin","doi":"10.1109/APCCAS.2016.7804021","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804021","url":null,"abstract":"Recent lithography optimizations demand higher accuracy and cause longer runtime. Optical proximity correction (OPC) and sub-resolution assist feature (SRAF) insertion, for example, take a few days due to lengthy lithography simulations and high pattern density. Etch proximity correction (EPC) is another example of intensive optimization due to a complex physical model of etching process. Machine learning has recently been applied to these lithography optimizations with some success. In this paper, we introduce basic algorithms of machine learning technique, e.g. support vector machine (SVM) and neural networks, and how they are applied to lithography optimization problems. Discussion on learning parameters, preparation of compact learning data set, technique to avoid over-fitting are also provided.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77070234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design of a low-complexity O-QPSK transceiver with spatial modulation for internet-of-things applications 面向物联网应用的空间调制低复杂度O-QPSK收发器设计
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803955
Ching-Hoa Yang, P. Tsai
In this paper, we propose an O-QPSK transceiver with five modes including 2×2 spatial-modulation mode to offer different data rates for supporting diverse internet-of-things (IoT) applications. Synchronization, channel estimation and joint ML detection for spatial modulation at the receiver are presented. To accomplish a low-complexity design, we use ℓ1-norm instead of ℓ2-norm, share the intermediate computation results, and exploit the property of the pulse-shaping-window coefficients for the joint Ml detection. Almost 78.8% reduction in computational complexity is achieved with only 0.2dB performance loss. The simulation results show that the low-complexity transceiver works well in the low-SNR region with low-rate modes and also supports up to 3Mbps with the spatial modulation.
在本文中,我们提出了一种O-QPSK收发器,具有五种模式,包括2×2空间调制模式,以提供不同的数据速率,以支持各种物联网(IoT)应用。提出了接收机空间调制的同步、信道估计和联合ML检测。为了实现低复杂度的设计,我们使用1-范数代替2-范数,共享中间计算结果,并利用脉冲形窗系数的特性进行联合Ml检测。在仅损失0.2dB性能的情况下,计算复杂度降低了78.8%。仿真结果表明,该低复杂度收发器在低信噪比区域和低速率模式下工作良好,在空间调制下可支持高达3Mbps的带宽。
{"title":"Design of a low-complexity O-QPSK transceiver with spatial modulation for internet-of-things applications","authors":"Ching-Hoa Yang, P. Tsai","doi":"10.1109/APCCAS.2016.7803955","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803955","url":null,"abstract":"In this paper, we propose an O-QPSK transceiver with five modes including 2×2 spatial-modulation mode to offer different data rates for supporting diverse internet-of-things (IoT) applications. Synchronization, channel estimation and joint ML detection for spatial modulation at the receiver are presented. To accomplish a low-complexity design, we use ℓ1-norm instead of ℓ2-norm, share the intermediate computation results, and exploit the property of the pulse-shaping-window coefficients for the joint Ml detection. Almost 78.8% reduction in computational complexity is achieved with only 0.2dB performance loss. The simulation results show that the low-complexity transceiver works well in the low-SNR region with low-rate modes and also supports up to 3Mbps with the spatial modulation.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78317910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
期刊
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
全部 Acc. Chem. Res. ACS Applied Bio Materials ACS Appl. Electron. Mater. ACS Appl. Energy Mater. ACS Appl. Mater. Interfaces ACS Appl. Nano Mater. ACS Appl. Polym. Mater. ACS BIOMATER-SCI ENG ACS Catal. ACS Cent. Sci. ACS Chem. Biol. ACS Chemical Health & Safety ACS Chem. Neurosci. ACS Comb. Sci. ACS Earth Space Chem. ACS Energy Lett. ACS Infect. Dis. ACS Macro Lett. ACS Mater. Lett. ACS Med. Chem. Lett. ACS Nano ACS Omega ACS Photonics ACS Sens. ACS Sustainable Chem. Eng. ACS Synth. Biol. Anal. Chem. BIOCHEMISTRY-US Bioconjugate Chem. BIOMACROMOLECULES Chem. Res. Toxicol. Chem. Rev. Chem. Mater. CRYST GROWTH DES ENERG FUEL Environ. Sci. Technol. Environ. Sci. Technol. Lett. Eur. J. Inorg. Chem. IND ENG CHEM RES Inorg. Chem. J. Agric. Food. Chem. J. Chem. Eng. Data J. Chem. Educ. J. Chem. Inf. Model. J. Chem. Theory Comput. J. Med. Chem. J. Nat. Prod. J PROTEOME RES J. Am. Chem. Soc. LANGMUIR MACROMOLECULES Mol. Pharmaceutics Nano Lett. Org. Lett. ORG PROCESS RES DEV ORGANOMETALLICS J. Org. Chem. J. Phys. Chem. J. Phys. Chem. A J. Phys. Chem. B J. Phys. Chem. C J. Phys. Chem. Lett. Analyst Anal. Methods Biomater. Sci. Catal. Sci. Technol. Chem. Commun. Chem. Soc. Rev. CHEM EDUC RES PRACT CRYSTENGCOMM Dalton Trans. Energy Environ. Sci. ENVIRON SCI-NANO ENVIRON SCI-PROC IMP ENVIRON SCI-WAT RES Faraday Discuss. Food Funct. Green Chem. Inorg. Chem. Front. Integr. Biol. J. Anal. At. Spectrom. J. Mater. Chem. A J. Mater. Chem. B J. Mater. Chem. C Lab Chip Mater. Chem. Front. Mater. Horiz. MEDCHEMCOMM Metallomics Mol. Biosyst. Mol. Syst. Des. Eng. Nanoscale Nanoscale Horiz. Nat. Prod. Rep. New J. Chem. Org. Biomol. Chem. Org. Chem. Front. PHOTOCH PHOTOBIO SCI PCCP Polym. Chem.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1