In this paper, we present a novel on-chip physical unclonable function (PUF) based on the cascode current mirrors. It exploits the process variation of a single transistor as the load of the current mirror to generate a reliable digital signature for the chip. By employing a cascode NMOS transistor in the current-mode PUF architecture, the proposed PUF greatly boosts the output impedance. As a result, the tiny mismatch current can be amplified to a large output voltage swing. In addition, the area overhead per bit is only two minimum-sized NMOS transistors: one for the load of the current mirror, the other one for the selecting switch. Moreover, the proposed PUF design is validated by our extensive post-layout simulation using UMC 65nm CMOS technology, with a power consumption per bit as low as 0.13μW. The average area for each response bit extracted from the design layout is 5.47μm2.
{"title":"A low power and compact physical unclonable function based on the cascode current mirrors","authors":"Shibang Lin, Dejian Liang, Yuan Cao, Xiaofang Pan, Xiaojin Zhao","doi":"10.1109/APCCAS.2016.7803913","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803913","url":null,"abstract":"In this paper, we present a novel on-chip physical unclonable function (PUF) based on the cascode current mirrors. It exploits the process variation of a single transistor as the load of the current mirror to generate a reliable digital signature for the chip. By employing a cascode NMOS transistor in the current-mode PUF architecture, the proposed PUF greatly boosts the output impedance. As a result, the tiny mismatch current can be amplified to a large output voltage swing. In addition, the area overhead per bit is only two minimum-sized NMOS transistors: one for the load of the current mirror, the other one for the selecting switch. Moreover, the proposed PUF design is validated by our extensive post-layout simulation using UMC 65nm CMOS technology, with a power consumption per bit as low as 0.13μW. The average area for each response bit extracted from the design layout is 5.47μm2.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 1","pages":"127-130"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81358811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804065
Ronnie Opone Serfa Juan, Min-Woo Jeong, Hyeong-Woo Cha, Hi-Seok Kim
Controller Area Network (CAN) protocol utilizes Cyclic Redundancy Check (CRC) code as a self-correcting method to detect and correct errors. The main objective of this algorithm is to use an alternative error correction scheme which is called as the Hamming code, replacing the conventional CRC code. Moreover, to possibly increase the CAN's frame rate of the system. The bit's positions of the redundant bits ‘r’ and the bit streams of the frames from the start-of-frame (SOF) to the control bit frames are determine. These bits will be fed into the redundant bit controller to compute for the necessary r. The redundant bit's positions are in power of 2, and will be calculated using modulo-2 operation. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results shows a significant increase of CAN's frame rate and, it minimizes the bits stuffing payload and can be a better option for detecting and correcting error in CAN System.
CAN (Controller Area Network)协议利用CRC (Cyclic Redundancy Check)码作为一种自纠错方法来检测和纠正错误。该算法的主要目的是使用一种称为汉明码的替代纠错方案来取代传统的CRC码。此外，尽可能提高系统的CAN帧率。确定冗余位' r '的位的位置以及从帧开始(SOF)到控制位帧的帧的位流。这些位将被送入冗余位控制器以计算所需的r。冗余位的位置是2的幂次，并将使用模-2运算进行计算。该方法是在Xilinx Virtex-5 FPGA上合成的。仿真结果表明，该方法显著提高了CAN的帧速率，减小了比特填充负载，是CAN系统中检测和纠错的一种较好的选择。
{"title":"FPGA implementation of hamming code for increasing the frame rate of CAN communication","authors":"Ronnie Opone Serfa Juan, Min-Woo Jeong, Hyeong-Woo Cha, Hi-Seok Kim","doi":"10.1109/APCCAS.2016.7804065","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804065","url":null,"abstract":"Controller Area Network (CAN) protocol utilizes Cyclic Redundancy Check (CRC) code as a self-correcting method to detect and correct errors. The main objective of this algorithm is to use an alternative error correction scheme which is called as the Hamming code, replacing the conventional CRC code. Moreover, to possibly increase the CAN's frame rate of the system. The bit's positions of the redundant bits ‘r’ and the bit streams of the frames from the start-of-frame (SOF) to the control bit frames are determine. These bits will be fed into the redundant bit controller to compute for the necessary r. The redundant bit's positions are in power of 2, and will be calculated using modulo-2 operation. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results shows a significant increase of CAN's frame rate and, it minimizes the bits stuffing payload and can be a better option for detecting and correcting error in CAN System.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"246 1","pages":"684-687"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76966036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we study the effect of traffic generation patterns on traffic performance of complex networks. We consider a generic type of networks consisting of two kinds of nodes: hosts and routers. In this kind of network, the traffic performance is closely related to the traffic generation pattern which is determined by the hosts' locations. We evaluate the performance of six kinds of methods to locate the hosts in Erdos-Renyi (ER) random network, Barabasi-Albert (BA) scale-free network and the Internet AS-level network. Our simulation results show that the traffic generation pattern has a significant effect on the traffic performance and provide insights into network design.
{"title":"Effect of traffic generation patterns on traffic performance of complex networks","authors":"Junwen Zeng, Jiajing Wu, Zhenhao Chen, Zibin Zheng","doi":"10.1109/APCCAS.2016.7803896","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803896","url":null,"abstract":"In this paper, we study the effect of traffic generation patterns on traffic performance of complex networks. We consider a generic type of networks consisting of two kinds of nodes: hosts and routers. In this kind of network, the traffic performance is closely related to the traffic generation pattern which is determined by the hosts' locations. We evaluate the performance of six kinds of methods to locate the hosts in Erdos-Renyi (ER) random network, Barabasi-Albert (BA) scale-free network and the Internet AS-level network. Our simulation results show that the traffic generation pattern has a significant effect on the traffic performance and provide insights into network design.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"118 1","pages":"61-64"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75741515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804049
Yushun Guo
This paper presents an accurate design approach for two-stage CMOS operational amplifiers developed based on the usual design procedure. It eliminates the errors existed in design results by employing the accurate MOS model and carrying out the design procedure iteratively. The specifications of the amplifier designed by this approach match exactly with the user specified values. A design example in 0.18μm CMOS technology is given to illustrate the effectiveness of the proposed design approach.
{"title":"An accurate design approach for two-stage CMOS operational amplifiers","authors":"Yushun Guo","doi":"10.1109/APCCAS.2016.7804049","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804049","url":null,"abstract":"This paper presents an accurate design approach for two-stage CMOS operational amplifiers developed based on the usual design procedure. It eliminates the errors existed in design results by employing the accurate MOS model and carrying out the design procedure iteratively. The specifications of the amplifier designed by this approach match exactly with the user specified values. A design example in 0.18μm CMOS technology is given to illustrate the effectiveness of the proposed design approach.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"18 1","pages":"563-566"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83347151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804010
C. Anand, K. Jainwal, M. Sarkar
In this paper, a background light subtraction circuit is presented for a long range time-of-flight camera in outdoor applications. A low (de)modulation frequency is used for long range estimation, which saturates the photodiode due to integration of high-intensity background light. Therefore, long range cameras are generally limited to indoor applications. In this work, a circuit is proposed to subtract up to 120 klx BGL for 1.07–9.65 m distance. A (de)modulation frequency of 2.33 MHz with 33 % duty-cycle is used. The measurement results show a range resolution of 1.49 cm and 65 cm for 1.07 m and 9.65 m distance, respectively at 120 klx background light. The circuit is fabricated and characterized in UMC 180 nm technology.
{"title":"A high background light subtraction circuit for long range time-of-flight cameras","authors":"C. Anand, K. Jainwal, M. Sarkar","doi":"10.1109/APCCAS.2016.7804010","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804010","url":null,"abstract":"In this paper, a background light subtraction circuit is presented for a long range time-of-flight camera in outdoor applications. A low (de)modulation frequency is used for long range estimation, which saturates the photodiode due to integration of high-intensity background light. Therefore, long range cameras are generally limited to indoor applications. In this work, a circuit is proposed to subtract up to 120 klx BGL for 1.07–9.65 m distance. A (de)modulation frequency of 2.33 MHz with 33 % duty-cycle is used. The measurement results show a range resolution of 1.49 cm and 65 cm for 1.07 m and 9.65 m distance, respectively at 120 klx background light. The circuit is fabricated and characterized in UMC 180 nm technology.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"125 1","pages":"487-490"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83938752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804027
Daejung Kim, Keun-Yeong Choi, Hojin Lee
In this paper, we presented a novel operational amplifier (op-amp) only with solution-processed n-type amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The a-IGZO TFTs and common-source amplifier were fabricated on glass substrate through the solution process and confirmed to show stable electrical characteristics suitable for display driving circuits. Based on the experimental results, we designed an op-amp to have an overall gain of 30.5 dB, a cut-off frequency of 1.47 kHz, and a unit gain frequency of 6.65 kHz when supply voltage was ±15 V. Finally, by constituting the comparator, the proposed op-amp is expected to be used in power control and driving systems for display applications.
{"title":"On-glass operational amplifier using solution-processed a-IGZO TFTs","authors":"Daejung Kim, Keun-Yeong Choi, Hojin Lee","doi":"10.1109/APCCAS.2016.7804027","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804027","url":null,"abstract":"In this paper, we presented a novel operational amplifier (op-amp) only with solution-processed n-type amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The a-IGZO TFTs and common-source amplifier were fabricated on glass substrate through the solution process and confirmed to show stable electrical characteristics suitable for display driving circuits. Based on the experimental results, we designed an op-amp to have an overall gain of 30.5 dB, a cut-off frequency of 1.47 kHz, and a unit gain frequency of 6.65 kHz when supply voltage was ±15 V. Finally, by constituting the comparator, the proposed op-amp is expected to be used in power control and driving systems for display applications.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"C-19 1","pages":"551-553"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85061831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804033
Seungbum Baek, J. Eshraghian, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, H. Iu, T. Fernando, K. Eshraghian
This live demonstration implements an established signal flow platform with its foundation derived from a system of nonlinear integral equations in a MATLAB simulation environment, characterizing the functional behavior of the signal that traverses from the photoreceptor to the ganglion cell in the vision processing architecture. While an increase in computational speed over the conventional method of solving a system of nonlinear ordinary differential equations (ODEs) has been confirmed for a single ganglion cell, the notion is extended to a retinal dual-pathway simulation which provides for a significantly improved adoption for organic mechanisms. There are various numerical methods in solving such a system which all have a bearing on both speed and error, and as such, systematic analyses using two common forms of integral solving methods are shown to improve the overall performance of simulating the extended pathway of the retinal model.
{"title":"Live demonstration: Signal flow platform implementation into retinal cell pathway","authors":"Seungbum Baek, J. Eshraghian, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, H. Iu, T. Fernando, K. Eshraghian","doi":"10.1109/APCCAS.2016.7804033","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804033","url":null,"abstract":"This live demonstration implements an established signal flow platform with its foundation derived from a system of nonlinear integral equations in a MATLAB simulation environment, characterizing the functional behavior of the signal that traverses from the photoreceptor to the ganglion cell in the vision processing architecture. While an increase in computational speed over the conventional method of solving a system of nonlinear ordinary differential equations (ODEs) has been confirmed for a single ganglion cell, the notion is extended to a retinal dual-pathway simulation which provides for a significantly improved adoption for organic mechanisms. There are various numerical methods in solving such a system which all have a bearing on both speed and error, and as such, systematic analyses using two common forms of integral solving methods are shown to improve the overall performance of simulating the extended pathway of the retinal model.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"4 1","pages":"740-741"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82390570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, nickel oxide (NiO) was used as sensing film of arrayed flexible NiO-based pH sensor, which could reach high sensitivity (63.376 mV/pH) by potentiometric measurement system. Non-ideal effects of the sensor, such as drift and hysteresis effects, were investigated. Drift rate in pH 7 was 3.436 mV/hr, and hysteresis voltages in loops of pH 7 → pH 3 → pH 7 → pH 11 → pH 7 and pH 7 → pH 11 → pH 7 → pH 3 → pH 7 were respectively 4.496 mV and 1.817 mV. Moreover, sensing mechanism was characterized by electrochemical impedance spectroscopy.
{"title":"Analysis of non-ideal effects and electrochemical impedance spectroscopy of arrayed flexible NiO-based pH sensor","authors":"Siao-Jie Yan, J. Chou, Yi-Hung Liao, Chih-Hsien Lai, Jian-Syun Chen, Bo-Yang Zhuang, Hsiang-Yi Chen, Ting-Wei Tseng","doi":"10.1109/APCCAS.2016.7804086","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804086","url":null,"abstract":"In this study, nickel oxide (NiO) was used as sensing film of arrayed flexible NiO-based pH sensor, which could reach high sensitivity (63.376 mV/pH) by potentiometric measurement system. Non-ideal effects of the sensor, such as drift and hysteresis effects, were investigated. Drift rate in pH 7 was 3.436 mV/hr, and hysteresis voltages in loops of pH 7 → pH 3 → pH 7 → pH 11 → pH 7 and pH 7 → pH 11 → pH 7 → pH 3 → pH 7 were respectively 4.496 mV and 1.817 mV. Moreover, sensing mechanism was characterized by electrochemical impedance spectroscopy.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"23 1","pages":"670-673"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72579122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804021
Seongbo Shim, Suhyeong Choi, Youngsoo Shin
Recent lithography optimizations demand higher accuracy and cause longer runtime. Optical proximity correction (OPC) and sub-resolution assist feature (SRAF) insertion, for example, take a few days due to lengthy lithography simulations and high pattern density. Etch proximity correction (EPC) is another example of intensive optimization due to a complex physical model of etching process. Machine learning has recently been applied to these lithography optimizations with some success. In this paper, we introduce basic algorithms of machine learning technique, e.g. support vector machine (SVM) and neural networks, and how they are applied to lithography optimization problems. Discussion on learning parameters, preparation of compact learning data set, technique to avoid over-fitting are also provided.
{"title":"Machine learning (ML)-based lithography optimizations","authors":"Seongbo Shim, Suhyeong Choi, Youngsoo Shin","doi":"10.1109/APCCAS.2016.7804021","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804021","url":null,"abstract":"Recent lithography optimizations demand higher accuracy and cause longer runtime. Optical proximity correction (OPC) and sub-resolution assist feature (SRAF) insertion, for example, take a few days due to lengthy lithography simulations and high pattern density. Etch proximity correction (EPC) is another example of intensive optimization due to a complex physical model of etching process. Machine learning has recently been applied to these lithography optimizations with some success. In this paper, we introduce basic algorithms of machine learning technique, e.g. support vector machine (SVM) and neural networks, and how they are applied to lithography optimization problems. Discussion on learning parameters, preparation of compact learning data set, technique to avoid over-fitting are also provided.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"46 1","pages":"530-533"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77070234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803955
Ching-Hoa Yang, P. Tsai
In this paper, we propose an O-QPSK transceiver with five modes including 2×2 spatial-modulation mode to offer different data rates for supporting diverse internet-of-things (IoT) applications. Synchronization, channel estimation and joint ML detection for spatial modulation at the receiver are presented. To accomplish a low-complexity design, we use ℓ1-norm instead of ℓ2-norm, share the intermediate computation results, and exploit the property of the pulse-shaping-window coefficients for the joint Ml detection. Almost 78.8% reduction in computational complexity is achieved with only 0.2dB performance loss. The simulation results show that the low-complexity transceiver works well in the low-SNR region with low-rate modes and also supports up to 3Mbps with the spatial modulation.
{"title":"Design of a low-complexity O-QPSK transceiver with spatial modulation for internet-of-things applications","authors":"Ching-Hoa Yang, P. Tsai","doi":"10.1109/APCCAS.2016.7803955","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803955","url":null,"abstract":"In this paper, we propose an O-QPSK transceiver with five modes including 2×2 spatial-modulation mode to offer different data rates for supporting diverse internet-of-things (IoT) applications. Synchronization, channel estimation and joint ML detection for spatial modulation at the receiver are presented. To accomplish a low-complexity design, we use ℓ1-norm instead of ℓ2-norm, share the intermediate computation results, and exploit the property of the pulse-shaping-window coefficients for the joint Ml detection. Almost 78.8% reduction in computational complexity is achieved with only 0.2dB performance loss. The simulation results show that the low-complexity transceiver works well in the low-SNR region with low-rate modes and also supports up to 3Mbps with the spatial modulation.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"12 1","pages":"285-288"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78317910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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