Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804069
W. Ki, Lin Cheng, Chenchang Zhan
State-space averaging and perturbation analysis is systematically applied to compute the open-loop and closed-loop transfer matrices (Tol and Tcl) of switching converters working in continuous conduction mode. The power supply rejection function, input impedance and output impedance can be read off directly from Tcl. A circuit-level simulation method, the frequency-point spectrum simulation, is proposed that resembles the actual spectrum measurement procedure to verify the analytical results.
{"title":"Closed-loop transfer functions and frequency-point spectrum simulation of CCM buck converters","authors":"W. Ki, Lin Cheng, Chenchang Zhan","doi":"10.1109/APCCAS.2016.7804069","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804069","url":null,"abstract":"State-space averaging and perturbation analysis is systematically applied to compute the open-loop and closed-loop transfer matrices (Tol and Tcl) of switching converters working in continuous conduction mode. The power supply rejection function, input impedance and output impedance can be read off directly from Tcl. A circuit-level simulation method, the frequency-point spectrum simulation, is proposed that resembles the actual spectrum measurement procedure to verify the analytical results.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78918261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804013
R. Zheng, Jia Wang
In this paper, a custom-designed CMOS image sensor (CIS) is proposed with N-type and P-type pixels fabricated on one chip. A Co radiation experiment is implemented on the proposed CIS chip. Measurement results shows that the P-type pixels have good total ionizing dose (TID) radiation tolerance with less radiation induced dark current compared with N-type pixels. But the dark current nonuniformity of P-type pixels is observed to be enhanced more than N-type ones by TID radiation effect.
{"title":"Dark current analysis of P-type and N-type pixels under total ionizing dose radiation effects","authors":"R. Zheng, Jia Wang","doi":"10.1109/APCCAS.2016.7804013","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804013","url":null,"abstract":"In this paper, a custom-designed CMOS image sensor (CIS) is proposed with N-type and P-type pixels fabricated on one chip. A Co radiation experiment is implemented on the proposed CIS chip. Measurement results shows that the P-type pixels have good total ionizing dose (TID) radiation tolerance with less radiation induced dark current compared with N-type pixels. But the dark current nonuniformity of P-type pixels is observed to be enhanced more than N-type ones by TID radiation effect.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80980584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804061
M. Aung, T. T. Kim
In this paper, we propose self-contained built-in-self-test/repair (BIST/R) solutions to improve the reliability of the direct face-to-face copper thermo-compression bonding A dual-mode transceiver is presented to operate either as an ohmic mode when the bonding has low resistance or as a capacitive coupling mode when the bonding is faulty showing high resistance.
{"title":"Self-contained built-in-self-test/repair transceivers for interconnects in 3DICs","authors":"M. Aung, T. T. Kim","doi":"10.1109/APCCAS.2016.7804061","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804061","url":null,"abstract":"In this paper, we propose self-contained built-in-self-test/repair (BIST/R) solutions to improve the reliability of the direct face-to-face copper thermo-compression bonding A dual-mode transceiver is presented to operate either as an ohmic mode when the bonding has low resistance or as a capacitive coupling mode when the bonding is faulty showing high resistance.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85387318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803937
Seokha Hwang, Youngjoo Lee
This paper presents an FPGA based real-time lane detection system for automotive applications. To reduce the computational complexity, the conventional Canny-Hough lane detection algorithm is modified for achieving the real-time processing. The prototype design is realized by using the commercialized FPGA platform and the processing rate is enhanced by 41% compared to the previous detection algorithm.
{"title":"FPGA-based real-time lane detection for advanced driver assistance systems","authors":"Seokha Hwang, Youngjoo Lee","doi":"10.1109/APCCAS.2016.7803937","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803937","url":null,"abstract":"This paper presents an FPGA based real-time lane detection system for automotive applications. To reduce the computational complexity, the conventional Canny-Hough lane detection algorithm is modified for achieving the real-time processing. The prototype design is realized by using the commercialized FPGA platform and the processing rate is enhanced by 41% compared to the previous detection algorithm.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81321526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803907
K. G. Jayaraman, Karim Rawy, T. T. Kim
This paper describes a fully integrated, low voltage digital low-dropout voltage (DLDO) regulator for ultra-low power applications with a load current aware clock modulation scheme. The proposed DLDO uses a clock modulation technique that provides a fast transient response during load state transitions. The proposed clock modulation (CM) controls the clock frequency when it senses a sudden load current transition. This eliminates the tradeoff between transient time and power efficiency with a fixed clock frequency. Thus, it minimizes the transient response time and maximizes the power and current efficiency. The proposed DLDO operates at 0.6 V and generates 0.55 V output voltage. A test chip is fabricated using 65-nm CMOS technology and demonstrates the current efficiency of 99.7% with the load current from 10 μA to 200 μA with and the quiescent current of 0.9 μA.
{"title":"A 0.6-V power efficient digital LDO with 99.7% current efficiency utilizing load current aware clock modulation for fast transient response","authors":"K. G. Jayaraman, Karim Rawy, T. T. Kim","doi":"10.1109/APCCAS.2016.7803907","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803907","url":null,"abstract":"This paper describes a fully integrated, low voltage digital low-dropout voltage (DLDO) regulator for ultra-low power applications with a load current aware clock modulation scheme. The proposed DLDO uses a clock modulation technique that provides a fast transient response during load state transitions. The proposed clock modulation (CM) controls the clock frequency when it senses a sudden load current transition. This eliminates the tradeoff between transient time and power efficiency with a fixed clock frequency. Thus, it minimizes the transient response time and maximizes the power and current efficiency. The proposed DLDO operates at 0.6 V and generates 0.55 V output voltage. A test chip is fabricated using 65-nm CMOS technology and demonstrates the current efficiency of 99.7% with the load current from 10 μA to 200 μA with and the quiescent current of 0.9 μA.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81407645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803893
Shu-Min Zhang, Xiang Li
Uncovering human mobility patterns is of vital importance to the widely practical applications ranging from urban planning to epidemic controlling. Although numerous previous studies regarding human mobility patterns have been carried out to statistically characterize the dynamics of human mobility in both empirical analysis and modelling approach, research on the level of driving factors of mobility behaviors is still limited. In this paper, we focus on two types of human mobility behaviors which are Non-Spontaneous Mobility and Spontaneous Mobility, respectively. Based on the Wi-Fi access records collected from a university campus, statistical distinctions have been uncovered between these two types of mobility behaviors, where non-spontaneous mobility behaviors display a less heterogeneous but more periodic pattern with a smaller activity range, suggesting the necessity of embedding these two types of behaviors when modelling human mobility.
{"title":"Mobility patterns of human population among university campuses","authors":"Shu-Min Zhang, Xiang Li","doi":"10.1109/APCCAS.2016.7803893","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803893","url":null,"abstract":"Uncovering human mobility patterns is of vital importance to the widely practical applications ranging from urban planning to epidemic controlling. Although numerous previous studies regarding human mobility patterns have been carried out to statistically characterize the dynamics of human mobility in both empirical analysis and modelling approach, research on the level of driving factors of mobility behaviors is still limited. In this paper, we focus on two types of human mobility behaviors which are Non-Spontaneous Mobility and Spontaneous Mobility, respectively. Based on the Wi-Fi access records collected from a university campus, statistical distinctions have been uncovered between these two types of mobility behaviors, where non-spontaneous mobility behaviors display a less heterogeneous but more periodic pattern with a smaller activity range, suggesting the necessity of embedding these two types of behaviors when modelling human mobility.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82111954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803949
S. A. E. A. Rahim, A. Barakat, R. Pokharel
This paper presents the design of low noise LC oscillator that employs an enhanced inductor, where a distributed grid of N-well in P-substrate of the inductor was design to improve the quality factor of the inductor, therefore improves the phase noise of the oscillator. The electromagnetic (EM) simulation shows that the total equivalent resistance of an inductor is reduced, which results in a higher quality factor. A 5.5GHz cross-coupled CMOS LC oscillator is designed by using this new inductor. Based on the simulation results, the oscillator shows an improvement of 0.7 dBc/Hz in phase noise at 1MHz offset from the carrier, which results a FOM of 189.
{"title":"Design of 5.5GHz LC oscillator using distributed grid of N-well in P-substrate inductor","authors":"S. A. E. A. Rahim, A. Barakat, R. Pokharel","doi":"10.1109/APCCAS.2016.7803949","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803949","url":null,"abstract":"This paper presents the design of low noise LC oscillator that employs an enhanced inductor, where a distributed grid of N-well in P-substrate of the inductor was design to improve the quality factor of the inductor, therefore improves the phase noise of the oscillator. The electromagnetic (EM) simulation shows that the total equivalent resistance of an inductor is reduced, which results in a higher quality factor. A 5.5GHz cross-coupled CMOS LC oscillator is designed by using this new inductor. Based on the simulation results, the oscillator shows an improvement of 0.7 dBc/Hz in phase noise at 1MHz offset from the carrier, which results a FOM of 189.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82215170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803934
Zilong Liu, Dongsheng Liu, X. Sun, X. Zou, Hui Lin
Several hardware implementations of elliptic curve cryptography have been recently proposed for resource-constrained applications but few of them considered the power analysis countermeasures. In this paper, a new modular multiplication with zero-value attack countermeasure is proposed. The Montgomery ladder algorithm and randomized projective coordinates method are used to resist simple power analysis and differential power analysis. The circular shift register has been adopted to reduce the area. The overall design has been implemented in binary field. 16.5K Gate Equivalent (GE) area is needed and 10.8ms is required for one scalar point multiplication at 13.56MHz. The implementation result shows that the proposed ECC processor achieves power analysis resistance with low resource cost.
{"title":"Implementation of a resource-constrained ECC processor with power analysis countermeasure","authors":"Zilong Liu, Dongsheng Liu, X. Sun, X. Zou, Hui Lin","doi":"10.1109/APCCAS.2016.7803934","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803934","url":null,"abstract":"Several hardware implementations of elliptic curve cryptography have been recently proposed for resource-constrained applications but few of them considered the power analysis countermeasures. In this paper, a new modular multiplication with zero-value attack countermeasure is proposed. The Montgomery ladder algorithm and randomized projective coordinates method are used to resist simple power analysis and differential power analysis. The circular shift register has been adopted to reduce the area. The overall design has been implemented in binary field. 16.5K Gate Equivalent (GE) area is needed and 10.8ms is required for one scalar point multiplication at 13.56MHz. The implementation result shows that the proposed ECC processor achieves power analysis resistance with low resource cost.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78838870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804079
S. Pandey, P. Kondekar, K. Nigam, D. Sharma
In this paper, a high gain and wideband input match CMOS low-noise amplifier (LNA) is presented for the ultra-wide band (UWB) application. The main novelty lies in significant improvement in bandwidth by using the inverter cell at the input node, with a peaking inductor at the gate of NMOS device. Self-forward-body-bias (SFBB) concept is also used within the inverter cell to mitigate the trade-off between input matching and power consumption. In the second stage, self bias resistive feedback circuit with the drain peaking inductor is used to increase the gain as well as output matching. Using a standard 90 nm CMOS process, the proposed LNA exhibits a peak gain of 15.3 dB at 9.4 GHz, while, it consumes 13.5 mW power from a 0.9 V supply voltage. The simulation results show S11 <−10 dB from 4.6–10.6 GHz frequency, minimum noise figure (NFmin) of 1.21–4.6 dB, output return loss −32 dB1 in the frequency range of 3.1–10.6 GHz. When a two tone test is performed with a frequency spacing of 10 MHz, a highest value of third order input intercept point (IIP3) of −3 dBm is achieved. Its other significant advantages are small group delay variation (±50 ps), and gain variation of ±1.21 dB.
{"title":"A 0.9V, 3.1–10.6 GHz CMOS LNA with high gain and wideband input match in 90 nm CMOS process","authors":"S. Pandey, P. Kondekar, K. Nigam, D. Sharma","doi":"10.1109/APCCAS.2016.7804079","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804079","url":null,"abstract":"In this paper, a high gain and wideband input match CMOS low-noise amplifier (LNA) is presented for the ultra-wide band (UWB) application. The main novelty lies in significant improvement in bandwidth by using the inverter cell at the input node, with a peaking inductor at the gate of NMOS device. Self-forward-body-bias (SFBB) concept is also used within the inverter cell to mitigate the trade-off between input matching and power consumption. In the second stage, self bias resistive feedback circuit with the drain peaking inductor is used to increase the gain as well as output matching. Using a standard 90 nm CMOS process, the proposed LNA exhibits a peak gain of 15.3 dB at 9.4 GHz, while, it consumes 13.5 mW power from a 0.9 V supply voltage. The simulation results show S11 <−10 dB from 4.6–10.6 GHz frequency, minimum noise figure (NFmin) of 1.21–4.6 dB, output return loss −32 dB<S22<−10 dB and unconditional stability k>1 in the frequency range of 3.1–10.6 GHz. When a two tone test is performed with a frequency spacing of 10 MHz, a highest value of third order input intercept point (IIP3) of −3 dBm is achieved. Its other significant advantages are small group delay variation (±50 ps), and gain variation of ±1.21 dB.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82653017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803997
Muhammad Umar Karim Khan, Asim Khan, C. Kyung
Numerous depth extraction schemes cannot extract depth on textureless regions, thus generating sparse depth maps. In this paper, we propose using perception cues to improve the sparse depth map. We consider the local neighborhood as well the global surface properties of objects. We use this information to complement depth extraction schemes. The method is not scene or class specific. With quantitative evaluation, the proposed method is shown to perform better compared to previous depth refinement methods. The error in terms of standard deviation of depth has been reduced down by 60%. The computational overhead of the proposed method is also very low, making it a suitable candidate for depth refinement.
{"title":"Depth refinement on sparse-depth images using visual perception cues","authors":"Muhammad Umar Karim Khan, Asim Khan, C. Kyung","doi":"10.1109/APCCAS.2016.7803997","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803997","url":null,"abstract":"Numerous depth extraction schemes cannot extract depth on textureless regions, thus generating sparse depth maps. In this paper, we propose using perception cues to improve the sparse depth map. We consider the local neighborhood as well the global surface properties of objects. We use this information to complement depth extraction schemes. The method is not scene or class specific. With quantitative evaluation, the proposed method is shown to perform better compared to previous depth refinement methods. The error in terms of standard deviation of depth has been reduced down by 60%. The computational overhead of the proposed method is also very low, making it a suitable candidate for depth refinement.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82623221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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