Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804066
Yang Liu, Chenchang Zhan, Lidan Wang
This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.
{"title":"An ultra-low power CMOS subthreshold voltage reference without requiring resistors or BJTs","authors":"Yang Liu, Chenchang Zhan, Lidan Wang","doi":"10.1109/APCCAS.2016.7804066","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804066","url":null,"abstract":"This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"479 1","pages":"688-690"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77410192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804077
C. Jang, Sanghun Kim, Young Hwan Kim
This paper proposes the power constrained contrast enhancement algorithm for OLED display based on the multi-mapping functions for improving the local contrast of the input image. The proposed method divides the input image into several blocks. Then, it calculates the multi-mapping functions corresponding to each block using convex optimization process between the image quality and power consumption. Using the multi-mapping function, the proposed method adjusts the mapping function and calculates the output image using the bilinear interpolation. In the experimental results, the proposed method improved the local contrast, and increased the enhancement performance measure and sharpness by up to 57.8% and 41.9% compared to benchmark methods.
{"title":"Contrast enhancement using multiple mapping functions for power reduction in OLED display","authors":"C. Jang, Sanghun Kim, Young Hwan Kim","doi":"10.1109/APCCAS.2016.7804077","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804077","url":null,"abstract":"This paper proposes the power constrained contrast enhancement algorithm for OLED display based on the multi-mapping functions for improving the local contrast of the input image. The proposed method divides the input image into several blocks. Then, it calculates the multi-mapping functions corresponding to each block using convex optimization process between the image quality and power consumption. Using the multi-mapping function, the proposed method adjusts the mapping function and calculates the output image using the bilinear interpolation. In the experimental results, the proposed method improved the local contrast, and increased the enhancement performance measure and sharpness by up to 57.8% and 41.9% compared to benchmark methods.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"61 1","pages":"725-726"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77863828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803981
N. S. Ahmad, S. J. A. Bakar
Due to nonlinear behavior of several phase-detectors, linear approximation method often leads to performance degradation in many phase-controlled systems, particularly when the phase errors are sufficiently large. In this work, with the nonlinearity considered in the system's model, a suitable criterion which takes into account both the nonlinearity's sector and slope bounds is employed to establish its global stability condition. The result is then incorporated into the existing H∞ synthesis in the controller/loop filter design. The searches are expressed in terms of convex linear matrix inequalities which are computationally tractable. To illustrate the improvement introduced via this approach, several numerical examples are included with comparisons over conventional linear approximation methods.
{"title":"Phase-controlled system design via mixed H∞ synthesis and nonlinear method","authors":"N. S. Ahmad, S. J. A. Bakar","doi":"10.1109/APCCAS.2016.7803981","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803981","url":null,"abstract":"Due to nonlinear behavior of several phase-detectors, linear approximation method often leads to performance degradation in many phase-controlled systems, particularly when the phase errors are sufficiently large. In this work, with the nonlinearity considered in the system's model, a suitable criterion which takes into account both the nonlinearity's sector and slope bounds is employed to establish its global stability condition. The result is then incorporated into the existing H∞ synthesis in the controller/loop filter design. The searches are expressed in terms of convex linear matrix inequalities which are computationally tractable. To illustrate the improvement introduced via this approach, several numerical examples are included with comparisons over conventional linear approximation methods.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"19 1","pages":"380-383"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76871652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803943
K. Sooksood
This paper presents novel bulk-driven current mirror and bulk-driven cascode current mirror. Bulk-driven technique is employed to overcome a threshold voltage limitation. High accuracy transfer characteristic over wide current range is achieved through a negative feedback. The proposed circuits are designed and simulated with a 0.18 μm CMOS technology. They operate at 1 V power supply. The simulation results show the headroom voltage of 0.11 V and 0.16 V for the proposed bulk driven current mirror and bulk driven cascode current mirror, respectively.
{"title":"Wide current range and high compliance-voltage bulk-driven current mirrors: Simple and cascode","authors":"K. Sooksood","doi":"10.1109/APCCAS.2016.7803943","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803943","url":null,"abstract":"This paper presents novel bulk-driven current mirror and bulk-driven cascode current mirror. Bulk-driven technique is employed to overcome a threshold voltage limitation. High accuracy transfer characteristic over wide current range is achieved through a negative feedback. The proposed circuits are designed and simulated with a 0.18 μm CMOS technology. They operate at 1 V power supply. The simulation results show the headroom voltage of 0.11 V and 0.16 V for the proposed bulk driven current mirror and bulk driven cascode current mirror, respectively.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"121 1","pages":"240-242"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73767727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804057
Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen
Polar Codes become a new channel coding, which will be common to apply for next-generation wireless MIMO communication systems. In this work, we propose LEGO-based VLSI hardware design and implementation of the Polar encoder using radix-2 processing engines, which features low area cost, low power dissipation, high speed, and high throughput via serial computation. Under TSMC 90nm CMOS technology, the 16384-point LEGO-based radix-2 Polar encoder chip (LB-R2-PE) is designed and synthesized with total area of 0.244mm2 and power dissipation of 366.6mW, operating at maximum frequency of 2.0GHz. In the APR chip implementation point-of-view, the 16384-point LB-R2-PE chip only occupies 0.305mm2 and consumes 357.8mW with maximum operating frequency of 1.61GHz, delivering total throughput of 1.61Gbps.
{"title":"LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines","authors":"Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen","doi":"10.1109/APCCAS.2016.7804057","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804057","url":null,"abstract":"Polar Codes become a new channel coding, which will be common to apply for next-generation wireless MIMO communication systems. In this work, we propose LEGO-based VLSI hardware design and implementation of the Polar encoder using radix-2 processing engines, which features low area cost, low power dissipation, high speed, and high throughput via serial computation. Under TSMC 90nm CMOS technology, the 16384-point LEGO-based radix-2 Polar encoder chip (LB-R2-PE) is designed and synthesized with total area of 0.244mm2 and power dissipation of 366.6mW, operating at maximum frequency of 2.0GHz. In the APR chip implementation point-of-view, the 16384-point LB-R2-PE chip only occupies 0.305mm2 and consumes 357.8mW with maximum operating frequency of 1.61GHz, delivering total throughput of 1.61Gbps.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"224 1","pages":"577-580"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75565366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803929
Sunwoong Kim, Hyuk-Jae Lee
RGBW domain is widely used to improve the brightness of display panels without their increasing power consumption. RGBW display systems use a look-up table (LUT) for fast RGB-to-RGBW conversion. However, the LUT is implemented by a large size memory and thereby incurring high hardware cost. To reduce the size of the LUT, data mapping in the LUT are sub-sampled, which results in large errors in data conversion. Based on the piecewise-linear characteristic in color change, the sub-sampled data are linearly interpolated. In addition, the interpolation performance is improved by utilizing distribution patterns of color components. Experimental results show that the average of the mean square errors by the proposed method is 21.72 when the size of the LUT decreases to 1/215 of the original LUT size.
{"title":"A design of a cost-effective look-up table for RGB-to-RGBW conversion","authors":"Sunwoong Kim, Hyuk-Jae Lee","doi":"10.1109/APCCAS.2016.7803929","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803929","url":null,"abstract":"RGBW domain is widely used to improve the brightness of display panels without their increasing power consumption. RGBW display systems use a look-up table (LUT) for fast RGB-to-RGBW conversion. However, the LUT is implemented by a large size memory and thereby incurring high hardware cost. To reduce the size of the LUT, data mapping in the LUT are sub-sampled, which results in large errors in data conversion. Based on the piecewise-linear characteristic in color change, the sub-sampled data are linearly interpolated. In addition, the interpolation performance is improved by utilizing distribution patterns of color components. Experimental results show that the average of the mean square errors by the proposed method is 21.72 when the size of the LUT decreases to 1/215 of the original LUT size.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"64 1","pages":"188-191"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88599679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803890
Fan Yang, Yasu Lu, P. Mok
An analytical study of designing power stage for the emerging digital LDO is presented in this paper. Two widely adopted sizing options are discussed, namely binary and multiple-unary weighted power stage sizing. Both methods target at realizing a balanced speed and resolution of the digital LDO. The binary sizing benefits the large current step, however, in average, may render a more oscillating voltage settling. The multiple unary sizing overcomes this by a step-by-step voltage regulation, and the speed is improved if a larger step size is selected. The difference of the required clock frequency, and suggestions in designing power stage are discussed in this paper as well. This comparative analysis is further verified by simulations in a 65-nm CMOS process.
{"title":"A comparative analysis on binary and multiple-unary weighted power stage design for digital LDO","authors":"Fan Yang, Yasu Lu, P. Mok","doi":"10.1109/APCCAS.2016.7803890","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803890","url":null,"abstract":"An analytical study of designing power stage for the emerging digital LDO is presented in this paper. Two widely adopted sizing options are discussed, namely binary and multiple-unary weighted power stage sizing. Both methods target at realizing a balanced speed and resolution of the digital LDO. The binary sizing benefits the large current step, however, in average, may render a more oscillating voltage settling. The multiple unary sizing overcomes this by a step-by-step voltage regulation, and the speed is improved if a larger step size is selected. The difference of the required clock frequency, and suggestions in designing power stage are discussed in this paper as well. This comparative analysis is further verified by simulations in a 65-nm CMOS process.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"94 1","pages":"41-42"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83920105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804014
Yung-Hao Lai, Yang-Lang Chang, Jyh-Perng Fang, Jie-Hung Lee
Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.
{"title":"Simultaneous layer-aware and region-aware partitioning for 3D IC","authors":"Yung-Hao Lai, Yang-Lang Chang, Jyh-Perng Fang, Jie-Hung Lee","doi":"10.1109/APCCAS.2016.7804014","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804014","url":null,"abstract":"Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"91 1","pages":"502-505"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78673789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804025
Yongchan Kim, Hojin Lee
In this paper, we presented a low-dropout (LDO) regulator composed with amorphous indium-gallium-zinc-oxide thin-film transistors (a-InGaZnO TFTs) for display driving systems. Through extensive simulation works, we confirmed that the proposed LDO regulator successfully could control the output voltage levels to follow the reference input voltages, and the output voltage ripple could be suppressed below 48mV when input reference voltage was changed from 14V to 15V with 100mV fluctuation.
{"title":"Design of low-dropout regulator using a-InGaZnO thin-film transistors","authors":"Yongchan Kim, Hojin Lee","doi":"10.1109/APCCAS.2016.7804025","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804025","url":null,"abstract":"In this paper, we presented a low-dropout (LDO) regulator composed with amorphous indium-gallium-zinc-oxide thin-film transistors (a-InGaZnO TFTs) for display driving systems. Through extensive simulation works, we confirmed that the proposed LDO regulator successfully could control the output voltage levels to follow the reference input voltages, and the output voltage ripple could be suppressed below 48mV when input reference voltage was changed from 14V to 15V with 100mV fluctuation.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"15 1","pages":"546-547"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76887257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804017
Hyun-jeong Kwon, Young Hwan Kim
We propose an analytic method to calculate the probability of timing violation of F/F-controlled paths by considering timing variations. We first characterize the timing characteristics of F/Fs and path delays using a generalized canonical delay model. The probability of setup-time violation is then calculated by considering the correlation between F/Fs and logic paths. For the calculation, we used conditional tightness probability equation which reflects the nonlinearity of the process parameters. In experiments, the proposed method exhibited the error less than 7 % with respect to Monte-Carlo (MC) simulation results. Compared to the benchmark method that does not consider the variations of the timing characteristics of F/Fs, the proposed method improved the accuracy by more than 18% on average.
{"title":"Calculating the probability of timing violation of F/F-controlled paths with timing variations","authors":"Hyun-jeong Kwon, Young Hwan Kim","doi":"10.1109/APCCAS.2016.7804017","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804017","url":null,"abstract":"We propose an analytic method to calculate the probability of timing violation of F/F-controlled paths by considering timing variations. We first characterize the timing characteristics of F/Fs and path delays using a generalized canonical delay model. The probability of setup-time violation is then calculated by considering the correlation between F/Fs and logic paths. For the calculation, we used conditional tightness probability equation which reflects the nonlinearity of the process parameters. In experiments, the proposed method exhibited the error less than 7 % with respect to Monte-Carlo (MC) simulation results. Compared to the benchmark method that does not consider the variations of the timing characteristics of F/Fs, the proposed method improved the accuracy by more than 18% on average.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"7 1","pages":"514-517"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76966718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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