Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803882
Truong Phu Truan Ho, Chip-Hong Chang
Recent hardware implementations of fully homomorphic encryption (FHE) exploit very high cardinality arbitrary moduli sets to parallelize large integer arithmetic. However, the benefit they gained are heavily offset by the slow residue-to-binary conversion due to the large modulo operations and limited number theoretic properties of arbitrary moduli. This paper presents a fast residue-to-binary (R2B) conversion method by transforming a large number of residues of arbitrary moduli into only three residues before the conversion. It exploits the smaller and parallel operations of base extension for the mapping to {2n−1, 2n, 2n +1} and the highly efficient adder-based R2B converter of the latter to achieve 2.25 ∼ 6.8 times speedup over recent R2B converters, which translates to approximately 10.2% to 32.08% of overall speed improvement for their FHE implementations.
{"title":"Accelerating residue-to-binary conversion of very high cardinality moduli set for fully homomorphic encryption","authors":"Truong Phu Truan Ho, Chip-Hong Chang","doi":"10.1109/APCCAS.2016.7803882","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803882","url":null,"abstract":"Recent hardware implementations of fully homomorphic encryption (FHE) exploit very high cardinality arbitrary moduli sets to parallelize large integer arithmetic. However, the benefit they gained are heavily offset by the slow residue-to-binary conversion due to the large modulo operations and limited number theoretic properties of arbitrary moduli. This paper presents a fast residue-to-binary (R2B) conversion method by transforming a large number of residues of arbitrary moduli into only three residues before the conversion. It exploits the smaller and parallel operations of base extension for the mapping to {2n−1, 2n, 2n +1} and the highly efficient adder-based R2B converter of the latter to achieve 2.25 ∼ 6.8 times speedup over recent R2B converters, which translates to approximately 10.2% to 32.08% of overall speed improvement for their FHE implementations.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"33 1","pages":"9-12"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74442925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803916
Chun-Shen Liu, Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu
Next-generation sequencing (NGS) has been widely applied to biological and medical researches for its efficient production of DNA short reads nowadays. Among various applications, de novo sequence assembly is a technique using NGS short reads to obtain a whole genome with no reference. To make assembly results accurate, it is a common practice to filter out low-quality data at the early stage of the assembly pipeline. Since filtering takes a great portion of assembly time, how to increase the processing speed of filtering stage becomes an important issue, especially with growing data scale in recent applications. In this paper, we propose an FPGA-based quality filter to accelerate the filtering step. With the introduction of the One-Hot-encoded accumulator and related modules, the hardware filter can reduce the processing time by half.
新一代测序技术以其高效的短链测序技术在生物学和医学研究中得到了广泛的应用。de novo sequence assembly在众多应用中，de novo sequence assembly是一种利用NGS短reads获得无参考全基因组的技术。为了使装配结果准确，通常的做法是在装配管道的早期阶段过滤掉低质量的数据。由于滤波占用了大量的装配时间，如何提高滤波阶段的处理速度成为一个重要的问题，特别是在最近的应用中，随着数据规模的增长。在本文中，我们提出了一种基于fpga的高质量滤波器来加快滤波步骤。通过引入One-Hot-encoded蓄电池和相关模块,硬件滤波器可以减少处理时间减半。
{"title":"An FPGA-based quality filter for de novo sequence assembly pipeline","authors":"Chun-Shen Liu, Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu","doi":"10.1109/APCCAS.2016.7803916","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803916","url":null,"abstract":"Next-generation sequencing (NGS) has been widely applied to biological and medical researches for its efficient production of DNA short reads nowadays. Among various applications, de novo sequence assembly is a technique using NGS short reads to obtain a whole genome with no reference. To make assembly results accurate, it is a common practice to filter out low-quality data at the early stage of the assembly pipeline. Since filtering takes a great portion of assembly time, how to increase the processing speed of filtering stage becomes an important issue, especially with growing data scale in recent applications. In this paper, we propose an FPGA-based quality filter to accelerate the filtering step. With the introduction of the One-Hot-encoded accumulator and related modules, the hardware filter can reduce the processing time by half.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"18 1","pages":"139-142"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72596810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804076
N. Vamsi, Sesha Sairam Ragulagadda, A. Dutta, S. Singh
A new approach for a battery-less 915MHz ISM band wake-up receiver with digital decoder for wireless sensor network is designed and presented. The proposed receiver architecture is based on a differential rectifier with gate-driver circuit using an ON-OFF Keying modulation for the input signal. To enhance the power conversion efficiency (PCE) of the rectifier for the low input power level, appropriate gate-drive voltages for each stage of the rectifier are generated using a chain of auxiliary floating rectifier cells. The wake-up receiver is designed in 0.18μm CMOS technology and achieves a sensitivity of −34 dBm at 0.8V for a 100 kbps.
{"title":"A −34dBm sensitivity battery-less wake-up receiver with digital decoder","authors":"N. Vamsi, Sesha Sairam Ragulagadda, A. Dutta, S. Singh","doi":"10.1109/APCCAS.2016.7804076","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804076","url":null,"abstract":"A new approach for a battery-less 915MHz ISM band wake-up receiver with digital decoder for wireless sensor network is designed and presented. The proposed receiver architecture is based on a differential rectifier with gate-driver circuit using an ON-OFF Keying modulation for the input signal. To enhance the power conversion efficiency (PCE) of the rectifier for the low input power level, appropriate gate-drive voltages for each stage of the rectifier are generated using a chain of auxiliary floating rectifier cells. The wake-up receiver is designed in 0.18μm CMOS technology and achieves a sensitivity of −34 dBm at 0.8V for a 100 kbps.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"9 1","pages":"721-724"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79078418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803918
Tsung-Han Tsai, Kung-Long Zhang
The intelligence for home appliances becomes more and more necessary in recent years. It can be developed based on the techniques from intelligent surveillance systems, and integrated with video sensor. In this paper, we propose an implementation of intelligent home appliances. This system typically involves several tasks including foreground detection, noise reduction, object labeling, object recognition and wireless transmission. To realize it on IoT (internet of things) era, we use the transmission device with Bluetooth 4.0 protocol. As a result we will receive the signal on mobile device applications if some dangerous situations is happened. We implement the whole system on embedded system to make a demonstration result. This system will help us to take care of our children prevent from danger appliances and inform the danger situation immediately.
{"title":"Implementation of intelligent home appliances based on IoT","authors":"Tsung-Han Tsai, Kung-Long Zhang","doi":"10.1109/APCCAS.2016.7803918","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803918","url":null,"abstract":"The intelligence for home appliances becomes more and more necessary in recent years. It can be developed based on the techniques from intelligent surveillance systems, and integrated with video sensor. In this paper, we propose an implementation of intelligent home appliances. This system typically involves several tasks including foreground detection, noise reduction, object labeling, object recognition and wireless transmission. To realize it on IoT (internet of things) era, we use the transmission device with Bluetooth 4.0 protocol. As a result we will receive the signal on mobile device applications if some dangerous situations is happened. We implement the whole system on embedded system to make a demonstration result. This system will help us to take care of our children prevent from danger appliances and inform the danger situation immediately.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"347 1","pages":"146-148"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79674702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803944
Lidan Wang, Chenchang Zhan, Guofeng Li
An ultra-low power and offset-insensitive CMOS voltage reference circuit is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed circuit can suppress the DC offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions, and improving the power supply ripple rejection (PSRR) are presented. The voltage reference is implemented in a 0.18μm CMOS process. Simulation results show that the reference can run with 0.8 V supply voltage, while the power consumption is only 62nW, and the PSRR of better than −43 dB over the full frequency range is achieved.
{"title":"An ultra-low power and offset-insensitive CMOS subthreshold voltage reference","authors":"Lidan Wang, Chenchang Zhan, Guofeng Li","doi":"10.1109/APCCAS.2016.7803944","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803944","url":null,"abstract":"An ultra-low power and offset-insensitive CMOS voltage reference circuit is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed circuit can suppress the DC offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions, and improving the power supply ripple rejection (PSRR) are presented. The voltage reference is implemented in a 0.18μm CMOS process. Simulation results show that the reference can run with 0.8 V supply voltage, while the power consumption is only 62nW, and the PSRR of better than −43 dB over the full frequency range is achieved.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"38 1","pages":"243-246"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80326001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803958
Itaru Hida, M. Ikebe, T. Asai, M. Motomura
In this paper, we propose a Bayesian branch-prediction circuit consisting of an instruction-feature extractor and a naïve Bayes classifier (NBC). Its purpose is to replace conventional branch predictors in modern pipelined RISC microprocessors. The proposed circuit is based on the conventional neural branch predictor [1]; however, the linear classifier circuit is replaced by the proposed NBC circuit. Implementing approximate Bayesian computation and its highly-parallel architectures, the NBC circuit completes branch prediction within 2 clock cycles per instruction, and is this suitable for implementation on standard pipelined microprocessors.
{"title":"A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors","authors":"Itaru Hida, M. Ikebe, T. Asai, M. Motomura","doi":"10.1109/APCCAS.2016.7803958","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803958","url":null,"abstract":"In this paper, we propose a Bayesian branch-prediction circuit consisting of an instruction-feature extractor and a naïve Bayes classifier (NBC). Its purpose is to replace conventional branch predictors in modern pipelined RISC microprocessors. The proposed circuit is based on the conventional neural branch predictor [1]; however, the linear classifier circuit is replaced by the proposed NBC circuit. Implementing approximate Bayesian computation and its highly-parallel architectures, the NBC circuit completes branch prediction within 2 clock cycles per instruction, and is this suitable for implementation on standard pipelined microprocessors.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"26 1","pages":"297-300"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80362851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803892
Y. Jang, Seong-Eun Cho, Byungsub Kim, J. Sim, Hong-June Park
By adding a Miller frequency compensation to the conventional LDO circuit that combines the super source follower and the voltage spike detection, a low-power LDO circuit is proposed to drive the load capacitance up to 10 pF with a fast load regulation. The LDO circuit converts a 5 V input to a 3.3V output, consumes 26 μA, and settles in 75 ns at a 10 mA load current step in 1ns.
{"title":"A low-power LDO circuit with a fast load regulation","authors":"Y. Jang, Seong-Eun Cho, Byungsub Kim, J. Sim, Hong-June Park","doi":"10.1109/APCCAS.2016.7803892","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803892","url":null,"abstract":"By adding a Miller frequency compensation to the conventional LDO circuit that combines the super source follower and the voltage spike detection, a low-power LDO circuit is proposed to drive the load capacitance up to 10 pF with a fast load regulation. The LDO circuit converts a 5 V input to a 3.3V output, consumes 26 μA, and settles in 75 ns at a 10 mA load current step in 1ns.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"68 1","pages":"47-49"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80887602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803948
Guan-Yi Li, Chun-Yu Lin
To effectively protect the radio-frequency (RF) integrated circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, the on-chip ESD protection circuits must be added at the pads that may be stressed by ESD. In this paper, a large-swing-tolerant ESD protection circuit is presented to protect the gigahertz large-swing power amplifier (PA). The proposed ESD protection circuit of diode string with embedded silicon-controlled rectifier (DSSCR) has been designed, fabricated, and verified in silicon chip. With the better RF performances and ESD robustness, the DSSCR can be further applied to the large-swing PA.
{"title":"On-chip ESD protection design for radio-frequency power amplifier with large-swing-tolerance consideration","authors":"Guan-Yi Li, Chun-Yu Lin","doi":"10.1109/APCCAS.2016.7803948","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803948","url":null,"abstract":"To effectively protect the radio-frequency (RF) integrated circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, the on-chip ESD protection circuits must be added at the pads that may be stressed by ESD. In this paper, a large-swing-tolerant ESD protection circuit is presented to protect the gigahertz large-swing power amplifier (PA). The proposed ESD protection circuit of diode string with embedded silicon-controlled rectifier (DSSCR) has been designed, fabricated, and verified in silicon chip. With the better RF performances and ESD robustness, the DSSCR can be further applied to the large-swing PA.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"26 1","pages":"258-261"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80938784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804047
Zdeněk Biolek, D. Biolek, V. Biolková
The problem of charging the capacitor from a voltage source via a resistor is a common part of introductory courses of the circuit theory. None the less, the paper brings some new information concerning the energetic aspects of this process, particularly as regards charging via a time-varying resistor or charge-dependent resistor, the so-called memristor. The efficiency of the charging process is also specified for special cases, which can appear due to certain pathological characteristics of the resistor or memristor. The results of computer simulations fully correspond to the theoretical conclusions.
{"title":"Charging the capacitor via a (Memory) resistor","authors":"Zdeněk Biolek, D. Biolek, V. Biolková","doi":"10.1109/APCCAS.2016.7804047","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804047","url":null,"abstract":"The problem of charging the capacitor from a voltage source via a resistor is a common part of introductory courses of the circuit theory. None the less, the paper brings some new information concerning the energetic aspects of this process, particularly as regards charging via a time-varying resistor or charge-dependent resistor, the so-called memristor. The efficiency of the charging process is also specified for special cases, which can appear due to certain pathological characteristics of the resistor or memristor. The results of computer simulations fully correspond to the theoretical conclusions.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"33 1","pages":"621-624"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89700373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803974
Sunghyun Kim, Youngmin Kim
Approximation in the adder logic is a promising solution for energy-efficient designs in various applications. In this study, new hybrid adder design, which consists of an accurate adder for higher bits and proposed approximate adders for lower bits, is investigated. The XOR-based inexact adder is modified to be used in the approximation part. Simulation results of 16-bits adders show that error rates can be reduced significantly by the proposed hybrid adder compared to other approximation adders with smaller number of transistors than an accurate adder.
{"title":"Energy-efficient hybrid adder design by using inexact lower bits adder","authors":"Sunghyun Kim, Youngmin Kim","doi":"10.1109/APCCAS.2016.7803974","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803974","url":null,"abstract":"Approximation in the adder logic is a promising solution for energy-efficient designs in various applications. In this study, new hybrid adder design, which consists of an accurate adder for higher bits and proposed approximate adders for lower bits, is investigated. The XOR-based inexact adder is modified to be used in the approximation part. Simulation results of 16-bits adders show that error rates can be reduced significantly by the proposed hybrid adder compared to other approximation adders with smaller number of transistors than an accurate adder.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"19 1","pages":"355-357"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89964219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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