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2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献

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Electrochromic display driving scheme for high dynamic range image capture 高动态范围图像捕获的电致变色显示驱动方案
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804053
Seok-Jeong Song, Dowon Kim, Jeongrim Seo, Ki-Hyuk Seol, Hyoungsik Nam
This paper describes a new high dynamic range (HDR) image capture system that utilizes an electrochromic display (ECD). The ECD panel reduces the transmittance of bright area and increases the transmittance of dark area, which retain as much information as possible without saturation at high or low luminance. A passive matrix driving scheme is employed for the ECD due to low cost and high transmittance and the column and row driving voltages are obtained by least square error method. The resulting information gain defined as the maximum gray scale ratio of HDR and normal images is 1.73.
本文介绍了一种利用电致变色显示器(ECD)的新型高动态范围(HDR)图像捕获系统。ECD面板降低了明亮区域的透光率,增加了黑暗区域的透光率,在高或低亮度下都保留了尽可能多的信息而不饱和。由于成本低、透光率高,采用无源矩阵驱动方案,采用最小二乘误差法获得柱、行驱动电压。所得的信息增益定义为HDR图像与正常图像的最大灰度比为1.73。
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引用次数: 0
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction 基于像素的流水线硬件架构,用于高性能haar类特征提取
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804044
Y. Fujita, F. An, A. Luo, X. Zhang, Lei Chen, H. Mattausch
Feature extraction, which is one of the basic tasks for pattern recognition, has often high computational cost and large memory usage. In this work, we propose a pixel-based pipeline hardware architecture for Haar-like feature extraction, implemented in 0.18 μm CMOS technology with 1.76 mm2 core area. Pixel-input speed relies on the working frequency of the image sensor so that features are extracted in real time without on-chip image buffer and complex computational procedures. The fabricated chip consumes 4.78 mW power at 1.8 V supply voltage and 12.5 MHz frequency during 30 fps VGA video input. Furthermore, a processing time of 3.07 ms per VGA frame with power dissipation of 36.25 mW at 100 MHz frequency is possible.
特征提取是模式识别的基本任务之一,计算量大,内存占用大。在这项工作中,我们提出了一种基于像素的流水线硬件架构,用于haar类特征提取,该架构采用0.18 μm CMOS技术,核心面积为1.76 mm2。像素输入速度依赖于图像传感器的工作频率,因此无需片上图像缓冲和复杂的计算过程即可实时提取特征。该芯片在1.8 V电源电压和12.5 MHz频率下,在30 fps的VGA视频输入下,功耗为4.78 mW。此外,在100 MHz频率下,每个VGA帧的处理时间为3.07 ms,功耗为36.25 mW是可能的。
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引用次数: 0
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS 现场演示:一种128通道峰值排序处理器,每通道0.175 μW和0.0033 mm2,采用65纳米CMOS
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804030
S. Zeinolabedin, A. Do, Dongsuk Jeon, D. Sylvester, T. T. Kim
Multi-electrode intracranial recording technology is highly required for various applications such as brain studies, brain machine interface (BMI) and treatment of disorders like epilepsy, memory loss and paralysis. The recording is done by inserting electrodes into the extracellular tissue of the brain to supposedly record the single-unit activity. However, the recorded signal is the summation of some near-by neurons activities and the background noise. Therefore, after recording and digitizing the signal by analog front-end, the first crucial step is to extract the information from extracellular recording [1]. This process is called spike sorting and shown in Fig. 1. It basically assigns the detected spike to their source neurons located near the corresponding recording electrodes.
多电极颅内记录技术在脑研究、脑机接口(BMI)以及癫痫、记忆丧失和瘫痪等疾病的治疗等各种应用中都有很高的需求。记录是通过将电极插入大脑的细胞外组织来记录单个单位的活动。然而,记录的信号是一些附近的神经元活动和背景噪声的总和。因此,在模拟前端对信号进行记录和数字化后,关键的第一步是从细胞外记录中提取信息[1]。这个过程被称为尖峰排序,如图1所示。它基本上将检测到的尖峰分配给位于相应记录电极附近的源神经元。
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引用次数: 0
A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control 具有稳态负载电流(SLC)估计器和动态增益缩放(DGS)控制的数字低差调节器
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803889
Jian-He Lin, Wen-Jie Tsou, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai
Conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn-on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18μm CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.
传统的数字低差(D-LDO)稳压器由于采用移位寄存器结构,在瞬态响应过程中存在稳定时间长的缺点。本文提出的D-LDO稳压器可以观察负载暂态期间的输出电压变化,从而预测负载电流,实现快速的暂态响应。利用所提出的稳态负载电流(SLC)估计器可以得到稳态时的近最优导通功率,而动态增益缩放(DGS)技术可以改善瞬态响应并避免限环振荡(LCO)问题。测试芯片采用0.18μm CMOS工艺设计。仿真结果表明,瞬态响应时间由920ns缩短至115ns,缩短了88%。
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引用次数: 5
VLSI layout hotspot detection based on discriminative feature extraction 基于判别特征提取的VLSI版图热点检测
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804024
Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young
Feature extraction is a key stage in machine learning based VLSI layout hotspot detection flow. Conventional machine learning based methods apply various feature extraction techniques to approximate an original layout structure at nanometer level. However, some important layout pattern information is missed during the approximation process, resulting in performance degradation. In this paper, we present a comprehensive study on layout feature extraction and propose a new method that can preserve discriminative layout pattern information to improve the detection performance in terms of accuracy and extra. Experiments were conducted on an industrial benchmark and ICCAD benchmark suite to study the effectiveness of our proposed methods.
特征提取是基于机器学习的超大规模集成电路版图热点检测流程的关键环节。传统的基于机器学习的方法采用各种特征提取技术来近似纳米级的原始布局结构。然而,在逼近过程中会遗漏一些重要的布局模式信息,从而导致性能下降。本文对布局特征提取进行了全面的研究,提出了一种保留可鉴别的布局模式信息的新方法,以提高检测的准确性和额外性能。在工业基准和ICCAD基准套件上进行了实验,以研究我们提出的方法的有效性。
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引用次数: 1
An efficient, wide range time-to-digital converter using cascaded time-interpolation stages for electrical impedance spectroscopy 一个有效的,宽范围的时间-数字转换器使用级联时间插值阶段电阻抗谱
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803993
Seongheon Shin, Soon-Jae Kweon, Jeong-Ho Park, Yong-Chang Choi, Hyung-Joun Yoo
This paper proposes a novel architecture of time-to-digital converter (TDC) with wide input range in polar demodulators for electrical impedance spectroscopy (EIS) systems. The system combines a counter-based TDC with cascaded time interpolation stages and efficiently quantizes the phase component. The maximum phase error of 0.52 degrees from 1-kHz to 2.048-MHz frequency sweep range superior to previously reported ones. Reconfigurability of interpolation factor and cascaded architecture greatly enhances hardware efficiency of the system with average power consumption of 1.93 mW, which makes this work worth for system-on-chip (SoC) realization of EIS systems based on polar demodulators.
本文提出了一种用于电阻抗谱(EIS)系统极性解调的宽输入范围时间-数字转换器(TDC)的新结构。该系统结合了基于计数器的TDC和级联时间插值阶段,有效地量化了相位分量。从1 khz到2.048 mhz频率扫描范围的最大相位误差为0.52度,优于先前报道的。插值因子的可重构性和级联架构极大地提高了系统的硬件效率,平均功耗仅为1.93 mW,这对基于极性解调器的EIS系统的SoC实现具有一定的参考价值。
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引用次数: 3
Low-cost prototype design of a portable ECG signal recorder 便携式心电信号记录仪的低成本原型设计
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803922
Shin-Chi Lai, Te-Hsuan Hung, W. Li, Yun-Syuan Jhang, Kuan-Ying Chang, Wen-Ho Juang, C. Luo
This paper presents an acquisition system design integrated with the Arduino Nano platform and commercial ICs for the prototype development of a portable ECG signal monitor. A simply lossless ECG compression algorithm with a better Compression Ratio (CR) is employed to reduce a great amount of storage and transmission recording data. The result proves that the CR averages are 2.53 for ECG test patterns from MIT-BIH arrhythmia database. The experimental result also shows a pure ECG signal can be easily acquired by using a 16-tap low-pass digital filter. Therefore, the proposed design would be a good choice for the application of ECG signal acquisition in the future.
本文提出了一种集成Arduino Nano平台和商用ic的采集系统设计,用于便携式心电信号监测仪的原型开发。为了减少大量的存储和传输记录数据,采用了一种具有较好压缩比(CR)的简单无损心电压缩算法。结果表明,MIT-BIH心律失常数据库心电图试验模式的平均CR值为2.53。实验结果还表明,使用16分路低通数字滤波器可以很容易地获得纯净的心电信号。因此,本设计将是今后心电信号采集应用的一个很好的选择。
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引用次数: 6
A low power relaxation oscillator with process insensitive auto-calibration scheme 具有过程不敏感自动校准方案的低功率弛豫振荡器
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804068
Xin Lu, Bo Wang, Zhihuang Wen, Xiaojin Zhao, Yuan Cao, A. Bermak
In this paper, we present an auto-calibrated process insensitive relaxation oscillator. A process sensitivity of 1.36% is achieved by automatically sensing the output clock frequency spread and alternatively adjusting the capacitor-used for charging and discharging. In addition, a time to digital converter is adopted for tuning the compensating capacitor. Moreover, the proposed oscillator with on-chip calibration scheme, implemented by UMC 0.18μm 1P6M standard process, is validated by our reported extensive post-layout simulation results. A frequency of 32.7 kHz can be generated by operating the system under 1V supply voltage.
本文提出了一种自校准过程不敏感弛豫振荡器。通过自动感知输出时钟频率扩展和交替调节用于充电和放电的电容器,实现了1.36%的过程灵敏度。此外,还采用时数字式变换器对补偿电容进行调谐。此外,采用UMC 0.18μm 1P6M标准工艺实现的片上校准方案通过大量布局后仿真结果进行了验证。在1V电源电压下操作系统可产生32.7 kHz的频率。
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引用次数: 1
Unified HW/SW framework for efficient system level simulation 统一的硬件/软件框架,实现高效的系统级仿真
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804018
N. Sutisna, L. Lanante, Y. Nagao, M. Kurosaki, H. Ochi
In this paper, we present unified Hardware (HW)/Software (SW) framework for efficient system level simulation of complex circuits, particularly high throughput wireless communication system. The proposed framework include a unified methodology covering both of system level simulation (e.g. MATLAB or C/C++) and physical level verification (e.g FPGA). It allows performing fast HW/SW evaluation in the context of system level performance and also covering large number of verification scenarios within acceptable time. Experimental evaluations show the example design case achieves improvement of simulation time several orders of magnitude faster than pure software simulation and also capable to run in near real-time processing. Moreover, the proposed verification platform can be used for complete performance characterization of a MIMO wireless system under various system parameters, hardware impairments and channel model.
在本文中,我们提出了统一的硬件(HW)/软件(SW)框架,用于复杂电路,特别是高吞吐量无线通信系统的高效系统级仿真。提出的框架包括一个统一的方法,涵盖系统级仿真(例如MATLAB或C/ c++)和物理层验证(例如FPGA)。它允许在系统级性能上下文中执行快速的硬件/软件评估,并且在可接受的时间内覆盖大量的验证场景。实验评估表明,实例设计案例的仿真时间比纯软件仿真快了几个数量级,并且能够在接近实时的处理中运行。此外,所提出的验证平台可用于在各种系统参数、硬件缺陷和信道模型下对MIMO无线系统进行完整的性能表征。
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引用次数: 1
A tunable power amplifier employing digitally controlled accumulation-mode varactor array for 2.4-GHz short-range wireless communication 一种用于2.4 ghz短距离无线通信的可调功率放大器,采用数字控制累加模式变容二极管阵列
Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803951
Sanggil Kim, D. Im
The most popular tunable capacitor topologies in CMOS are the analog varactor and digitally controlled switched capacitor array (SCA). The conventional analog varactor shows a high quality factor (g-factor) in both the minimum capacitance (Cmin) and the maximum capacitance (Cmax) states with a wide tuning range, but it has a poor linearity performance due to the voltage dependent nonlinear capacitance. In case of the digitally controlled switched capacitor array, while it shows a very good linearity, its g-factor in Cmin state is strongly dependent on the substrate loss by the parasitic junction capacitances between p-well, deep n-well, and p-substrate and the substrate resistance. To overcome the aforementioned drawbacks of the analog varactor and the switched capacitor array, the digitally controlled binary-weighted accumulation-mode varactor array (AVA) is proposed. In the simulation, at 2.4 GHz frequency band, the proposed tunable capacitor shows a g-factor of greater than 60 over all states and a tuning range of 3. The inverter-based push-pull power amplifier (PA) with the tunable matching network (TMN) employing the proposed tunable capacitor extends the impedance coverage maintaining the output power of greater than 0 dBm under the worst case for antenna impedance mismatch.
CMOS中最流行的可调谐电容器拓扑是模拟变容管和数字控制开关电容器阵列(SCA)。传统的模拟变容器在最小电容(Cmin)和最大电容(Cmax)状态下均具有较高的质量因子(g因子),且调谐范围宽,但由于其电压相关的非线性电容,其线性性能较差。对于数字控制开关电容阵列,虽然其线性度非常好,但其在Cmin状态下的g因子强烈依赖于p-井、深n-井和p-衬底之间的寄生结电容和衬底电阻造成的衬底损耗。为了克服模拟变容管和开关电容阵列的上述缺点,提出了一种数字控制二加权累加型变容管阵列(AVA)。仿真结果表明,在2.4 GHz频段,所提出的可调谐电容在所有状态下的g因子均大于60,调谐范围为3。基于逆变器的推挽功率放大器(PA)与采用所提出的可调谐电容的可调谐匹配网络(TMN)扩展了阻抗覆盖范围,在天线阻抗失配的最坏情况下保持输出功率大于0 dBm。
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引用次数: 1
期刊
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
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