Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804053
Seok-Jeong Song, Dowon Kim, Jeongrim Seo, Ki-Hyuk Seol, Hyoungsik Nam
This paper describes a new high dynamic range (HDR) image capture system that utilizes an electrochromic display (ECD). The ECD panel reduces the transmittance of bright area and increases the transmittance of dark area, which retain as much information as possible without saturation at high or low luminance. A passive matrix driving scheme is employed for the ECD due to low cost and high transmittance and the column and row driving voltages are obtained by least square error method. The resulting information gain defined as the maximum gray scale ratio of HDR and normal images is 1.73.
{"title":"Electrochromic display driving scheme for high dynamic range image capture","authors":"Seok-Jeong Song, Dowon Kim, Jeongrim Seo, Ki-Hyuk Seol, Hyoungsik Nam","doi":"10.1109/APCCAS.2016.7804053","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804053","url":null,"abstract":"This paper describes a new high dynamic range (HDR) image capture system that utilizes an electrochromic display (ECD). The ECD panel reduces the transmittance of bright area and increases the transmittance of dark area, which retain as much information as possible without saturation at high or low luminance. A passive matrix driving scheme is employed for the ECD due to low cost and high transmittance and the column and row driving voltages are obtained by least square error method. The resulting information gain defined as the maximum gray scale ratio of HDR and normal images is 1.73.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"29 1","pages":"637-639"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83708813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804044
Y. Fujita, F. An, A. Luo, X. Zhang, Lei Chen, H. Mattausch
Feature extraction, which is one of the basic tasks for pattern recognition, has often high computational cost and large memory usage. In this work, we propose a pixel-based pipeline hardware architecture for Haar-like feature extraction, implemented in 0.18 μm CMOS technology with 1.76 mm2 core area. Pixel-input speed relies on the working frequency of the image sensor so that features are extracted in real time without on-chip image buffer and complex computational procedures. The fabricated chip consumes 4.78 mW power at 1.8 V supply voltage and 12.5 MHz frequency during 30 fps VGA video input. Furthermore, a processing time of 3.07 ms per VGA frame with power dissipation of 36.25 mW at 100 MHz frequency is possible.
{"title":"Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction","authors":"Y. Fujita, F. An, A. Luo, X. Zhang, Lei Chen, H. Mattausch","doi":"10.1109/APCCAS.2016.7804044","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804044","url":null,"abstract":"Feature extraction, which is one of the basic tasks for pattern recognition, has often high computational cost and large memory usage. In this work, we propose a pixel-based pipeline hardware architecture for Haar-like feature extraction, implemented in 0.18 μm CMOS technology with 1.76 mm2 core area. Pixel-input speed relies on the working frequency of the image sensor so that features are extracted in real time without on-chip image buffer and complex computational procedures. The fabricated chip consumes 4.78 mW power at 1.8 V supply voltage and 12.5 MHz frequency during 30 fps VGA video input. Furthermore, a processing time of 3.07 ms per VGA frame with power dissipation of 36.25 mW at 100 MHz frequency is possible.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"84 1","pages":"611-612"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79112722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804030
S. Zeinolabedin, A. Do, Dongsuk Jeon, D. Sylvester, T. T. Kim
Multi-electrode intracranial recording technology is highly required for various applications such as brain studies, brain machine interface (BMI) and treatment of disorders like epilepsy, memory loss and paralysis. The recording is done by inserting electrodes into the extracellular tissue of the brain to supposedly record the single-unit activity. However, the recorded signal is the summation of some near-by neurons activities and the background noise. Therefore, after recording and digitizing the signal by analog front-end, the first crucial step is to extract the information from extracellular recording [1]. This process is called spike sorting and shown in Fig. 1. It basically assigns the detected spike to their source neurons located near the corresponding recording electrodes.
{"title":"Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS","authors":"S. Zeinolabedin, A. Do, Dongsuk Jeon, D. Sylvester, T. T. Kim","doi":"10.1109/APCCAS.2016.7804030","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804030","url":null,"abstract":"Multi-electrode intracranial recording technology is highly required for various applications such as brain studies, brain machine interface (BMI) and treatment of disorders like epilepsy, memory loss and paralysis. The recording is done by inserting electrodes into the extracellular tissue of the brain to supposedly record the single-unit activity. However, the recorded signal is the summation of some near-by neurons activities and the background noise. Therefore, after recording and digitizing the signal by analog front-end, the first crucial step is to extract the information from extracellular recording [1]. This process is called spike sorting and shown in Fig. 1. It basically assigns the detected spike to their source neurons located near the corresponding recording electrodes.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"117 1","pages":"734-735"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87395680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn-on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18μm CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.
{"title":"A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control","authors":"Jian-He Lin, Wen-Jie Tsou, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai","doi":"10.1109/APCCAS.2016.7803889","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803889","url":null,"abstract":"Conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn-on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18μm CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"43 1","pages":"37-40"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91050902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804024
Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young
Feature extraction is a key stage in machine learning based VLSI layout hotspot detection flow. Conventional machine learning based methods apply various feature extraction techniques to approximate an original layout structure at nanometer level. However, some important layout pattern information is missed during the approximation process, resulting in performance degradation. In this paper, we present a comprehensive study on layout feature extraction and propose a new method that can preserve discriminative layout pattern information to improve the detection performance in terms of accuracy and extra. Experiments were conducted on an industrial benchmark and ICCAD benchmark suite to study the effectiveness of our proposed methods.
{"title":"VLSI layout hotspot detection based on discriminative feature extraction","authors":"Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young","doi":"10.1109/APCCAS.2016.7804024","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804024","url":null,"abstract":"Feature extraction is a key stage in machine learning based VLSI layout hotspot detection flow. Conventional machine learning based methods apply various feature extraction techniques to approximate an original layout structure at nanometer level. However, some important layout pattern information is missed during the approximation process, resulting in performance degradation. In this paper, we present a comprehensive study on layout feature extraction and propose a new method that can preserve discriminative layout pattern information to improve the detection performance in terms of accuracy and extra. Experiments were conducted on an industrial benchmark and ICCAD benchmark suite to study the effectiveness of our proposed methods.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"67 1","pages":"542-545"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91120404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803993
Seongheon Shin, Soon-Jae Kweon, Jeong-Ho Park, Yong-Chang Choi, Hyung-Joun Yoo
This paper proposes a novel architecture of time-to-digital converter (TDC) with wide input range in polar demodulators for electrical impedance spectroscopy (EIS) systems. The system combines a counter-based TDC with cascaded time interpolation stages and efficiently quantizes the phase component. The maximum phase error of 0.52 degrees from 1-kHz to 2.048-MHz frequency sweep range superior to previously reported ones. Reconfigurability of interpolation factor and cascaded architecture greatly enhances hardware efficiency of the system with average power consumption of 1.93 mW, which makes this work worth for system-on-chip (SoC) realization of EIS systems based on polar demodulators.
{"title":"An efficient, wide range time-to-digital converter using cascaded time-interpolation stages for electrical impedance spectroscopy","authors":"Seongheon Shin, Soon-Jae Kweon, Jeong-Ho Park, Yong-Chang Choi, Hyung-Joun Yoo","doi":"10.1109/APCCAS.2016.7803993","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803993","url":null,"abstract":"This paper proposes a novel architecture of time-to-digital converter (TDC) with wide input range in polar demodulators for electrical impedance spectroscopy (EIS) systems. The system combines a counter-based TDC with cascaded time interpolation stages and efficiently quantizes the phase component. The maximum phase error of 0.52 degrees from 1-kHz to 2.048-MHz frequency sweep range superior to previously reported ones. Reconfigurability of interpolation factor and cascaded architecture greatly enhances hardware efficiency of the system with average power consumption of 1.93 mW, which makes this work worth for system-on-chip (SoC) realization of EIS systems based on polar demodulators.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"40 1","pages":"425-428"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91214622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803922
Shin-Chi Lai, Te-Hsuan Hung, W. Li, Yun-Syuan Jhang, Kuan-Ying Chang, Wen-Ho Juang, C. Luo
This paper presents an acquisition system design integrated with the Arduino Nano platform and commercial ICs for the prototype development of a portable ECG signal monitor. A simply lossless ECG compression algorithm with a better Compression Ratio (CR) is employed to reduce a great amount of storage and transmission recording data. The result proves that the CR averages are 2.53 for ECG test patterns from MIT-BIH arrhythmia database. The experimental result also shows a pure ECG signal can be easily acquired by using a 16-tap low-pass digital filter. Therefore, the proposed design would be a good choice for the application of ECG signal acquisition in the future.
{"title":"Low-cost prototype design of a portable ECG signal recorder","authors":"Shin-Chi Lai, Te-Hsuan Hung, W. Li, Yun-Syuan Jhang, Kuan-Ying Chang, Wen-Ho Juang, C. Luo","doi":"10.1109/APCCAS.2016.7803922","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803922","url":null,"abstract":"This paper presents an acquisition system design integrated with the Arduino Nano platform and commercial ICs for the prototype development of a portable ECG signal monitor. A simply lossless ECG compression algorithm with a better Compression Ratio (CR) is employed to reduce a great amount of storage and transmission recording data. The result proves that the CR averages are 2.53 for ECG test patterns from MIT-BIH arrhythmia database. The experimental result also shows a pure ECG signal can be easily acquired by using a 16-tap low-pass digital filter. Therefore, the proposed design would be a good choice for the application of ECG signal acquisition in the future.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"26 1","pages":"160-163"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74770072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804068
Xin Lu, Bo Wang, Zhihuang Wen, Xiaojin Zhao, Yuan Cao, A. Bermak
In this paper, we present an auto-calibrated process insensitive relaxation oscillator. A process sensitivity of 1.36% is achieved by automatically sensing the output clock frequency spread and alternatively adjusting the capacitor-used for charging and discharging. In addition, a time to digital converter is adopted for tuning the compensating capacitor. Moreover, the proposed oscillator with on-chip calibration scheme, implemented by UMC 0.18μm 1P6M standard process, is validated by our reported extensive post-layout simulation results. A frequency of 32.7 kHz can be generated by operating the system under 1V supply voltage.
{"title":"A low power relaxation oscillator with process insensitive auto-calibration scheme","authors":"Xin Lu, Bo Wang, Zhihuang Wen, Xiaojin Zhao, Yuan Cao, A. Bermak","doi":"10.1109/APCCAS.2016.7804068","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804068","url":null,"abstract":"In this paper, we present an auto-calibrated process insensitive relaxation oscillator. A process sensitivity of 1.36% is achieved by automatically sensing the output clock frequency spread and alternatively adjusting the capacitor-used for charging and discharging. In addition, a time to digital converter is adopted for tuning the compensating capacitor. Moreover, the proposed oscillator with on-chip calibration scheme, implemented by UMC 0.18μm 1P6M standard process, is validated by our reported extensive post-layout simulation results. A frequency of 32.7 kHz can be generated by operating the system under 1V supply voltage.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"694-697"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72864283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804018
N. Sutisna, L. Lanante, Y. Nagao, M. Kurosaki, H. Ochi
In this paper, we present unified Hardware (HW)/Software (SW) framework for efficient system level simulation of complex circuits, particularly high throughput wireless communication system. The proposed framework include a unified methodology covering both of system level simulation (e.g. MATLAB or C/C++) and physical level verification (e.g FPGA). It allows performing fast HW/SW evaluation in the context of system level performance and also covering large number of verification scenarios within acceptable time. Experimental evaluations show the example design case achieves improvement of simulation time several orders of magnitude faster than pure software simulation and also capable to run in near real-time processing. Moreover, the proposed verification platform can be used for complete performance characterization of a MIMO wireless system under various system parameters, hardware impairments and channel model.
{"title":"Unified HW/SW framework for efficient system level simulation","authors":"N. Sutisna, L. Lanante, Y. Nagao, M. Kurosaki, H. Ochi","doi":"10.1109/APCCAS.2016.7804018","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804018","url":null,"abstract":"In this paper, we present unified Hardware (HW)/Software (SW) framework for efficient system level simulation of complex circuits, particularly high throughput wireless communication system. The proposed framework include a unified methodology covering both of system level simulation (e.g. MATLAB or C/C++) and physical level verification (e.g FPGA). It allows performing fast HW/SW evaluation in the context of system level performance and also covering large number of verification scenarios within acceptable time. Experimental evaluations show the example design case achieves improvement of simulation time several orders of magnitude faster than pure software simulation and also capable to run in near real-time processing. Moreover, the proposed verification platform can be used for complete performance characterization of a MIMO wireless system under various system parameters, hardware impairments and channel model.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"79 1","pages":"518-521"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73013392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803951
Sanggil Kim, D. Im
The most popular tunable capacitor topologies in CMOS are the analog varactor and digitally controlled switched capacitor array (SCA). The conventional analog varactor shows a high quality factor (g-factor) in both the minimum capacitance (Cmin) and the maximum capacitance (Cmax) states with a wide tuning range, but it has a poor linearity performance due to the voltage dependent nonlinear capacitance. In case of the digitally controlled switched capacitor array, while it shows a very good linearity, its g-factor in Cmin state is strongly dependent on the substrate loss by the parasitic junction capacitances between p-well, deep n-well, and p-substrate and the substrate resistance. To overcome the aforementioned drawbacks of the analog varactor and the switched capacitor array, the digitally controlled binary-weighted accumulation-mode varactor array (AVA) is proposed. In the simulation, at 2.4 GHz frequency band, the proposed tunable capacitor shows a g-factor of greater than 60 over all states and a tuning range of 3. The inverter-based push-pull power amplifier (PA) with the tunable matching network (TMN) employing the proposed tunable capacitor extends the impedance coverage maintaining the output power of greater than 0 dBm under the worst case for antenna impedance mismatch.
{"title":"A tunable power amplifier employing digitally controlled accumulation-mode varactor array for 2.4-GHz short-range wireless communication","authors":"Sanggil Kim, D. Im","doi":"10.1109/APCCAS.2016.7803951","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803951","url":null,"abstract":"The most popular tunable capacitor topologies in CMOS are the analog varactor and digitally controlled switched capacitor array (SCA). The conventional analog varactor shows a high quality factor (g-factor) in both the minimum capacitance (Cmin) and the maximum capacitance (Cmax) states with a wide tuning range, but it has a poor linearity performance due to the voltage dependent nonlinear capacitance. In case of the digitally controlled switched capacitor array, while it shows a very good linearity, its g-factor in Cmin state is strongly dependent on the substrate loss by the parasitic junction capacitances between p-well, deep n-well, and p-substrate and the substrate resistance. To overcome the aforementioned drawbacks of the analog varactor and the switched capacitor array, the digitally controlled binary-weighted accumulation-mode varactor array (AVA) is proposed. In the simulation, at 2.4 GHz frequency band, the proposed tunable capacitor shows a g-factor of greater than 60 over all states and a tuning range of 3. The inverter-based push-pull power amplifier (PA) with the tunable matching network (TMN) employing the proposed tunable capacitor extends the impedance coverage maintaining the output power of greater than 0 dBm under the worst case for antenna impedance mismatch.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"6 1","pages":"269-272"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74404135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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