Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803950
W. Lai, Jhe-Wei Jhuang, S. Jang, Guan-Yu Lin, C. Hsue
This letter proposes a dual-resonance CMOS LC-tank injection locked frequency doubler (ILFD) fabricated in the 0.18 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFD. The ILFD circuit is composed of a RLC dual-resonance first-harmonic injection-locked oscillator (ILO), a wide-band frequency doubler with differential-injection ports. The ILFD uses resistors to degrade the resonator quality factor and enhance the locking range. At the supply voltage of 1.65 V, the dc power consumption is 7.71 mW. At the incident power of 0 dBm, the ILFD has locking range from the incident frequency 3.9 GHz to 8.2 GHz.
{"title":"Wide-band injection-locked frequency doubler","authors":"W. Lai, Jhe-Wei Jhuang, S. Jang, Guan-Yu Lin, C. Hsue","doi":"10.1109/APCCAS.2016.7803950","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803950","url":null,"abstract":"This letter proposes a dual-resonance CMOS LC-tank injection locked frequency doubler (ILFD) fabricated in the 0.18 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFD. The ILFD circuit is composed of a RLC dual-resonance first-harmonic injection-locked oscillator (ILO), a wide-band frequency doubler with differential-injection ports. The ILFD uses resistors to degrade the resonator quality factor and enhance the locking range. At the supply voltage of 1.65 V, the dc power consumption is 7.71 mW. At the incident power of 0 dBm, the ILFD has locking range from the incident frequency 3.9 GHz to 8.2 GHz.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"73 1","pages":"265-268"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85814008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803972
Junjie Kong, S. Henzler, D. Schmitt-Landsiedel, L. Siek
This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be −0.097/0.2 LSB and −0.12/0.41 LSB respectively.
{"title":"A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC","authors":"Junjie Kong, S. Henzler, D. Schmitt-Landsiedel, L. Siek","doi":"10.1109/APCCAS.2016.7803972","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803972","url":null,"abstract":"This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be −0.097/0.2 LSB and −0.12/0.41 LSB respectively.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"46 1","pages":"348-351"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85880261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804085
Tobias Tired, H. Sjöland, Göran Jönsson, J. Wernehag
This paper presents simulation and measurement results for two 2-stage E-band power amplifiers implemented in 0.18 μm SiGe technology with fr = 200 GHz. To increase the power gain by mitigating the effect of the base-collector capacitance, the first design uses a differential cascode topology with a 2.7 V supply voltage. The second design instead uses capacitive cross-coupling of a differential common emitter stage, previously not demonstrated in mm-wave SiGe PAs, and has a supply voltage of only 1.5 V. Low supply voltage is advantageous since a common supply can then be shared between the transceiver and the PA. To maximize the power gain and robustness, both designs use a transformer based interstage matching. The cascode design achieves a measured power gain, S21, of 16 dB at 92 GHz with 17 GHz 3-dB bandwidth, and a simulated saturated output power, Psat, of 17 dBm with a 16% peak PAE. The cross-coupled design achieves a measured S21 of 10 dB at 93 GHz with 16 GHz 3-dB bandwidth, and a simulated Psat, of 15 dBm with 16% peak PAE. Comparing the measured and simulated results for the two amplifier architectures, the cascode topology is more robust, while the cross-coupled topology would benefit from a programmable cross-coupling capacitance.
{"title":"Comparison of two SiGe 2-stage E-band power amplifier architectures","authors":"Tobias Tired, H. Sjöland, Göran Jönsson, J. Wernehag","doi":"10.1109/APCCAS.2016.7804085","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804085","url":null,"abstract":"This paper presents simulation and measurement results for two 2-stage E-band power amplifiers implemented in 0.18 μm SiGe technology with fr = 200 GHz. To increase the power gain by mitigating the effect of the base-collector capacitance, the first design uses a differential cascode topology with a 2.7 V supply voltage. The second design instead uses capacitive cross-coupling of a differential common emitter stage, previously not demonstrated in mm-wave SiGe PAs, and has a supply voltage of only 1.5 V. Low supply voltage is advantageous since a common supply can then be shared between the transceiver and the PA. To maximize the power gain and robustness, both designs use a transformer based interstage matching. The cascode design achieves a measured power gain, S21, of 16 dB at 92 GHz with 17 GHz 3-dB bandwidth, and a simulated saturated output power, Psat, of 17 dBm with a 16% peak PAE. The cross-coupled design achieves a measured S21 of 10 dB at 93 GHz with 16 GHz 3-dB bandwidth, and a simulated Psat, of 15 dBm with 16% peak PAE. Comparing the measured and simulated results for the two amplifier architectures, the cascode topology is more robust, while the cross-coupled topology would benefit from a programmable cross-coupling capacitance.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"99 1","pages":"666-669"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78607781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803931
Sanghun Kim, C. Jang, Young Hwan Kim
In this paper, we propose a new stereo confidence metric, weighted peak ratio. Unlike existing confidence metrics, it computes the confidence level using the costs of surrounding pixels and given weights based on the color similarity between the pixels. In the experimental results, the proposed confidence metric showed better performance in detecting outliers compared to the state-of-the-art confidence metric, average peak ratio. Especially, the proposed metric is effective in object boundary regions.
{"title":"Weighted peak ratio for estimating stereo confidence level using color similarity","authors":"Sanghun Kim, C. Jang, Young Hwan Kim","doi":"10.1109/APCCAS.2016.7803931","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803931","url":null,"abstract":"In this paper, we propose a new stereo confidence metric, weighted peak ratio. Unlike existing confidence metrics, it computes the confidence level using the costs of surrounding pixels and given weights based on the color similarity between the pixels. In the experimental results, the proposed confidence metric showed better performance in detecting outliers compared to the state-of-the-art confidence metric, average peak ratio. Especially, the proposed metric is effective in object boundary regions.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"348 1","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78949835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803964
Andrea Bandiziol, W. Grollitsch, F. Brandonisio, R. Nonis, P. Palestri
This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given. The proposed transmitter features feed-forward equalization with 8 taps (1 pre-cursor and 6 post-cursors, plus the main tap), whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area. The proposed architecture is also able to tune its output impedance independently from the choice of the weights of the equalization tap. It features a 300 mV peak-to-peak eye diagram with 16 equalization levels and achieves a remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit for the predriver+driver).
{"title":"Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers","authors":"Andrea Bandiziol, W. Grollitsch, F. Brandonisio, R. Nonis, P. Palestri","doi":"10.1109/APCCAS.2016.7803964","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803964","url":null,"abstract":"This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given. The proposed transmitter features feed-forward equalization with 8 taps (1 pre-cursor and 6 post-cursors, plus the main tap), whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area. The proposed architecture is also able to tune its output impedance independently from the choice of the weights of the equalization tap. It features a 300 mV peak-to-peak eye diagram with 16 equalization levels and achieves a remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit for the predriver+driver).","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"321-324"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79132582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803941
Kento Endo, Norikazu Takahashi
Algebraic connectivity of a network, which is defined as the second smallest eigenvalue of the Laplacian matrix, represents how strongly the network is connected. This paper proposes a new decentralized discrete-time algorithm for the estimation of the algebraic connectivity of multiagent networks. The validity of the proposed algorithm is verified by theoretical analysis and numerical experiments.
{"title":"A new decentralized discrete-time algorithm for estimating algebraic connectivity of multiagent networks","authors":"Kento Endo, Norikazu Takahashi","doi":"10.1109/APCCAS.2016.7803941","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803941","url":null,"abstract":"Algebraic connectivity of a network, which is defined as the second smallest eigenvalue of the Laplacian matrix, represents how strongly the network is connected. This paper proposes a new decentralized discrete-time algorithm for the estimation of the algebraic connectivity of multiagent networks. The validity of the proposed algorithm is verified by theoretical analysis and numerical experiments.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"232-235"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77485849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804026
Jong-Seok Kim, Jin-O. Yoon, B. Choi
A 10b LCD column driver with resistor-resistor string DAC (RRDAC) is proposed having 0.24, 0.37 LSB of DNL and INL, and 17.4% of area shrinkage compared with an 8b LCD column driver with traditional resistor string DACs. To resolve the problems of the previous RRDACs such as power consumption increase, and inapplicability for nonlinear gamma curve, we propose an RRDAC using voltage-drop compensated coarse decoders.
{"title":"A low-area 10b column driver with resistor-resistor-string DAC for mobile active-matrix LCDs","authors":"Jong-Seok Kim, Jin-O. Yoon, B. Choi","doi":"10.1109/APCCAS.2016.7804026","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804026","url":null,"abstract":"A 10b LCD column driver with resistor-resistor string DAC (RRDAC) is proposed having 0.24, 0.37 LSB of DNL and INL, and 17.4% of area shrinkage compared with an 8b LCD column driver with traditional resistor string DACs. To resolve the problems of the previous RRDACs such as power consumption increase, and inapplicability for nonlinear gamma curve, we propose an RRDAC using voltage-drop compensated coarse decoders.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"28 7","pages":"548-550"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91437876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803921
Chun-Wei Chen, Fang-Kai Hsu, Der-Wei Yang, Jonas Wang, Ming-Der Shieh
Single-image super-resolution is widely adopted for high resolution display related applications. Example learning-based approaches can provide plenty of image details by using trained dataset. Regression-based methods reduce the memory storage size by training mapping functions instead of using a huge dictionary. The reconstructed image quality can be further enhanced by combining various prediction results. This work presents an effective model reconstruction method for enhanced predictions. The desired model can be constructed offline when using the local multi-gradient level pattern as the clustering feature. Applying the proposed schemes can further improve the quality of reconstructed high resolution image while retaining almost the same time complexity as the original solution. Experimental results exhibit that the quality of reconstructed image using the proposed schemes is very close to that of Yang's work, but the proposed one can operate much faster than his solutions. Moreover, the space for storing mapping functions can be dramatically reduced by using the proposed model combining method.
{"title":"Effective model construction for enhanced prediction in example-based super-resolution","authors":"Chun-Wei Chen, Fang-Kai Hsu, Der-Wei Yang, Jonas Wang, Ming-Der Shieh","doi":"10.1109/APCCAS.2016.7803921","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803921","url":null,"abstract":"Single-image super-resolution is widely adopted for high resolution display related applications. Example learning-based approaches can provide plenty of image details by using trained dataset. Regression-based methods reduce the memory storage size by training mapping functions instead of using a huge dictionary. The reconstructed image quality can be further enhanced by combining various prediction results. This work presents an effective model reconstruction method for enhanced predictions. The desired model can be constructed offline when using the local multi-gradient level pattern as the clustering feature. Applying the proposed schemes can further improve the quality of reconstructed high resolution image while retaining almost the same time complexity as the original solution. Experimental results exhibit that the quality of reconstructed image using the proposed schemes is very close to that of Yang's work, but the proposed one can operate much faster than his solutions. Moreover, the space for storing mapping functions can be dramatically reduced by using the proposed model combining method.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"14 1","pages":"156-159"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86027096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804050
Minh Hai Tran, Kosuke Oi, Y. Uwate, Y. Nishio
In many cases, mutual synchronization systems consisting of a large number of oscillators are used for practical model. In this work, we investigate synchronization phenomena observed by adding different frequency van der Pol oscillators coupled with star combination. By computer simulations, we confirm some of oscillators in the system are synchronized at anti-phase.
{"title":"Synchronization phenomena in star-coupled van der pol oscillators by adding different frequency oscillators","authors":"Minh Hai Tran, Kosuke Oi, Y. Uwate, Y. Nishio","doi":"10.1109/APCCAS.2016.7804050","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804050","url":null,"abstract":"In many cases, mutual synchronization systems consisting of a large number of oscillators are used for practical model. In this work, we investigate synchronization phenomena observed by adding different frequency van der Pol oscillators coupled with star combination. By computer simulations, we confirm some of oscillators in the system are synchronized at anti-phase.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"76 1","pages":"629-632"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86087823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803938
Daisuke Oku, M. Yanagisawa, N. Togawa
Scan-path test, which is one of design-for-test techniques using a scan chain, can control and observe internal registers in an LSI chip. However, attackers can also use it to retrieve secret information from cipher circuits. Recently, scan-based attacks using a scan chain inside an LSI chip is reported which can restore secret information by analyzing the scan data during cryptographic processing. In this paper, we pick up a scan-based attack method against a Trivium cipher, one of synchronous stream ciphers, and evaluate it using the FPGA platform called SASEBO-GII. We implement the Trivium cipher on the FPGA chip and perform the scan-based attack against it. We demonstrate that the scan-based attack can successfully restore the secret information in the FPGA chip within several minutes, even if the FPGA chip contains several circuits other than the Trivium cipher circuit, which reveals that the scan-based attack against the Trivium cipher is not only a simulation threat but a real threat.
{"title":"Implementation evaluation of scan-based attack against a Trivium cipher circuit","authors":"Daisuke Oku, M. Yanagisawa, N. Togawa","doi":"10.1109/APCCAS.2016.7803938","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803938","url":null,"abstract":"Scan-path test, which is one of design-for-test techniques using a scan chain, can control and observe internal registers in an LSI chip. However, attackers can also use it to retrieve secret information from cipher circuits. Recently, scan-based attacks using a scan chain inside an LSI chip is reported which can restore secret information by analyzing the scan data during cryptographic processing. In this paper, we pick up a scan-based attack method against a Trivium cipher, one of synchronous stream ciphers, and evaluate it using the FPGA platform called SASEBO-GII. We implement the Trivium cipher on the FPGA chip and perform the scan-based attack against it. We demonstrate that the scan-based attack can successfully restore the secret information in the FPGA chip within several minutes, even if the FPGA chip contains several circuits other than the Trivium cipher circuit, which reveals that the scan-based attack against the Trivium cipher is not only a simulation threat but a real threat.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"15 1","pages":"220-223"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81833221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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