Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803950
W. Lai, Jhe-Wei Jhuang, S. Jang, Guan-Yu Lin, C. Hsue
This letter proposes a dual-resonance CMOS LC-tank injection locked frequency doubler (ILFD) fabricated in the 0.18 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFD. The ILFD circuit is composed of a RLC dual-resonance first-harmonic injection-locked oscillator (ILO), a wide-band frequency doubler with differential-injection ports. The ILFD uses resistors to degrade the resonator quality factor and enhance the locking range. At the supply voltage of 1.65 V, the dc power consumption is 7.71 mW. At the incident power of 0 dBm, the ILFD has locking range from the incident frequency 3.9 GHz to 8.2 GHz.
{"title":"Wide-band injection-locked frequency doubler","authors":"W. Lai, Jhe-Wei Jhuang, S. Jang, Guan-Yu Lin, C. Hsue","doi":"10.1109/APCCAS.2016.7803950","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803950","url":null,"abstract":"This letter proposes a dual-resonance CMOS LC-tank injection locked frequency doubler (ILFD) fabricated in the 0.18 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFD. The ILFD circuit is composed of a RLC dual-resonance first-harmonic injection-locked oscillator (ILO), a wide-band frequency doubler with differential-injection ports. The ILFD uses resistors to degrade the resonator quality factor and enhance the locking range. At the supply voltage of 1.65 V, the dc power consumption is 7.71 mW. At the incident power of 0 dBm, the ILFD has locking range from the incident frequency 3.9 GHz to 8.2 GHz.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"73 1","pages":"265-268"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85814008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803972
Junjie Kong, S. Henzler, D. Schmitt-Landsiedel, L. Siek
This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be −0.097/0.2 LSB and −0.12/0.41 LSB respectively.
{"title":"A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC","authors":"Junjie Kong, S. Henzler, D. Schmitt-Landsiedel, L. Siek","doi":"10.1109/APCCAS.2016.7803972","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803972","url":null,"abstract":"This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be −0.097/0.2 LSB and −0.12/0.41 LSB respectively.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"46 1","pages":"348-351"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85880261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804085
Tobias Tired, H. Sjöland, Göran Jönsson, J. Wernehag
This paper presents simulation and measurement results for two 2-stage E-band power amplifiers implemented in 0.18 μm SiGe technology with fr = 200 GHz. To increase the power gain by mitigating the effect of the base-collector capacitance, the first design uses a differential cascode topology with a 2.7 V supply voltage. The second design instead uses capacitive cross-coupling of a differential common emitter stage, previously not demonstrated in mm-wave SiGe PAs, and has a supply voltage of only 1.5 V. Low supply voltage is advantageous since a common supply can then be shared between the transceiver and the PA. To maximize the power gain and robustness, both designs use a transformer based interstage matching. The cascode design achieves a measured power gain, S21, of 16 dB at 92 GHz with 17 GHz 3-dB bandwidth, and a simulated saturated output power, Psat, of 17 dBm with a 16% peak PAE. The cross-coupled design achieves a measured S21 of 10 dB at 93 GHz with 16 GHz 3-dB bandwidth, and a simulated Psat, of 15 dBm with 16% peak PAE. Comparing the measured and simulated results for the two amplifier architectures, the cascode topology is more robust, while the cross-coupled topology would benefit from a programmable cross-coupling capacitance.
{"title":"Comparison of two SiGe 2-stage E-band power amplifier architectures","authors":"Tobias Tired, H. Sjöland, Göran Jönsson, J. Wernehag","doi":"10.1109/APCCAS.2016.7804085","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804085","url":null,"abstract":"This paper presents simulation and measurement results for two 2-stage E-band power amplifiers implemented in 0.18 μm SiGe technology with fr = 200 GHz. To increase the power gain by mitigating the effect of the base-collector capacitance, the first design uses a differential cascode topology with a 2.7 V supply voltage. The second design instead uses capacitive cross-coupling of a differential common emitter stage, previously not demonstrated in mm-wave SiGe PAs, and has a supply voltage of only 1.5 V. Low supply voltage is advantageous since a common supply can then be shared between the transceiver and the PA. To maximize the power gain and robustness, both designs use a transformer based interstage matching. The cascode design achieves a measured power gain, S21, of 16 dB at 92 GHz with 17 GHz 3-dB bandwidth, and a simulated saturated output power, Psat, of 17 dBm with a 16% peak PAE. The cross-coupled design achieves a measured S21 of 10 dB at 93 GHz with 16 GHz 3-dB bandwidth, and a simulated Psat, of 15 dBm with 16% peak PAE. Comparing the measured and simulated results for the two amplifier architectures, the cascode topology is more robust, while the cross-coupled topology would benefit from a programmable cross-coupling capacitance.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"99 1","pages":"666-669"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78607781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803931
Sanghun Kim, C. Jang, Young Hwan Kim
In this paper, we propose a new stereo confidence metric, weighted peak ratio. Unlike existing confidence metrics, it computes the confidence level using the costs of surrounding pixels and given weights based on the color similarity between the pixels. In the experimental results, the proposed confidence metric showed better performance in detecting outliers compared to the state-of-the-art confidence metric, average peak ratio. Especially, the proposed metric is effective in object boundary regions.
{"title":"Weighted peak ratio for estimating stereo confidence level using color similarity","authors":"Sanghun Kim, C. Jang, Young Hwan Kim","doi":"10.1109/APCCAS.2016.7803931","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803931","url":null,"abstract":"In this paper, we propose a new stereo confidence metric, weighted peak ratio. Unlike existing confidence metrics, it computes the confidence level using the costs of surrounding pixels and given weights based on the color similarity between the pixels. In the experimental results, the proposed confidence metric showed better performance in detecting outliers compared to the state-of-the-art confidence metric, average peak ratio. Especially, the proposed metric is effective in object boundary regions.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"348 1","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78949835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803964
Andrea Bandiziol, W. Grollitsch, F. Brandonisio, R. Nonis, P. Palestri
This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given. The proposed transmitter features feed-forward equalization with 8 taps (1 pre-cursor and 6 post-cursors, plus the main tap), whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area. The proposed architecture is also able to tune its output impedance independently from the choice of the weights of the equalization tap. It features a 300 mV peak-to-peak eye diagram with 16 equalization levels and achieves a remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit for the predriver+driver).
{"title":"Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers","authors":"Andrea Bandiziol, W. Grollitsch, F. Brandonisio, R. Nonis, P. Palestri","doi":"10.1109/APCCAS.2016.7803964","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803964","url":null,"abstract":"This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given. The proposed transmitter features feed-forward equalization with 8 taps (1 pre-cursor and 6 post-cursors, plus the main tap), whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area. The proposed architecture is also able to tune its output impedance independently from the choice of the weights of the equalization tap. It features a 300 mV peak-to-peak eye diagram with 16 equalization levels and achieves a remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit for the predriver+driver).","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"321-324"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79132582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803941
Kento Endo, Norikazu Takahashi
Algebraic connectivity of a network, which is defined as the second smallest eigenvalue of the Laplacian matrix, represents how strongly the network is connected. This paper proposes a new decentralized discrete-time algorithm for the estimation of the algebraic connectivity of multiagent networks. The validity of the proposed algorithm is verified by theoretical analysis and numerical experiments.
{"title":"A new decentralized discrete-time algorithm for estimating algebraic connectivity of multiagent networks","authors":"Kento Endo, Norikazu Takahashi","doi":"10.1109/APCCAS.2016.7803941","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803941","url":null,"abstract":"Algebraic connectivity of a network, which is defined as the second smallest eigenvalue of the Laplacian matrix, represents how strongly the network is connected. This paper proposes a new decentralized discrete-time algorithm for the estimation of the algebraic connectivity of multiagent networks. The validity of the proposed algorithm is verified by theoretical analysis and numerical experiments.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"232-235"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77485849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804026
Jong-Seok Kim, Jin-O. Yoon, B. Choi
A 10b LCD column driver with resistor-resistor string DAC (RRDAC) is proposed having 0.24, 0.37 LSB of DNL and INL, and 17.4% of area shrinkage compared with an 8b LCD column driver with traditional resistor string DACs. To resolve the problems of the previous RRDACs such as power consumption increase, and inapplicability for nonlinear gamma curve, we propose an RRDAC using voltage-drop compensated coarse decoders.
{"title":"A low-area 10b column driver with resistor-resistor-string DAC for mobile active-matrix LCDs","authors":"Jong-Seok Kim, Jin-O. Yoon, B. Choi","doi":"10.1109/APCCAS.2016.7804026","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804026","url":null,"abstract":"A 10b LCD column driver with resistor-resistor string DAC (RRDAC) is proposed having 0.24, 0.37 LSB of DNL and INL, and 17.4% of area shrinkage compared with an 8b LCD column driver with traditional resistor string DACs. To resolve the problems of the previous RRDACs such as power consumption increase, and inapplicability for nonlinear gamma curve, we propose an RRDAC using voltage-drop compensated coarse decoders.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"28 7","pages":"548-550"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91437876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803943
K. Sooksood
This paper presents novel bulk-driven current mirror and bulk-driven cascode current mirror. Bulk-driven technique is employed to overcome a threshold voltage limitation. High accuracy transfer characteristic over wide current range is achieved through a negative feedback. The proposed circuits are designed and simulated with a 0.18 μm CMOS technology. They operate at 1 V power supply. The simulation results show the headroom voltage of 0.11 V and 0.16 V for the proposed bulk driven current mirror and bulk driven cascode current mirror, respectively.
{"title":"Wide current range and high compliance-voltage bulk-driven current mirrors: Simple and cascode","authors":"K. Sooksood","doi":"10.1109/APCCAS.2016.7803943","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803943","url":null,"abstract":"This paper presents novel bulk-driven current mirror and bulk-driven cascode current mirror. Bulk-driven technique is employed to overcome a threshold voltage limitation. High accuracy transfer characteristic over wide current range is achieved through a negative feedback. The proposed circuits are designed and simulated with a 0.18 μm CMOS technology. They operate at 1 V power supply. The simulation results show the headroom voltage of 0.11 V and 0.16 V for the proposed bulk driven current mirror and bulk driven cascode current mirror, respectively.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"121 1","pages":"240-242"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73767727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804066
Yang Liu, Chenchang Zhan, Lidan Wang
This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.
{"title":"An ultra-low power CMOS subthreshold voltage reference without requiring resistors or BJTs","authors":"Yang Liu, Chenchang Zhan, Lidan Wang","doi":"10.1109/APCCAS.2016.7804066","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804066","url":null,"abstract":"This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"479 1","pages":"688-690"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77410192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803905
Sijie Pan, P. Mok
This paper proposes a single on/off reference tracking buck converter for DVFS application with a novel turning point prediction based on the turning point of the output voltage. The equation to determine the turning point of the output voltage for optimal reference tracking is analyzed and implemented by a current multiplier and divider circuit. In addition, a new reference tracking scheme is introduced to avoid undershoot of output voltage caused by load change. This work is simulated in a 0.13-μm CMOS process and simulation results show fast reference tracking capability with 1.48 μs/V for up reference tracking, 1.91 μs/V for down reference tracking, and effective reduction of the undershoot and overshoot problem.
{"title":"A single on/off reference tracking buck converter using turning point prediction for DVFS application","authors":"Sijie Pan, P. Mok","doi":"10.1109/APCCAS.2016.7803905","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803905","url":null,"abstract":"This paper proposes a single on/off reference tracking buck converter for DVFS application with a novel turning point prediction based on the turning point of the output voltage. The equation to determine the turning point of the output voltage for optimal reference tracking is analyzed and implemented by a current multiplier and divider circuit. In addition, a new reference tracking scheme is introduced to avoid undershoot of output voltage caused by load change. This work is simulated in a 0.13-μm CMOS process and simulation results show fast reference tracking capability with 1.48 μs/V for up reference tracking, 1.91 μs/V for down reference tracking, and effective reduction of the undershoot and overshoot problem.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"112 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76869774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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