Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573554
S. Mathew, Sudhir K. Satpathy, Vikram B. Suresh, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, Gregory K. Chen, R. Krishnamurthy, V. De
A 1024-bit delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential clock delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.
{"title":"A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS","authors":"S. Mathew, Sudhir K. Satpathy, Vikram B. Suresh, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, Gregory K. Chen, R. Krishnamurthy, V. De","doi":"10.1109/VLSIC.2016.7573554","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573554","url":null,"abstract":"A 1024-bit delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential clock delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"20 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84635790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573523
Yuan Du, Wei-Han Cho, Yilei Li, C. Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, S. Lee, Mau-Chung Frank Chang
A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.
{"title":"A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS","authors":"Yuan Du, Wei-Han Cho, Yilei Li, C. Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, S. Lee, Mau-Chung Frank Chang","doi":"10.1109/VLSIC.2016.7573523","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573523","url":null,"abstract":"A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"26 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89415053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573548
S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu
This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.
{"title":"An 8.865-GHz −244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique","authors":"S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu","doi":"10.1109/VLSIC.2016.7573548","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573548","url":null,"abstract":"This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"31 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89878509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573541
S. Saeedi, A. Emami-Neyestanak
In this work, a CMOS-SiPh optical transmitter based on carrier-injection ring modulators is presented. It features a novel low-power switched-capacitor-based pre-emphasis that effectively compensates the modulator bandwidth limitation. A wavelength stabilization technique via direct measurement of ring temperature using a monolithic PTAT sensor is also presented. The optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit consumes 0.29mW.
{"title":"A 10Gb/s, 342fJ/bit micro-ring modulator transmitter with switched-capacitor pre-emphasis and monolithic temperature sensor in 65nm CMOS","authors":"S. Saeedi, A. Emami-Neyestanak","doi":"10.1109/VLSIC.2016.7573541","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573541","url":null,"abstract":"In this work, a CMOS-SiPh optical transmitter based on carrier-injection ring modulators is presented. It features a novel low-power switched-capacitor-based pre-emphasis that effectively compensates the modulator bandwidth limitation. A wavelength stabilization technique via direct measurement of ring temperature using a monolithic PTAT sensor is also presented. The optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit consumes 0.29mW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75427175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573561
Seongjong Kim, J. P. Cerqueira, Mingoo Seok
We propose an error detection and correction technique based on local body swapping for eliminating the worst-case margin in near/sub-VTH non-instruction parallel architectures. We apply the proposed technique on an unsupervised waveform sorter for brain computer interface microsystems, improving energy-efficiency by 49.3% and throughput by 35.6% over the baseline that is margined for the worst-case variation. The area overhead is 4.1%.
{"title":"A 450mV timing-margin-free waveform sorter based on body swapping error correction","authors":"Seongjong Kim, J. P. Cerqueira, Mingoo Seok","doi":"10.1109/VLSIC.2016.7573561","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573561","url":null,"abstract":"We propose an error detection and correction technique based on local body swapping for eliminating the worst-case margin in near/sub-VTH non-instruction parallel architectures. We apply the proposed technique on an unsupervised waveform sorter for brain computer interface microsystems, improving energy-efficiency by 49.3% and throughput by 35.6% over the baseline that is margined for the worst-case variation. The area overhead is 4.1%.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"198 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78065310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573532
M. Eberlein, Idan Yahav
This paper describes an innovative architecture for temperature sensors, which achieves excellent linearity at minimum complexity. Fabricated in 28nm, the circuit occupies only 0.0038mm2 and draws 16μA from 1.8V, capable also for lower supplies. The 8-bit smart sensor operates from -20 to 130°C and utilizes the benefits of parasitic NPN transistor. Current-mode technique is adopted in a new way, which simplifies digital output and makes common error correction dispensable. Excellent PSRR and a raw accuracy of 1.8°C (3σ) is obtained without calibration, due to the inherent robustness against MOS mismatch. Precision can be increased to ~ +/-0.8°C by convenient single point soft-trimming. (smart thermal sensor, current-mode, NPN bipolar, CMOS)
{"title":"A 28nm CMOS ultra-compact thermal sensor in current-mode technique","authors":"M. Eberlein, Idan Yahav","doi":"10.1109/VLSIC.2016.7573532","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573532","url":null,"abstract":"This paper describes an innovative architecture for temperature sensors, which achieves excellent linearity at minimum complexity. Fabricated in 28nm, the circuit occupies only 0.0038mm2 and draws 16μA from 1.8V, capable also for lower supplies. The 8-bit smart sensor operates from -20 to 130°C and utilizes the benefits of parasitic NPN transistor. Current-mode technique is adopted in a new way, which simplifies digital output and makes common error correction dispensable. Excellent PSRR and a raw accuracy of 1.8°C (3σ) is obtained without calibration, due to the inherent robustness against MOS mismatch. Precision can be increased to ~ +/-0.8°C by convenient single point soft-trimming. (smart thermal sensor, current-mode, NPN bipolar, CMOS)","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86570675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573550
Yongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi
This paper presents a low-reference-spur and low-jitter injection-locked clock multiplier (ILCM). To secure these performances over PVT-variations, we propose the use of a voltage-domain period-calibrating loop (VDPCL) in the ILCM that monitors the intrinsic period of the VCO and stores this information as the charges in a capacitor. By evaluating the voltage of the capacitor, it is possible to correct the free-running frequency of the VCO. By iteratively accumulating charges, the precision of the calibration can be increased. The measured reference spur and RMS jitter were -59 dBc and 450 fs, respectively, and their degradations over the PVT were less than 1.5 dB and 50 fs, respectively.
{"title":"A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop","authors":"Yongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi","doi":"10.1109/VLSIC.2016.7573550","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573550","url":null,"abstract":"This paper presents a low-reference-spur and low-jitter injection-locked clock multiplier (ILCM). To secure these performances over PVT-variations, we propose the use of a voltage-domain period-calibrating loop (VDPCL) in the ILCM that monitors the intrinsic period of the VCO and stores this information as the charges in a capacitor. By evaluating the voltage of the capacitor, it is possible to correct the free-running frequency of the VCO. By iteratively accumulating charges, the precision of the calibration can be increased. The measured reference spur and RMS jitter were -59 dBc and 450 fs, respectively, and their degradations over the PVT were less than 1.5 dB and 50 fs, respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"2 38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88127492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573520
A. D. Hossain, Aurangozeb, Maruf Mohammad, Masum Hossain
This paper describes design technique of energy-efficient ADC-DSP less sequence detection and equalization. This scheme takes advantage of the ISI in the channel to reconstruct the time domain bit sequence. This concept is demonstrated with a 4-bit sequence decoder designed and fabricated in 65nm CMOS using only 4-data, 3-edge comparators. Consuming only 35 mW at 10 Gb/s and without any transmit equalization, this receiver is capable of compensating 27 dB channel loss with 90 mV Voltage margin and 25 ps timing margin at BER of 10-12.
{"title":"A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS","authors":"A. D. Hossain, Aurangozeb, Maruf Mohammad, Masum Hossain","doi":"10.1109/VLSIC.2016.7573520","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573520","url":null,"abstract":"This paper describes design technique of energy-efficient ADC-DSP less sequence detection and equalization. This scheme takes advantage of the ISI in the channel to reconstruct the time domain bit sequence. This concept is demonstrated with a 4-bit sequence decoder designed and fabricated in 65nm CMOS using only 4-data, 3-edge comparators. Consuming only 35 mW at 10 Gb/s and without any transmit equalization, this receiver is capable of compensating 27 dB channel loss with 90 mV Voltage margin and 25 ps timing margin at BER of 10-12.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"47 4","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91425292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573467
S. Zeinolabedin, A. Do, Dongsuk Jeon, D. Sylvester, T. T. Kim
This paper presents a power and area efficient processor for real-time neural spike-sorting. We propose a robust spike detector (SD), a feature extractor (FE), and an improved k-means algorithm for better clustering accuracy. Furthermore, time-multiplexing architecture is used in SD for dynamic power reduction. A customized 39kb 8T SRAM is also implemented to minimize leakage and storage area. The proposed processor consumes 0.175 μW/ch with leakage of 0.03 μW/ch at 0.54 V and area of 0.0033 mm2/ch.
{"title":"A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS","authors":"S. Zeinolabedin, A. Do, Dongsuk Jeon, D. Sylvester, T. T. Kim","doi":"10.1109/VLSIC.2016.7573467","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573467","url":null,"abstract":"This paper presents a power and area efficient processor for real-time neural spike-sorting. We propose a robust spike detector (SD), a feature extractor (FE), and an improved k-means algorithm for better clustering accuracy. Furthermore, time-multiplexing architecture is used in SD for dynamic power reduction. A customized 39kb 8T SRAM is also implemented to minimize leakage and storage area. The proposed processor consumes 0.175 μW/ch with leakage of 0.03 μW/ch at 0.54 V and area of 0.0033 mm2/ch.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"26 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79423223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573478
K. Blutman, A. Kapoor, A. Majumdar, Jacinto Garcia Martinez, J. Echeverri, L. Sevat, A. P. V. D. Wel, H. Fatemi, J. P. D. Gyvez, K. Makinwa
This paper presents a CMOS 40nm microcontroller where for the first time, stacked voltage domains are used. The system features an ARM Cortex M0+ processor, 4kB ROM, 16kB SRAM, peripherals, and an on-chip switched-capacitor voltage regulator (SCVR). By using voltage stacking the test chip achieves state-of-the-art (96%) power-conversion efficiency and observed power savings run from 23% to 63% depending upon the payload current, while supply voltage variations are reduced from 5.6mV to 3.8mV (RMS).
{"title":"A microcontroller with 96% power-conversion efficiency using stacked voltage domains","authors":"K. Blutman, A. Kapoor, A. Majumdar, Jacinto Garcia Martinez, J. Echeverri, L. Sevat, A. P. V. D. Wel, H. Fatemi, J. P. D. Gyvez, K. Makinwa","doi":"10.1109/VLSIC.2016.7573478","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573478","url":null,"abstract":"This paper presents a CMOS 40nm microcontroller where for the first time, stacked voltage domains are used. The system features an ARM Cortex M0+ processor, 4kB ROM, 16kB SRAM, peripherals, and an on-chip switched-capacitor voltage regulator (SCVR). By using voltage stacking the test chip achieves state-of-the-art (96%) power-conversion efficiency and observed power savings run from 23% to 63% depending upon the payload current, while supply voltage variations are reduced from 5.6mV to 3.8mV (RMS).","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"53 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79930285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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