Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573463
Koji Obata, Kazuo Matsukawa, Takuji Miki, Y. Tsukamoto, K. Sushihara
A 97.99 dB SNDR, 2 kHz bandwidth noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. Distortion due to mismatch of capacitive DAC is eliminated by introducing dynamic element matching (DEM) technique and by utilizing modulation dither effect. The ADC consumes 37.1 μW with 100 kHz sampling speed and achieves Schreier's figure of merit (FoMs) of 175.3 dB.
{"title":"A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect","authors":"Koji Obata, Kazuo Matsukawa, Takuji Miki, Y. Tsukamoto, K. Sushihara","doi":"10.1109/VLSIC.2016.7573463","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573463","url":null,"abstract":"A 97.99 dB SNDR, 2 kHz bandwidth noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. Distortion due to mismatch of capacitive DAC is eliminated by introducing dynamic element matching (DEM) technique and by utilizing modulation dither effect. The ADC consumes 37.1 μW with 100 kHz sampling speed and achieves Schreier's figure of merit (FoMs) of 175.3 dB.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"46 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78749928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573528
Amr Suleiman, Zhengdong Zhang, V. Sze
This paper presents a programmable, energy-efficient and real-time object detection accelerator using deformable parts models (DPM), with 2× higher accuracy than traditional rigid body models. With 8 deformable parts detection, three methods are used to address the high computational complexity: classification pruning for 33× fewer parts classification, vector quantization for 15× memory size reduction, and feature basis projection for 2× reduction of the cost of each classification. The chip is implemented in 65nm CMOS technology, and can process HD (1920×1080) images at 30fps without any off-chip storage while consuming only 58.6mW (0.94nJ/pixel, 1168 GOPS/W). The chip has two classification engines to simultaneously detect two different classes of objects. With a tested high throughput of 60fps, the classification engines can be time multiplexed to detect even more than two object classes. It is energy scalable by changing the pruning factor or disabling the parts classification.
{"title":"A 58.6mW real-time programmable object detector with multi-scale multi-object support using deformable parts model on 1920×1080 video at 30fps","authors":"Amr Suleiman, Zhengdong Zhang, V. Sze","doi":"10.1109/VLSIC.2016.7573528","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573528","url":null,"abstract":"This paper presents a programmable, energy-efficient and real-time object detection accelerator using deformable parts models (DPM), with 2× higher accuracy than traditional rigid body models. With 8 deformable parts detection, three methods are used to address the high computational complexity: classification pruning for 33× fewer parts classification, vector quantization for 15× memory size reduction, and feature basis projection for 2× reduction of the cost of each classification. The chip is implemented in 65nm CMOS technology, and can process HD (1920×1080) images at 30fps without any off-chip storage while consuming only 58.6mW (0.94nJ/pixel, 1168 GOPS/W). The chip has two classification engines to simultaneously detect two different classes of objects. With a tested high throughput of 60fps, the classification engines can be time multiplexed to detect even more than two object classes. It is energy scalable by changing the pruning factor or disabling the parts classification.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"5 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90441899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573497
Ruida Yun, James Sun, E. Gaalaas, Baoxing Chen
This paper presents a transformer-based digital isolator that achieves best-in-class robustness with 20kVPK surge capability and > 200kV/μS Common Mode Transient Immunity (CMTI). Using polyimide as insulation material, the isolation barrier is more than 30μm thick and enables the exceptional surge performance. The transformer is fully differential with symmetric layout to improve noise immunity. The OOK Transmitter (TX) is based on the negative-Gm oscillator and operates in the voltage-limited domain. It enable the TX to keep generating the differential On-Off Keying (OOK) carrier signal during disturbances from very fast Common Mode Transient (CMT) noise.
{"title":"A transformer-based digital isolator with 20kVPK surge capability and > 200kV/µS Common Mode Transient Immunity","authors":"Ruida Yun, James Sun, E. Gaalaas, Baoxing Chen","doi":"10.1109/VLSIC.2016.7573497","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573497","url":null,"abstract":"This paper presents a transformer-based digital isolator that achieves best-in-class robustness with 20kVPK surge capability and > 200kV/μS Common Mode Transient Immunity (CMTI). Using polyimide as insulation material, the isolation barrier is more than 30μm thick and enables the exceptional surge performance. The transformer is fully differential with symmetric layout to improve noise immunity. The OOK Transmitter (TX) is based on the negative-Gm oscillator and operates in the voltage-limited domain. It enable the TX to keep generating the differential On-Off Keying (OOK) carrier signal during disturbances from very fast Common Mode Transient (CMT) noise.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"48 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73613476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573552
Sudhir K. Satpathy, S. Mathew, Vikram B. Suresh, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, Gregory K. Chen, R. Krishnamurthy
A 10K-gate 4Gbps unified encrypt/decrypt SMS4 Chinese cryptographic accelerator is fabricated in 14nm tri-gate CMOS, operating at 1GHz, 750mV, 25°C with total power consumption of 12mW. Double-affine mapped Sbox circuits enable inverse computation using GF(24)2 data-path, resulting in 33% reduction in accelerator area by elimination of look-up tables (LUT). Optimal composite-field reduction polynomials, counter-assisted round constant generation circuits, and a hybrid data-path with in-line key-expansion provide additional 14% area saving over traditional designs resulting in a compact layout occupying 2445μm2. Low voltage optimizations enable robust sub-threshold operation down to 250mV, with peak energy-efficiency of 1.1Tbps/W measured at 330mV.
{"title":"250mV–950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS","authors":"Sudhir K. Satpathy, S. Mathew, Vikram B. Suresh, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, Gregory K. Chen, R. Krishnamurthy","doi":"10.1109/VLSIC.2016.7573552","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573552","url":null,"abstract":"A 10K-gate 4Gbps unified encrypt/decrypt SMS4 Chinese cryptographic accelerator is fabricated in 14nm tri-gate CMOS, operating at 1GHz, 750mV, 25°C with total power consumption of 12mW. Double-affine mapped Sbox circuits enable inverse computation using GF(24)2 data-path, resulting in 33% reduction in accelerator area by elimination of look-up tables (LUT). Optimal composite-field reduction polynomials, counter-assisted round constant generation circuits, and a hybrid data-path with in-line key-expansion provide additional 14% area saving over traditional designs resulting in a compact layout occupying 2445μm2. Low voltage optimizations enable robust sub-threshold operation down to 250mV, with peak energy-efficiency of 1.1Tbps/W measured at 330mV.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"60 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76250276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573483
S. Kim, C. Park, Youngky Kim, Seok-Ju Yun, Young-Jun Hong, Sang-Gug Lee
A novel 2.4-GHz Ternary Sequence Spread Spectrum (TSSS)-OOK Transceiver with spur suppression and dual-mode detection architecture is presented for the ULP wearable devices. A random bi-phase switching of a PA rejects the intrinsic spur of spread spectrum OOK TX by 22dB. A new TSSS-OOK TX supports spreading spectrum and dual reception of the coherent as well as non-coherent mode, implementing 12 dB SNR gain. The single-chip TSSS-OOK transceiver in 90nm CMOS occupies an active area of 2.1mm2 and measures 1 Mb/s, 22dB spur-suppressed output spectrum and 5.5% EVM at 2.17mW.
{"title":"A 2.4GHz ternary sequence spread spectrum OOK transceiver with harmonic spur suppression and dual-mode detection architecture for ULP wearable devices","authors":"S. Kim, C. Park, Youngky Kim, Seok-Ju Yun, Young-Jun Hong, Sang-Gug Lee","doi":"10.1109/VLSIC.2016.7573483","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573483","url":null,"abstract":"A novel 2.4-GHz Ternary Sequence Spread Spectrum (TSSS)-OOK Transceiver with spur suppression and dual-mode detection architecture is presented for the ULP wearable devices. A random bi-phase switching of a PA rejects the intrinsic spur of spread spectrum OOK TX by 22dB. A new TSSS-OOK TX supports spreading spectrum and dual reception of the coherent as well as non-coherent mode, implementing 12 dB SNR gain. The single-chip TSSS-OOK transceiver in 90nm CMOS occupies an active area of 2.1mm2 and measures 1 Mb/s, 22dB spur-suppressed output spectrum and 5.5% EVM at 2.17mW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78681839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573538
V. Ravinuthula, W. Bright, M. Weaver, K. Maclean, S. Kaylor, S. Balasubramanian, Jesse Coulon, Robert Keller, B. Nguyen, E. Dwobeng
We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1:1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 <;-65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and data/dummy-data scheme to minimize the pattern dependent sourcing/sinking of current on the DAC driver supply and ground. The DAC is fabricated in a 40nm dual-oxide CMOS process and dissipates 1.2W, with the contribution of the synthesized digital block and SerDes excluded.
{"title":"A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz","authors":"V. Ravinuthula, W. Bright, M. Weaver, K. Maclean, S. Kaylor, S. Balasubramanian, Jesse Coulon, Robert Keller, B. Nguyen, E. Dwobeng","doi":"10.1109/VLSIC.2016.7573538","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573538","url":null,"abstract":"We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1:1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 <;-65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and data/dummy-data scheme to minimize the pattern dependent sourcing/sinking of current on the DAC driver supply and ground. The DAC is fabricated in a 40nm dual-oxide CMOS process and dissipates 1.2W, with the contribution of the synthesized digital block and SerDes excluded.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"134 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77369602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573539
M. Raj, P. Upadhyaya, Y. Frans, Ken Chang
A dual-mode wide-band transformer based VCO is proposed. The two port impedance of the transformer based resonator is analyzed to derive the optimum primary to secondary capacitor load ratio, for robust mode selectivity and minimum power consumption. Fabricated in a 16nm FinFET technology, the design achieves 2.6× continuous tuning range spanning 7-to-18.3 GHz using a coil area of 120×150 μm2. The absence of lossy switches helps in maintaining phase noise of -112 to -100 dBc/Hz at 1 MHz offset, across the entire tuning range. The VCO consumes 3-4.4 mW and realizes power frequency tuning normalized figure of merit of 12.8 and 2.4 dB at 7 and 18.3 GHz respectively.
{"title":"A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET","authors":"M. Raj, P. Upadhyaya, Y. Frans, Ken Chang","doi":"10.1109/VLSIC.2016.7573539","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573539","url":null,"abstract":"A dual-mode wide-band transformer based VCO is proposed. The two port impedance of the transformer based resonator is analyzed to derive the optimum primary to secondary capacitor load ratio, for robust mode selectivity and minimum power consumption. Fabricated in a 16nm FinFET technology, the design achieves 2.6× continuous tuning range spanning 7-to-18.3 GHz using a coil area of 120×150 μm2. The absence of lossy switches helps in maintaining phase noise of -112 to -100 dBc/Hz at 1 MHz offset, across the entire tuning range. The VCO consumes 3-4.4 mW and realizes power frequency tuning normalized figure of merit of 12.8 and 2.4 dB at 7 and 18.3 GHz respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82866508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573470
Chao Chen, Zhao Chen, D. Bera, S. Raghunathan, M. Shabanimotlagh, Emile Noothout, Z. Chang, Jacco Ponte, C. Prins, H. Vos, J. Bosch, M. Verweij, N. Jong, M. Pertijs
This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.
{"title":"A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography","authors":"Chao Chen, Zhao Chen, D. Bera, S. Raghunathan, M. Shabanimotlagh, Emile Noothout, Z. Chang, Jacco Ponte, C. Prins, H. Vos, J. Bosch, M. Verweij, N. Jong, M. Pertijs","doi":"10.1109/VLSIC.2016.7573470","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573470","url":null,"abstract":"This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"7 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85696017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573533
H. Omran, Abdulaziz Alhoshany, H. Alahmadi, K. Salama
We propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area.
{"title":"A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation","authors":"H. Omran, Abdulaziz Alhoshany, H. Alahmadi, K. Salama","doi":"10.1109/VLSIC.2016.7573533","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573533","url":null,"abstract":"We propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"27 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87340938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573484
Y. Ogasawara, H. Sakurai, R. Fujimoto, K. Sami
A novel spur canceled clock generator (SCCG) capable of recovering RX sensitivity degradations caused by digital clocks in wireless SoCs is presented. Clock spurs which degrade RX sensitivity are canceled by applying the SCCG to the digital circuits or ADCs. The SCCG is integrated into a Bluetooth® smart SoC fabricated in a 65 nm CMOS process. Measured clock spur reduction of over 35 dB and RX sensitivity recovery of 4 dB are achieved. The power consumption and occupied area of the SCCG are only 18 μW and 40 μm × 120 μm, respectively.
{"title":"An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs","authors":"Y. Ogasawara, H. Sakurai, R. Fujimoto, K. Sami","doi":"10.1109/VLSIC.2016.7573484","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573484","url":null,"abstract":"A novel spur canceled clock generator (SCCG) capable of recovering RX sensitivity degradations caused by digital clocks in wireless SoCs is presented. Clock spurs which degrade RX sensitivity are canceled by applying the SCCG to the digital circuits or ADCs. The SCCG is integrated into a Bluetooth® smart SoC fabricated in a 65 nm CMOS process. Measured clock spur reduction of over 35 dB and RX sensitivity recovery of 4 dB are achieved. The power consumption and occupied area of the SCCG are only 18 μW and 40 μm × 120 μm, respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85154812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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