Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573540
Amit Jha, A. Ahmadi, S. Kshattry, T. Cao, K. Liao, G. Yeap, Y. Makris, K. O. Kenneth
A 4.3-GHz voltage controlled oscillator (VCO) using an addressable array of cross-coupled minimum size NMOS transistor pairs for post fabrication selection is demonstrated in 65-nm CMOS. An algorithm based on Hamming distance using the phase noise measurements of ~1,500 array combinations was used to identify combinations that have record phase noise of -130dBc/Hz at 1-MHz offset from a 4.3-GHz carrier, while consuming 5.2 mW from a 1-V supply. The operating frequency of circuits using post fabrication selection in its high frequency path is increased to 5 GHz.
{"title":"−197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS","authors":"Amit Jha, A. Ahmadi, S. Kshattry, T. Cao, K. Liao, G. Yeap, Y. Makris, K. O. Kenneth","doi":"10.1109/VLSIC.2016.7573540","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573540","url":null,"abstract":"A 4.3-GHz voltage controlled oscillator (VCO) using an addressable array of cross-coupled minimum size NMOS transistor pairs for post fabrication selection is demonstrated in 65-nm CMOS. An algorithm based on Hamming distance using the phase noise measurements of ~1,500 array combinations was used to identify combinations that have record phase noise of -130dBc/Hz at 1-MHz offset from a 4.3-GHz carrier, while consuming 5.2 mW from a 1-V supply. The operating frequency of circuits using post fabrication selection in its high frequency path is increased to 5 GHz.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"35 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76221960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573522
Ryan Boesch, Kevin Zheng, B. Murmann
A 0.003 mm2 5.2 mW/tap analog receive-side feedforward equalizer (RX-FFE) is demonstrated in 40 nm CMOS for up to 20 GBd ADC-based links. The FFE is constructed entirely with analog-inverter transconductors and capacitors, avoiding the use of area-intensive inductors. The delay element is implemented as a first-order Padé approximant of an ideal delay. The equalization performance is measured to be sufficient to relax the ADC resolution requirement by 1 bit. The total power consumed is less than 26 mW with less than 9.2 nV/√Hz output noise for all configurations.
{"title":"A 0.003 mm2 5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE","authors":"Ryan Boesch, Kevin Zheng, B. Murmann","doi":"10.1109/VLSIC.2016.7573522","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573522","url":null,"abstract":"A 0.003 mm2 5.2 mW/tap analog receive-side feedforward equalizer (RX-FFE) is demonstrated in 40 nm CMOS for up to 20 GBd ADC-based links. The FFE is constructed entirely with analog-inverter transconductors and capacitors, avoiding the use of area-intensive inductors. The delay element is implemented as a first-order Padé approximant of an ideal delay. The equalization performance is measured to be sufficient to relax the ADC resolution requirement by 1 bit. The total power consumed is less than 26 mW with less than 9.2 nV/√Hz output noise for all configurations.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"9 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76491973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573518
Minseob Shim, Seokhyeon Jeong, Paul D. Myers, S. Bang, Chulwoo Kim, D. Sylvester, D. Blaauw, Wanyeong Jung
This paper presents a new energy-efficient ring oscillator collapse-based comparator, which is demonstrated in a 15-bit SAR ADC. The comparator automatically adjusts comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. The employed SAR ADC supplements a 10-bit differential main CDAC with a 5-bit common-mode CDAC. This offers an additional 5 bits of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40nm CMOS shows 74.12 dB SNDR and 173.4 dB FOMs. The comparator consumes 104 nW with the full ADC consuming 1.17 μW.
{"title":"An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC","authors":"Minseob Shim, Seokhyeon Jeong, Paul D. Myers, S. Bang, Chulwoo Kim, D. Sylvester, D. Blaauw, Wanyeong Jung","doi":"10.1109/VLSIC.2016.7573518","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573518","url":null,"abstract":"This paper presents a new energy-efficient ring oscillator collapse-based comparator, which is demonstrated in a 15-bit SAR ADC. The comparator automatically adjusts comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. The employed SAR ADC supplements a 10-bit differential main CDAC with a 5-bit common-mode CDAC. This offers an additional 5 bits of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40nm CMOS shows 74.12 dB SNDR and 173.4 dB FOMs. The comparator consumes 104 nW with the full ADC consuming 1.17 μW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74349976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573525
Bert Moons, M. Verhelst
A low-power precision-scalable processor for ConvNets or convolutional neural networks (CNN) is implemented in a 40nm technology. Its 256 parallel processing units achieve a peak 102GOPS running at 204MHz. To minimize energy consumption while maintaining throughput, this works is the first to both exploit the sparsity of convolutions and to implement dynamic precision-scalability enabling supply- and energy scaling. The processor is fully C-programmable, consumes 25-288mW at 204 MHz and scales efficiency from 0.3-2.6 real TOPS/W. This system hereby outperforms the state-of-the-art up to 3.9× in energy efficiency.
{"title":"A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets","authors":"Bert Moons, M. Verhelst","doi":"10.1109/VLSIC.2016.7573525","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573525","url":null,"abstract":"A low-power precision-scalable processor for ConvNets or convolutional neural networks (CNN) is implemented in a 40nm technology. Its 256 parallel processing units achieve a peak 102GOPS running at 204MHz. To minimize energy consumption while maintaining throughput, this works is the first to both exploit the sparsity of convolutions and to implement dynamic precision-scalability enabling supply- and energy scaling. The processor is fully C-programmable, consumes 25-288mW at 204 MHz and scales efficiency from 0.3-2.6 real TOPS/W. This system hereby outperforms the state-of-the-art up to 3.9× in energy efficiency.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"501 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78136020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573471
P. Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, J. Im, Junho Cho, Kee Hian Tan, S. McLeod, S. Chen, Wenfeng Zhang, Y. Frans, Ken Chang
This paper describes the design of a low power fully-adaptive wideband, flexible reach transceiver in 16nm FinFET CMOS embedded within FPGA. The receiver utilizes a 3-stage CTLE with a segmented AGC to minimize parasitic peaking and 15-tap DFE to operate over both short and long channels. The transmitter uses a swing boosted CML driver architecture. Low noise wideband fractional N LC PLLs combined with linear active inductor based phase interpolators and high speed clocking are utilized for low jitter clock generation. The transceiver achieves >1200mVdpp TX swing with <;190 fs RJ and 5.39 ps TJ to achieve BER <; 10-15 over a 30 dB loss backplane at 32.75 Gb/s, while consuming 577 mW.
{"title":"A fully-adaptive wideband 0.5–32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology","authors":"P. Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, J. Im, Junho Cho, Kee Hian Tan, S. McLeod, S. Chen, Wenfeng Zhang, Y. Frans, Ken Chang","doi":"10.1109/VLSIC.2016.7573471","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573471","url":null,"abstract":"This paper describes the design of a low power fully-adaptive wideband, flexible reach transceiver in 16nm FinFET CMOS embedded within FPGA. The receiver utilizes a 3-stage CTLE with a segmented AGC to minimize parasitic peaking and 15-tap DFE to operate over both short and long channels. The transmitter uses a swing boosted CML driver architecture. Low noise wideband fractional N LC PLLs combined with linear active inductor based phase interpolators and high speed clocking are utilized for low jitter clock generation. The transceiver achieves >1200mVdpp TX swing with <;190 fs RJ and 5.39 ps TJ to achieve BER <; 10-15 over a 30 dB loss backplane at 32.75 Gb/s, while consuming 577 mW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83738871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573500
Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, B. Hu, C. Wong, Mau-Chung Frank Chang
A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.
{"title":"Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers","authors":"Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, B. Hu, C. Wong, Mau-Chung Frank Chang","doi":"10.1109/VLSIC.2016.7573500","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573500","url":null,"abstract":"A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90508275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573494
Qing Dong, Kaiyuan Yang, D. Blaauw, D. Sylvester
A sub-nW voltage reference is presented that uses only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation for LDOs and other applications in nW microsystems. Sixty chips from 3 different wafers in 180nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124ppm/°C from -40°C to 85°C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114pW at 25°C.
{"title":"A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems","authors":"Qing Dong, Kaiyuan Yang, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2016.7573494","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573494","url":null,"abstract":"A sub-nW voltage reference is presented that uses only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation for LDOs and other applications in nW microsystems. Sixty chips from 3 different wafers in 180nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124ppm/°C from -40°C to 85°C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114pW at 25°C.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"36 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90551359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573472
H. Miyaoka, Futoshi Terasawa, M. Kudo, H. Kano, A. Matsuda, N. Shirai, S. Kawai, T. Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, H. Yamaguchi, Toshihiko Mori, Y. Koyanagi, H. Tamura, Yutaka Ide, Kazuhiro Terashima, H. Higashi, Tomokazu Higuchi, N. Naka
28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).
{"title":"A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS","authors":"H. Miyaoka, Futoshi Terasawa, M. Kudo, H. Kano, A. Matsuda, N. Shirai, S. Kawai, T. Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, H. Yamaguchi, Toshihiko Mori, Y. Koyanagi, H. Tamura, Yutaka Ide, Kazuhiro Terashima, H. Higashi, Tomokazu Higuchi, N. Naka","doi":"10.1109/VLSIC.2016.7573472","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573472","url":null,"abstract":"28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"62 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91232057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573457
O. Temam
Amazing progress in machine-learning, largely based on deep neural networks, has started to make applications once considered impossible, such as real-time translation or self-driving cars, a reality. However, even if, on some restricted problems, machine-learning is getting close to human-level performance, we are still far from the capabilities of the human brain. Machine-learning researchers themselves acknowledge that the progress observed in the past 10 years has been largely due to rapid increase in computing performance, allowing to tackle larger neural networks and larger training sets. So the computer systems and circuits communities can play a very significant role in enabling future progress. While GPUs have been a major driver of this recent progress, both the slowing rate of improvement of standard CMOS technology and the need for even faster progress suggest to at least explore alternative approaches. In this talk, we will discuss lessons learned from research on architectures for machine-learning, and that some of the hurdles ahead largely lie at the circuit level, but can possibly be overcome in the near future.
{"title":"Enabling future progress in machine-learning","authors":"O. Temam","doi":"10.1109/VLSIC.2016.7573457","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573457","url":null,"abstract":"Amazing progress in machine-learning, largely based on deep neural networks, has started to make applications once considered impossible, such as real-time translation or self-driving cars, a reality. However, even if, on some restricted problems, machine-learning is getting close to human-level performance, we are still far from the capabilities of the human brain. Machine-learning researchers themselves acknowledge that the progress observed in the past 10 years has been largely due to rapid increase in computing performance, allowing to tackle larger neural networks and larger training sets. So the computer systems and circuits communities can play a very significant role in enabling future progress. While GPUs have been a major driver of this recent progress, both the slowing rate of improvement of standard CMOS technology and the need for even faster progress suggest to at least explore alternative approaches. In this talk, we will discuss lessons learned from research on architectures for machine-learning, and that some of the hurdles ahead largely lie at the circuit level, but can possibly be overcome in the near future.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"28 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87633218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573544
Hidetake Sugo, Shunichi Wakashima, R. Kuroda, Y. Yamashita, H. Sumi, Tzu-Jui Wang, Po-Sheng Chou, Ming-Chieh Hsu, S. Sugawa
An almost 100% temporal aperture (dead-time free) global shutter (GS) stacked CMOS image sensor (CIS) with in-pixel lateral overflow integration capacitor (LOFIC), ADC and DRAM is developed using pixel-wise connections. The prototype chip with 6.6μm-pitch VGA LOFIC pixel dead-time free GS mode and 1.65μm-pitch 4.9M sub-pixel high resolution rolling shutter (RS) mode was fabricated with a 45nm 1P4M CIS technology for PD substrate and a 65nm 1P5M CMOS technology for ASIC substrate.
{"title":"A dead-time free global shutter CMOS image sensor with in-pixel LOFIC and ADC using pixel-wis e connections","authors":"Hidetake Sugo, Shunichi Wakashima, R. Kuroda, Y. Yamashita, H. Sumi, Tzu-Jui Wang, Po-Sheng Chou, Ming-Chieh Hsu, S. Sugawa","doi":"10.1109/VLSIC.2016.7573544","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573544","url":null,"abstract":"An almost 100% temporal aperture (dead-time free) global shutter (GS) stacked CMOS image sensor (CIS) with in-pixel lateral overflow integration capacitor (LOFIC), ADC and DRAM is developed using pixel-wise connections. The prototype chip with 6.6μm-pitch VGA LOFIC pixel dead-time free GS mode and 1.65μm-pitch 4.9M sub-pixel high resolution rolling shutter (RS) mode was fabricated with a 45nm 1P4M CIS technology for PD substrate and a 65nm 1P5M CMOS technology for ASIC substrate.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79560291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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