Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573474
Y. Frans, Mohamed Elzeftawi, H. Hedayati, J. Im, V. Kireev, Toan Pham, Jaewook Shin, P. Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang
A 56Gb/s PAM4 wireline transceiver testchip is implemented in 16nm FinFET. The CML transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The receiver consists of continuous-time linear equalizers with constant DC-gain and a 28GSa/s 32-way time-interleaved SAR ADC. The transceiver achieves 1e-8 BER over a backplane channel with 25dB loss at 14GHz while consuming 550mW power, excluding DSP.
{"title":"A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET","authors":"Y. Frans, Mohamed Elzeftawi, H. Hedayati, J. Im, V. Kireev, Toan Pham, Jaewook Shin, P. Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang","doi":"10.1109/VLSIC.2016.7573474","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573474","url":null,"abstract":"A 56Gb/s PAM4 wireline transceiver testchip is implemented in 16nm FinFET. The CML transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The receiver consists of continuous-time linear equalizers with constant DC-gain and a 28GSa/s 32-way time-interleaved SAR ADC. The transceiver achieves 1e-8 BER over a backplane channel with 25dB loss at 14GHz while consuming 550mW power, excluding DSP.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"67 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86012279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573493
S. H. Shalmany, D. Draxelmayr, K. Makinwa
This paper presents an integrated shunt-based current-sensing system (CSS) capable of handling ±36A currents, the highest ever reported. It also achieves 0.3% gain error and 400μA offset, which is significantly better than the state-of-the-art. The heart of the system is a robust 260μΩ shunt made from the lead-frame of a standard HVQFN plastic package. The resulting voltage drop is then digitized by a ΔΣ ADC and a bandgap reference (BGR). At the expense of current handling capability, a ±5A version of the CSS uses a 10mΩ on-chip metal shunt to achieve just 4μA offset. Both designs were realized in a standard 0.13μm CMOS process.
{"title":"A ± 36A integrated current-sensing system with 0.3% gain error and 400µA offset from −55°C to +85°C","authors":"S. H. Shalmany, D. Draxelmayr, K. Makinwa","doi":"10.1109/VLSIC.2016.7573493","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573493","url":null,"abstract":"This paper presents an integrated shunt-based current-sensing system (CSS) capable of handling ±36A currents, the highest ever reported. It also achieves 0.3% gain error and 400μA offset, which is significantly better than the state-of-the-art. The heart of the system is a robust 260μΩ shunt made from the lead-frame of a standard HVQFN plastic package. The resulting voltage drop is then digitized by a ΔΣ ADC and a bandgap reference (BGR). At the expense of current handling capability, a ±5A version of the CSS uses a 10mΩ on-chip metal shunt to achieve just 4μA offset. Both designs were realized in a standard 0.13μm CMOS process.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85334469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573502
Jianhong Xiao, Weinan Gao, Xiaojing Xu, D. Chang, Jiang Cao, R. Sun, Vijayaramalingam Periasamy, N. Wang, Xi Chen, G. Unruh, Takayuki Hayashi, T. Chih, L. Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, B. Shen, Ardie G. Venes, D. Koh, J. Chang
A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7-13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.
{"title":"A 180 mW multistandard TV tuner in 28 nm CMOS","authors":"Jianhong Xiao, Weinan Gao, Xiaojing Xu, D. Chang, Jiang Cao, R. Sun, Vijayaramalingam Periasamy, N. Wang, Xi Chen, G. Unruh, Takayuki Hayashi, T. Chih, L. Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, B. Shen, Ardie G. Venes, D. Koh, J. Chang","doi":"10.1109/VLSIC.2016.7573502","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573502","url":null,"abstract":"A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7-13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"29 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85560807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573556
Jintao Zhang, Zhuo Wang, N. Verma
This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.
{"title":"A machine-learning classifier implemented in a standard 6T SRAM array","authors":"Jintao Zhang, Zhuo Wang, N. Verma","doi":"10.1109/VLSIC.2016.7573556","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573556","url":null,"abstract":"This paper presents a machine-learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g., from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS), where a 128×128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST-database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113× lower energy. The approach achieves accuracy >95% with a full feature set (i.e., 28×28=784 image pixels), and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations). The energy per 10-way digit classification is 633pJ at a speed of 50MHz.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81131897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573517
Yuanching Lien
A 12b time-interleaved pipelined SAR ADC is presented. The proposed sampling circuit makes timing skew immune to mismatch of control circuit for time interleaving and reduces the main mismatch source to only sampling switch to achieve very low sampling skew of 60fsrms without calibration. MDAC transfer curve of pipeline stage is folded and OP output is kept half without degrading its gain and bandwidth by the proposed MDAC. The proposed OP loading reset scheme also enhances the settling speed without sacrificing ADC conversion time. Operating at 800MS/s, this ADC consumes 14.6mW from 1V supply and achieves SNDR of 60.8dB with Nyquist input.
{"title":"A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration","authors":"Yuanching Lien","doi":"10.1109/VLSIC.2016.7573517","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573517","url":null,"abstract":"A 12b time-interleaved pipelined SAR ADC is presented. The proposed sampling circuit makes timing skew immune to mismatch of control circuit for time interleaving and reduces the main mismatch source to only sampling switch to achieve very low sampling skew of 60fsrms without calibration. MDAC transfer curve of pipeline stage is folded and OP output is kept half without degrading its gain and bandwidth by the proposed MDAC. The proposed OP loading reset scheme also enhances the settling speed without sacrificing ADC conversion time. Operating at 800MS/s, this ADC consumes 14.6mW from 1V supply and achieves SNDR of 60.8dB with Nyquist input.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81925466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573461
Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi
Programmable Logic (PL) with a high logic density is demonstrated by cross-bar (xbar) of atom switches, which are programmed through logic transistors. The PL has 4 4-input LUTs to minimize area-delay product owing to small area & capacitance of atom switch. Xbar with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm. 3× higher operation frequency and 40% lower power consumption are also assessed.
{"title":"A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond","authors":"Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi","doi":"10.1109/VLSIC.2016.7573461","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573461","url":null,"abstract":"Programmable Logic (PL) with a high logic density is demonstrated by cross-bar (xbar) of atom switches, which are programmed through logic transistors. The PL has 4 4-input LUTs to minimize area-delay product owing to small area & capacitance of atom switch. Xbar with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm. 3× higher operation frequency and 40% lower power consumption are also assessed.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79526447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573524
Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, Seong-Jin Jang, Byungsub Kim, J. Sim, Hong-June Park
The measured H-field EMI peak was reduced by around 15dB in a 4-wire single-ended DRAM interface by using a 3-level balanced coding scheme with a 100% pin efficiency. Charge-pump circuits are used to generate 3-level channel signals (-100mV, 0, +100mV) at TX. The RX input comparator uses the ground-level (0) as the voltage reference and employs the meta-stability to identify the ground-level input. The energy efficiency was 2.67pJ/b at 6.4Gb/s with a 65nm LP 1.2V CMOS process and 3-inch FR-4.
{"title":"A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme","authors":"Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, Seong-Jin Jang, Byungsub Kim, J. Sim, Hong-June Park","doi":"10.1109/VLSIC.2016.7573524","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573524","url":null,"abstract":"The measured H-field EMI peak was reduced by around 15dB in a 4-wire single-ended DRAM interface by using a 3-level balanced coding scheme with a 100% pin efficiency. Charge-pump circuits are used to generate 3-level channel signals (-100mV, 0, +100mV) at TX. The RX input comparator uses the ground-level (0) as the voltage reference and employs the meta-stability to identify the ground-level input. The energy efficiency was 2.67pJ/b at 6.4Gb/s with a 65nm LP 1.2V CMOS process and 3-inch FR-4.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"45 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78816046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573480
F. Kuo, S. Ferreira, M. Babaie, H. Chen, Lan-chou Cho, C. Jou, F. Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, R. Staszewski
We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low power consumption. A transmitter (TX) employs an all-digital PLL (ADPLL) with switched-current-source digitally controlled oscillator (DCO) and switching PA. An integrated on-chip matching network serves both PA and LNTA, thus allowing a 1-pin direct antenna connection with no external antenna filters. The transceiver consumes 2.75mW in RX and 3.6mW in TX when delivering 0 dBm in Bluetooth LE.
{"title":"A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter","authors":"F. Kuo, S. Ferreira, M. Babaie, H. Chen, Lan-chou Cho, C. Jou, F. Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, R. Staszewski","doi":"10.1109/VLSIC.2016.7573480","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573480","url":null,"abstract":"We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low power consumption. A transmitter (TX) employs an all-digital PLL (ADPLL) with switched-current-source digitally controlled oscillator (DCO) and switching PA. An integrated on-chip matching network serves both PA and LNTA, thus allowing a 1-pin direct antenna connection with no external antenna filters. The transceiver consumes 2.75mW in RX and 3.6mW in TX when delivering 0 dBm in Bluetooth LE.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77093093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573519
Sung-En Hsieh, C. Hsieh
A 0.3V 600KS/s 11b SAR ADC with semi-resting (SR) DAC, cascade-input (CI) comparator, and double rail-to-rail input range is implemented in 90nm CMOS. The SR DAC consumes only 6-13.5% switching energy of the state-of-the-art works. The CI comparator consumes only 49% of power and 66% of decision time with an ×3 front-stage gain boost. The prototype achieves a SNDR of 58.7dB, an ENOB of 9.46b, a power of 187nW, and a resulting FoM of 0.44fJ/conv.-step.
一个0.3V 600KS/s 11b SAR ADC，具有半静息(SR) DAC、级联输入(CI)比较器和双轨到轨输入范围。SR DAC消耗的开关能量仅为最先进器件的6-13.5%。CI比较器仅消耗49%的功率和66%的决策时间，并具有×3前置增益提升。该样机的SNDR为58.7dB, ENOB为9.46b，功率为187nW, FoM为0.44fJ/ vs .-step。
{"title":"A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC","authors":"Sung-En Hsieh, C. Hsieh","doi":"10.1109/VLSIC.2016.7573519","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573519","url":null,"abstract":"A 0.3V 600KS/s 11b SAR ADC with semi-resting (SR) DAC, cascade-input (CI) comparator, and double rail-to-rail input range is implemented in 90nm CMOS. The SR DAC consumes only 6-13.5% switching energy of the state-of-the-art works. The CI comparator consumes only 49% of power and 66% of decision time with an ×3 front-stage gain boost. The prototype achieves a SNDR of 58.7dB, an ENOB of 9.46b, a power of 187nW, and a resulting FoM of 0.44fJ/conv.-step.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"75 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76499245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573557
Mahsa Shoaran, Masoud Shahshahani, Masoud Farivar, J. Almajano, Amirhossein Shahshahani, A. Schmid, A. Bragin, Y. Leblebici, A. Emami-Neyestanak
We present a 16-channel seizure detection system-on-chip (SoC) with 0.92μW/channel power dissipation in a total area of 1.1mm2 including a closed-loop neural stimulator. A set of four features are extracted from the spatially filtered neural data to achieve a high detection accuracy at minimal hardware cost. The performance is demonstrated by early detection and termination of kainic acid-induced seizures in freely moving rats and by offline evaluation on human intracranial EEG (iEEG) data. Our design improves upon previous works by over 40× reduction in power-area product per channel. This improvement is a key step towards integration of larger arrays with higher spatiotemporal resolution to further boost the detection accuracy.
{"title":"A 16-channel 1.1mm2 implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS","authors":"Mahsa Shoaran, Masoud Shahshahani, Masoud Farivar, J. Almajano, Amirhossein Shahshahani, A. Schmid, A. Bragin, Y. Leblebici, A. Emami-Neyestanak","doi":"10.1109/VLSIC.2016.7573557","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573557","url":null,"abstract":"We present a 16-channel seizure detection system-on-chip (SoC) with 0.92μW/channel power dissipation in a total area of 1.1mm2 including a closed-loop neural stimulator. A set of four features are extracted from the spatially filtered neural data to achieve a high detection accuracy at minimal hardware cost. The performance is demonstrated by early detection and termination of kainic acid-induced seizures in freely moving rats and by offline evaluation on human intracranial EEG (iEEG) data. Our design improves upon previous works by over 40× reduction in power-area product per channel. This improvement is a key step towards integration of larger arrays with higher spatiotemporal resolution to further boost the detection accuracy.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87482263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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