Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573553
Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, D. Blaauw, D. Sylvester
An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage in conventional AES implementations and replaces flip-flops in data and key storage with latches using re-timing, saving 25% area and 69% power. Along with a 2-stage Sbox in native GF(24)2 composite-field computation and glitch reduction techniques, this results in a compact 2228 gate design achieving 446 Gbps/W and 46.2 Mbps throughput at 0.47V.
{"title":"A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm","authors":"Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2016.7573553","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573553","url":null,"abstract":"An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage in conventional AES implementations and replaces flip-flops in data and key storage with latches using re-timing, saving 25% area and 69% power. Along with a 2-stage Sbox in native GF(24)2 composite-field computation and glitch reduction techniques, this results in a compact 2228 gate design achieving 446 Gbps/W and 46.2 Mbps throughput at 0.47V.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83530181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573488
Ajit Sharma, Seung Bae Lee, Arup Polley, Sriram Narayanan, Wen Li, T. Sculley, S. Ramaswamy
A multi-modal analog front end (AFE) and ultra-low energy bio-sensing CMOS SoC is presented. System/ circuit techniques enable signal path duty cycles as low as sub-1% and result in a 35μA Photo Plethysmography (PPG) RX Chain - 5X lower than published state of the art - while maintaining overall SNR > 80dBFS. The signal chain is adaptively synchronized by an ultra-low power FSM and includes a 1.3μW 14b 1kSPS SAR A/D. Input signal-aware, real-time data path adaptation is achieved by leveraging on-the-fly algorithms running on an external microcontroller (μC) to further reduce system energy. A programmable, asynchronous capacitive reset amplifier (PARCA) with NEF of 4.8 and dx/dt analog feature extractor demonstrate energy efficient ECG capture. A battery-powered, Bluetooth low energy (BLE) based, wearable platform with simultaneous ECG and PPG acquisition using this AFE has been demonstrated.
提出了一种多模态模拟前端(AFE)和超低能量生物传感CMOS SoC。系统/电路技术使信号通路占空比低至低于1%，并产生35μA的光容积脉搏波(PPG) RX链-比目前公布的状态低5倍-同时保持总体信噪比> 80dBFS。信号链由超低功耗FSM自适应同步，包括1.3μW 14b 1kSPS SAR a /D。通过利用运行在外部微控制器(μC)上的动态算法来实现输入信号感知，实时数据路径自适应，以进一步降低系统能量。NEF为4.8的可编程异步电容复位放大器(PARCA)和dx/dt模拟特征提取器演示了高能效的心电捕获。一个基于电池供电、蓝牙低功耗(BLE)的可穿戴平台，使用该AFE同时进行ECG和PPG采集。
{"title":"Multi-modal smart bio-sensing SoC platform with >80dB SNR 35µA PPG RX chain","authors":"Ajit Sharma, Seung Bae Lee, Arup Polley, Sriram Narayanan, Wen Li, T. Sculley, S. Ramaswamy","doi":"10.1109/VLSIC.2016.7573488","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573488","url":null,"abstract":"A multi-modal analog front end (AFE) and ultra-low energy bio-sensing CMOS SoC is presented. System/ circuit techniques enable signal path duty cycles as low as sub-1% and result in a 35μA Photo Plethysmography (PPG) RX Chain - 5X lower than published state of the art - while maintaining overall SNR > 80dBFS. The signal chain is adaptively synchronized by an ultra-low power FSM and includes a 1.3μW 14b 1kSPS SAR A/D. Input signal-aware, real-time data path adaptation is achieved by leveraging on-the-fly algorithms running on an external microcontroller (μC) to further reduce system energy. A programmable, asynchronous capacitive reset amplifier (PARCA) with NEF of 4.8 and dx/dt analog feature extractor demonstrate energy efficient ECG capture. A battery-powered, Bluetooth low energy (BLE) based, wearable platform with simultaneous ECG and PPG acquisition using this AFE has been demonstrated.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"65 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90446418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573477
Se-un Shin, Min-Yong Jung, Kiduk Kim, Sang-Hui Park, Yeunhee Huh, Changsik Shin, Se-Hong Park, Jun-Suk Bang, Jong-Beom Baek, Sung-Won Choi, Yong-Min Ju, G. Cho
This paper presents a reconfigurable SIMO system with 10-output dual-bus DC-DC converter having two buses for heavy and light load outputs, respectively. The converter controls the load condition for each bus to be well balanced. Under diversified load condition, a group allocator assigns each output to the corresponding bus properly depending on its load current. Due to such load balancing function, severe regulation issues which could occur under diversified load condition are resolved with output voltage ripples below 25mV, and over 81% efficiency is achieved under wide range of load (0-300mA).
{"title":"A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load condition","authors":"Se-un Shin, Min-Yong Jung, Kiduk Kim, Sang-Hui Park, Yeunhee Huh, Changsik Shin, Se-Hong Park, Jun-Suk Bang, Jong-Beom Baek, Sung-Won Choi, Yong-Min Ju, G. Cho","doi":"10.1109/VLSIC.2016.7573477","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573477","url":null,"abstract":"This paper presents a reconfigurable SIMO system with 10-output dual-bus DC-DC converter having two buses for heavy and light load outputs, respectively. The converter controls the load condition for each bus to be well balanced. Under diversified load condition, a group allocator assigns each output to the corresponding bus properly depending on its load current. Due to such load balancing function, severe regulation issues which could occur under diversified load condition are resolved with output voltage ripples below 25mV, and over 81% efficiency is achieved under wide range of load (0-300mA).","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"65 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75978786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573506
Zhanping Chen, S. Kulkarni, V. Dorgan, U. Bhattacharya, Kevin Zhang
This work introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 0.9μm2 1T1R bit cell and bit level redundancy is presented. An array efficiency of 50% is achieved with hierarchical bit line design to separate fuse programming from read/sense. A power gating scheme is adopted to reduce leakage current consumption and reduce high voltage exposure for reliability. Program conditions can be optimized for HVM and in-field programming (IFP) to achieve close to 100% bit level yield.
{"title":"A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating","authors":"Zhanping Chen, S. Kulkarni, V. Dorgan, U. Bhattacharya, Kevin Zhang","doi":"10.1109/VLSIC.2016.7573506","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573506","url":null,"abstract":"This work introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 0.9μm2 1T1R bit cell and bit level redundancy is presented. An array efficiency of 50% is achieved with hierarchical bit line design to separate fuse programming from read/sense. A power gating scheme is adopted to reduce leakage current consumption and reduce high voltage exposure for reliability. Program conditions can be optimized for HVM and in-field programming (IFP) to achieve close to 100% bit level yield.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77796421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573503
Sangheon Lee, Jeonghwan Song, Chang-Gyeong Seong, J. Woo, Jong-Moon Choi, Soon-Chan Kwon, Hojoon Kim, Hyun-Suk Kang, S. Kim, Hoe Gwon Jung, K. Kwon, H. Hwang
In this report, a fully integrated 3-D cross-point ReRAM is demonstrated with minimized disturbance and sneak current effect. HfOX memory cells stacked on threshold-type selector exhibit superb leakage current suppression than cells with exponential selector. Remaining leakage current is diagnosed and compensated by leakage compensating write driver. Cells are prevented from disturbance by lowering read voltage at hot temperature, which sacrifices read margin. The read margin is recovered by cell current amplifier in read circuit.
{"title":"Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier","authors":"Sangheon Lee, Jeonghwan Song, Chang-Gyeong Seong, J. Woo, Jong-Moon Choi, Soon-Chan Kwon, Hojoon Kim, Hyun-Suk Kang, S. Kim, Hoe Gwon Jung, K. Kwon, H. Hwang","doi":"10.1109/VLSIC.2016.7573503","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573503","url":null,"abstract":"In this report, a fully integrated 3-D cross-point ReRAM is demonstrated with minimized disturbance and sneak current effect. HfOX memory cells stacked on threshold-type selector exhibit superb leakage current suppression than cells with exponential selector. Remaining leakage current is diagnosed and compensated by leakage compensating write driver. Cells are prevented from disturbance by lowering read voltage at hot temperature, which sacrifices read margin. The read margin is recovered by cell current amplifier in read circuit.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"67 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79545624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573545
Suyao Ji, Jing Pu, Byongchan Lim, M. Horowitz
To reduce power consumption in a CMOS imager readout path, we use partial settling of the column values into a SAR-ADC, creating a 320H×240V prototype sensor with two column-shared 10-bit ADCs, which consumes 2.2mW at 130 fps. The measured INL and DNL with a third order correction of partial settling behavior is +1.855LSB/-1.855LSB and +0.337LSB/-0.179LSB, respectively. The input referred readout noise is 5e- with a conversion gain of 90uV/e-.
{"title":"A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture","authors":"Suyao Ji, Jing Pu, Byongchan Lim, M. Horowitz","doi":"10.1109/VLSIC.2016.7573545","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573545","url":null,"abstract":"To reduce power consumption in a CMOS imager readout path, we use partial settling of the column values into a SAR-ADC, creating a 320H×240V prototype sensor with two column-shared 10-bit ADCs, which consumes 2.2mW at 130 fps. The measured INL and DNL with a third order correction of partial settling behavior is +1.855LSB/-1.855LSB and +0.337LSB/-0.179LSB, respectively. The input referred readout noise is 5e- with a conversion gain of 90uV/e-.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"9 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84817931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573460
M. Yabuuchi, Yohei Sawada, T. Sano, Y. Ishii, S. Tanaka, Miki Tanaka, K. Nii
High-density and low-leakage 1W1R 2-port (2P) SRAM is realized by 6T 1-port SRAM bitcell with double pumping internal clock in 16 nm FinFET technology. Proposed clock generator with address latch circuit enables robust timing design without sever setup/hold margin. We designed a 256 kb 1W1R 2P SRAM macro which achieves the highest density of 6.05 Mb/mm2. Measured data shows that a 313 ps of read-access-time is observed at 0.8 V. Standby leakage power in resume standby (RS) mode is reduced by 79% compared to the conventional dual-port SRAM without RS.
{"title":"A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time","authors":"M. Yabuuchi, Yohei Sawada, T. Sano, Y. Ishii, S. Tanaka, Miki Tanaka, K. Nii","doi":"10.1109/VLSIC.2016.7573460","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573460","url":null,"abstract":"High-density and low-leakage 1W1R 2-port (2P) SRAM is realized by 6T 1-port SRAM bitcell with double pumping internal clock in 16 nm FinFET technology. Proposed clock generator with address latch circuit enables robust timing design without sever setup/hold margin. We designed a 256 kb 1W1R 2P SRAM macro which achieves the highest density of 6.05 Mb/mm2. Measured data shows that a 313 ps of read-access-time is observed at 0.8 V. Standby leakage power in resume standby (RS) mode is reduced by 79% compared to the conventional dual-port SRAM without RS.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"33 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85834451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573531
B. Yousefzadeh, S. H. Shalmany, K. Makinwa
This paper presents the most accurate BJT-based CMOS temperature-to-digital converter (TDC) ever reported, with an inaccuracy of ±60mK (3σ) from -70°C to 125°C. This is 2× better than the state-of-the-art, despite being implemented in a process (160nm) that only offers low-βF (<;5) PNPs. It is also the most energy-efficient ever reported, with a resolution FOM of 7.3pJ°C2. This level of performance is achieved by an improved βF-compensation scheme, the use of dynamic error correction techniques to suppress non-BJT related errors and the use of an energy-efficient zoom-ADC based on current-reuse OTAs. These techniques also result in very low power-supply sensitivity (12mK/V), thus maintaining TDC accuracy for supply voltages ranging from 1.5V to 2V.
{"title":"A BJT-based temperature-to-digital converter with ±60mK (3σ) inaccuracy from −70°C to 125°C in 160nm CMOS","authors":"B. Yousefzadeh, S. H. Shalmany, K. Makinwa","doi":"10.1109/VLSIC.2016.7573531","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573531","url":null,"abstract":"This paper presents the most accurate BJT-based CMOS temperature-to-digital converter (TDC) ever reported, with an inaccuracy of ±60mK (3σ) from -70°C to 125°C. This is 2× better than the state-of-the-art, despite being implemented in a process (160nm) that only offers low-β<sub>F</sub> (<;5) PNPs. It is also the most energy-efficient ever reported, with a resolution FOM of 7.3pJ°C<sup>2</sup>. This level of performance is achieved by an improved β<sub>F</sub>-compensation scheme, the use of dynamic error correction techniques to suppress non-BJT related errors and the use of an energy-efficient zoom-ADC based on current-reuse OTAs. These techniques also result in very low power-supply sensitivity (12mK/V), thus maintaining TDC accuracy for supply voltages ranging from 1.5V to 2V.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86076393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573535
Benwei Xu, Yuan Zhou, Y. Chiu
We present a power- and area-efficient 24GS/s, 6b, 16-way time-interleaved (TI) ADC array, featuring a voltage-time (v/t) hybrid two-step structure for high-speed and low-power operation, a crosstalk-free SAR DAC topology and a non-hierarchical sampling frontend obviating reference and input buffers, respectively, for power and area savings. Background timing-skew calibration via dithering a reference ADC is also reported. Fabricated in 28nm CMOS, the prototype ADC array consumes 23mW at 24GS/s and measures an SNDR/SFDR of 35/54dB for a low-frequency input and 29/41dB for a Nyquist input, respectively. The core area of the ADC is 0.03mm2.
{"title":"A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS","authors":"Benwei Xu, Yuan Zhou, Y. Chiu","doi":"10.1109/VLSIC.2016.7573535","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573535","url":null,"abstract":"We present a power- and area-efficient 24GS/s, 6b, 16-way time-interleaved (TI) ADC array, featuring a voltage-time (v/t) hybrid two-step structure for high-speed and low-power operation, a crosstalk-free SAR DAC topology and a non-hierarchical sampling frontend obviating reference and input buffers, respectively, for power and area savings. Background timing-skew calibration via dithering a reference ADC is also reported. Fabricated in 28nm CMOS, the prototype ADC array consumes 23mW at 24GS/s and measures an SNDR/SFDR of 35/54dB for a low-frequency input and 29/41dB for a Nyquist input, respectively. The core area of the ADC is 0.03mm2.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86388803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-01DOI: 10.1109/VLSIC.2016.7573489
Takashi Shimizu, Y. Tomita, Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, David Thach, T. Miyoshi, Takayuki Baba, Yasuhiro Watanabe, A. Ike
We propose and demonstrate an FPGA-accelerated partial-image-matching engine for massive media-data searching systems. To take advantage of FPGA, a highly parallelized and pipelined architecture with an application-specific calculation was adopted. Our prototype system achieves 32 times better runtime performance than a CPU-based solution.
{"title":"An FPGA-accelerated partial image matching engine for massive media data searching systems","authors":"Takashi Shimizu, Y. Tomita, Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, David Thach, T. Miyoshi, Takayuki Baba, Yasuhiro Watanabe, A. Ike","doi":"10.1109/VLSIC.2016.7573489","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573489","url":null,"abstract":"We propose and demonstrate an FPGA-accelerated partial-image-matching engine for massive media-data searching systems. To take advantage of FPGA, a highly parallelized and pipelined architecture with an application-specific calculation was adopted. Our prototype system achieves 32 times better runtime performance than a CPU-based solution.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88418469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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